A gate drive monitoring circuit and device
By using the dead-time control and duty cycle compensation unit of the gate drive monitoring circuit, the problems of low adjustment flexibility and accuracy in the prior art are solved, and independent adjustment of the high-side and low-side MOSFETs is realized, improving the flexibility and accuracy of the circuit, and providing fault detection function.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HANGZHOU RUIMENG TECH
- Filing Date
- 2025-06-13
- Publication Date
- 2026-06-02
AI Technical Summary
Existing gate drive monitoring circuits cannot independently adjust the dead time of high-side and low-side MOSFETs, resulting in low adjustment flexibility and duty cycle accuracy. Furthermore, they are limited in function and do not consider blanking time or gate fault detection.
The gate drive monitoring circuit, including a gate drive feedback module and a gate drive monitoring module, is adopted. Through the dead time control unit and the duty cycle compensation unit, the independent dead time adjustment of the high-side and low-side MOSFETs is realized. Combined with the fault judgment function, the adjustment flexibility and duty cycle accuracy are improved.
It achieves automatic adjustment of the dead time of high-side and low-side MOSFETs, improving adjustment flexibility and duty cycle accuracy, reducing power consumption, possessing complex and diverse functions, and can detect gate faults in a timely manner to prevent device damage.
Smart Images
Figure CN224319237U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power electronics technology, specifically providing a gate drive monitoring circuit and device. Background Technology
[0002] Gate drive monitoring circuits are a key component of power electronic systems, primarily used to control and monitor the switching process of power semiconductor devices. In switching power supply circuits employing synchronous rectification technology, to ensure that the upper and lower transistors do not turn on simultaneously and to prevent punch-through damage to the circuit, a dead time needs to be set during the switching transition to protect the circuit's safe operation.
[0003] Existing gate drive monitoring circuits, such as the "Circuit, Method, and Switching Power Supply for Adaptive Dead Time Adjustment" disclosed in Chinese patent literature (publication number CN117792065A), consist of a second comparator, a counter, and a converter forming a dead time detection and adjustment module. By controlling the turn-on time of the lower MOSFET, it controls the dead time from the turn-off of the upper MOSFET to the turn-on of the lower MOSFET, thus solving the efficiency loss problem caused by excessively short or long dead times. However, this patent's technical solution can only automatically adjust the dead time of the low-side MOSFET, not the high-side MOSFET, resulting in low adjustment flexibility. Furthermore, the lack of duty cycle compensation leads to low duty cycle accuracy. Additionally, it does not consider blanking time and gate fault detection, thus only achieving a single function. Utility Model Content
[0004] To address the issues of low adjustment flexibility and duty cycle accuracy in existing technologies, which can only achieve single functions, this invention provides a gate drive monitoring circuit and device that can independently and automatically adjust the dead time of the high-side MOSFET and the low-side MOSFET, thereby improving adjustment flexibility, compensating for the duty cycle, improving the accuracy of the duty cycle, and enabling complex and diverse functions.
[0005] The specific solution of this utility model is as follows.
[0006] In a first aspect, a gate drive monitoring circuit includes a gate drive feedback module and a gate drive monitoring module connected to a gate drive module, wherein the gate drive feedback module is connected to the gate drive monitoring module; the gate drive monitoring module includes a dead time control unit and a duty cycle compensation unit, wherein the dead time control unit is connected between the gate drive module and the gate drive feedback module, and the duty cycle compensation unit is connected to the gate drive module.
[0007] The adaptive dead time implementation of the gate drive monitoring circuit of this utility model is achieved by removing the MOSFET turn-on and turn-off propagation delay when calculating the dead time, preventing the cross-conduction or breakdown of the high-side and low-side MOSFETs of the half-bridge, and minimizing the dead time at the same time. This reduces power consumption and enables independent automatic adjustment of the dead time by the high-side and low-side MOSFETs. The duty cycle compensation unit obtains the control signals and compensation dead time of the high-side and low-side MOSFET switches before duty cycle compensation, realizes duty cycle compensation, and improves duty cycle accuracy.
[0008] Furthermore, the gate driving module includes a high-side pre-drive circuit unit connected to the gate of the high-side MOSFET, and a low-side pre-drive circuit unit connected to the gate of the low-side MOSFET; the source of the high-side MOSFET is connected to the drain of the low-side MOSFET, the drain is connected to a power supply, and the source of the low-side MOSFET is grounded; the input terminals of the low-side pre-drive circuit unit and the high-side pre-drive circuit unit serve as the input terminals of the gate driving module. The switching of the high-side MOSFET is controlled by the high-side pre-drive circuit unit, and the switching of the low-side MOSFET is controlled by the low-side pre-drive circuit unit.
[0009] Furthermore, the gate driving module further includes a first diode D1 and a second diode D2; the anode of the first diode D1 is connected to the source of the high-side MOSFET, and the cathode is connected to the drain of the high-side MOSFET; the anode of the second diode D2 is connected to the source of the low-side MOSFET, and the cathode is connected to the drain of the low-side MOSFET. The gate and source of the high-side MOSFET and the low-side MOSFET are the output terminals of the gate driving module.
[0010] Furthermore, the gate drive feedback module includes a first comparator C1, a first current adjustment unit, and a first resistor R1; the gate drive monitoring module also includes a current adjustment register unit connected to the input terminal of the first current adjustment unit; the non-inverting input terminal of the first comparator C1 is connected to the gate of the high-side MOSFET, and the inverting input terminal is connected to the output terminal of the first current adjustment unit and the second terminal of the first resistor R1, respectively; the first terminal of the first resistor R1 is connected to the source of the high-side MOSFET and the drain of the low-side MOSFET, respectively.
[0011] Furthermore, the gate drive feedback module also includes a second comparator C2, a second current adjustment unit, and a second resistor R2; the current adjustment register unit is also connected to the input terminal of the second current adjustment unit; the non-inverting input terminal of the second comparator C2 is connected to the gate of the low-side MOSFET, the inverting input terminal is connected to the output terminal of the second current adjustment unit and the second terminal of the second resistor R2, and the first terminal of the second resistor R2 is connected to the source of the low-side MOSFET and ground respectively; the output terminals of the first comparator C1 and the second comparator C2 together serve as the output terminal of the gate drive feedback module.
[0012] In this module, the non-inverting input terminals of the first comparator C1 and the second comparator C2, as well as the first terminals of the first resistor R1 and the second resistor R2, serve as the first input terminals of the gate drive feedback module. The input terminals of the first current adjustment unit and the second current adjustment unit serve as the second input terminals of the gate drive feedback module. By setting up two comparators and two current adjustment units respectively, combined with the gate drive monitoring module, automatic adjustment of the dead time of the high-side MOSFET and the low-side MOSFET can be achieved independently, thereby improving adjustment flexibility.
[0013] Furthermore, the gate drive monitoring module also includes a first counter unit connected to the output terminal of the gate drive feedback module, and a drive control signal unit connected to the input terminal of the gate drive module; the output terminal of the dead time control unit is connected to the first input terminal of the drive control signal unit, and the input terminal is connected to the output terminal of the first counter unit.
[0014] Specifically, the first counter unit is used to count the first time of the high-side MOSFET and the low-side MOSFET; the dead time control unit is used to control the drive control signal unit to send the corresponding high-side MOSFET control signal and low-side MOSFET control signal to the input terminal of the gate drive module according to the actual dead time.
[0015] Furthermore, the gate drive monitoring module also includes a fault control unit connected to the output terminal of the gate drive feedback module and the second input terminal of the drive control signal unit; the fault control unit is also connected to a blanking time control unit; the blanking time control unit is also connected to a second counter unit.
[0016] The second counter unit is used to count the actual blanking time; the blanking time control unit is used to control the drive control signal unit to send the corresponding high-side MOSFET control signal and low-side MOSFET control signal to the gate drive module when the feedback signal does not follow the change of the control signal within the preset blanking time.
[0017] Furthermore, the duty cycle compensation unit is connected to the output terminal of the blanking time control unit and the second counter unit, as well as the third input terminal of the drive control signal unit. The duty cycle compensation unit is also connected to the output terminal of the drive control signal unit through the blanking time control unit.
[0018] The duty cycle compensation unit can obtain the control signals of the high-side and low-side MOSFET switches before duty cycle compensation through the blanking time control unit, as well as the compensation dead time of the second counter (this time is equal to the actual blanking time, so it is also directly obtained from the second counter), thereby controlling the drive control signal unit to send the corresponding high-side MOSFET control signal and low-side MOSFET control signal to the gate drive module.
[0019] In a second aspect, a gate drive monitoring device includes the gate drive monitoring circuit described above. The dead time control unit includes an adder / subtractor BU3 and an adder / subtractor CU4, a dead time register U5, and a dead time signal comparison and judgment U10. The duty cycle compensation unit includes a subtractor D U7 and a register D counting condition judgment unit U16.
[0020] Further, the first counter unit includes counter A U1 and counter A counting and reset condition judgment unit U14; the second counter unit includes counter B U2 and counter B counting and reset condition judgment unit U15; the blanking time control unit includes blanking time register U6 and blanking signal comparison and judgment U11; the current adjustment register unit includes high-side current adjustment register U8 and low-side current adjustment register U9; the drive control signal unit includes drive control logic processing unit U12; and the fault control unit includes fault judgment unit U13.
[0021] Therefore, this utility model has the following beneficial effects:
[0022] (1) The main functions of the gate drive monitoring circuit and device of this utility model are realized by digital circuits, which can realize more complex and diverse functions, and can effectively reduce chip area and reduce cost;
[0023] (2) The adaptive dead time is achieved by removing the propagation delay of MOSFET turn-on and turn-off when calculating the dead time, which prevents the high-side and low-side MOSFETs of the half-bridge from cross-conducting or breaking down, while minimizing the dead time, which can reduce power consumption and can independently realize the automatic adjustment of the dead time of the high-side MOSFET and the low-side MOSFET.
[0024] (3) The duty cycle compensation unit obtains the control signals and compensation dead time of the high-side and low-side MOSFET switches before duty cycle compensation, realizes duty cycle compensation, and improves duty cycle accuracy.
[0025] (4) The adaptive blanking time is taken into account and implemented together with the adaptive dead time. The implementation method is simple, which can not only improve the authenticity of fault detection, but also reduce the area and reduce the cost;
[0026] (5) A gate fault detection function is set up, which can detect effective faults in a timely manner when a gate fault occurs and take corresponding measures to prevent device damage. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0028] Figure 1 This is an overall circuit structure diagram of a gate drive monitoring circuit according to the present invention.
[0029] Figure 2 This is an overall block diagram of a gate drive monitoring circuit according to the present invention.
[0030] Figure 3 This is a circuit diagram of the gate driving module of this utility model.
[0031] Figure 4 This is a circuit diagram of the gate drive feedback module of this utility model.
[0032] Figure 5 This is a circuit diagram of the gate drive monitoring module of this utility model.
[0033] Figure 6 Circuit timing diagram provided for at least one embodiment of this utility model Figure 1 .
[0034] Figure 7 Circuit timing diagram provided for at least one embodiment of this utility model Figure 2 .
[0035] Figure 8 Circuit timing diagram provided for at least one embodiment of this utility model Figure 3 . Detailed Implementation
[0036] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.
[0037] Example 1.
[0038] This application provides a gate drive monitoring circuit, such as Figure 1 The diagram shown is an overall circuit structure diagram of a gate drive monitoring circuit according to this utility model. Figure 2 The diagram shows an overall block diagram of a gate drive monitoring circuit according to this invention. This embodiment of the gate drive monitoring circuit includes a gate drive feedback module and a gate drive monitoring module connected to a gate drive module. The gate drive feedback module is connected to the gate drive monitoring module.
[0039] like Figure 3 The diagram shows the circuit diagram of the gate driving module of this invention. The gate driving module includes a high-side MOSFET and a low-side MOSFET, wherein the source of the high-side MOSFET is connected to the drain of the low-side MOSFET, the drain of the high-side MOSFET is connected to the power supply, and the source of the low-side MOSFET is grounded. The gate of the high-side MOSFET is connected to the high-side pre-drive circuit unit, and the gate of the low-side MOSFET is connected to the low-side pre-drive circuit unit. That is, the high-side pre-drive circuit unit outputs the gate voltage of the high-side MOSFET, and the low-side pre-drive circuit unit outputs the gate voltage of the low-side MOSFET.
[0040] The gate drive module also includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the source of the high-side MOSFET, and the cathode of the first diode D1 is connected to the drain of the high-side MOSFET. The anode of the second diode D2 is connected to the source of the low-side MOSFET, and the cathode of the second diode D2 is connected to the drain of the low-side MOSFET. The first diode D1 and the second diode D2 are typically fast recovery diodes, which can shorten the turn-off time and reduce the turn-off loss.
[0041] Figure 3 In this context, VM represents the power supply voltage, GND represents ground, and V... GH V is the gate voltage of the high-side MOSFET. GL V is the gate voltage of the low-side MOSFET. SHThis represents the output phase voltage. The high-side MOSFET switch is controlled by the high-side MOSFET control signal GH_CTRL. If GH_CTRL is 0, the high-side MOSFET is off; if GH_CTRL is 1, the high-side MOSFET is on. Similarly, the low-side MOSFET switch is controlled by the low-side MOSFET control signal GL_CTRL. If GL_CTRL is 0, the low-side MOSFET is off; if GL_CTRL is 1, the low-side MOSFET is on. GH_CTRL and GL_CTRL are digital signals, while the others are analog signals.
[0042] like Figure 4 The diagram shown is a circuit diagram of the gate drive feedback module of this invention. The gate drive feedback module includes a first comparator C1, a second comparator C2, a first current adjustment unit, a second current adjustment unit, a first resistor R1, and a second resistor R2.
[0043] The non-inverting input of the first comparator C1 is connected to the gate of the high-side MOSFET, which is also connected to the output of the high-side pre-drive circuit unit. The inverting input of the first comparator C1 is connected to the output of the first current adjustment unit. The first end of the first resistor R1 is connected to the source of the high-side MOSFET and the drain of the low-side MOSFET, respectively. The second end of the first resistor R1 is connected to the inverting input of the first comparator C1 and the output of the first current adjustment unit, respectively.
[0044] The non-inverting input of the second comparator C2 is connected to the gate of the low-side MOSFET, which is the output of the low-side pre-drive circuit unit. The inverting input of the second comparator C2 is connected to the output of the second current adjustment unit. The first end of the second resistor R2 is connected to the source of the low-side MOSFET, which is grounded. The second end of the second resistor R2 is connected to the inverting input of the second comparator C2 and the output of the second current adjustment unit, respectively.
[0045] When V GH Less than I GH The product of R and V SH When the sum of and , then VGS_GH is 0; when V GH Greater than I GH The product of R and V SH When V and VGS_GH are equal, then VGS_GH is 1. GL Less than I GL When multiplied by R, VGS_GL is 0; when V GL Greater than I GL When multiplied by R, VGS_GL is 1. Where V GH V is the gate voltage of the high-side MOSFET. GL V is the gate voltage of the low-side MOSFET. SHThis is the output phase voltage. GH and I GL It is an adjustable current, controlled by the current adjustment register unit IGH_CTRL / IGL_CTRL in the gate drive monitoring module, where R is a fixed resistor and I... GH The product of R and I GL The product of VGS and R is generally between 1V and 1.4V, depending on the characteristics of the high-side and low-side MOSFETs. VGS_GH is the feedback signal sent to the gate drive monitoring corresponding to the high-side MOSFET, and VGS_GL is the feedback signal sent to the gate drive monitoring corresponding to the low-side MOSFET.
[0046] like Figure 1 As shown, the gate drive monitoring module further includes a dead-time control unit connected between the gate drive module and the gate drive feedback module, a first counter unit connected to the output terminal of the gate drive feedback module, and a drive control signal unit connected to the input terminal of the gate drive module. The output terminal of the dead-time control unit is connected to the first input terminal of the drive control signal unit, and the input terminal is connected to the output terminal of the first counter unit. The first counter unit is used to count the actual dead time of the high-side MOSFET and the low-side MOSFET. The dead-time control unit is used to control the drive control signal unit to send corresponding high-side MOSFET control signals and low-side MOSFET control signals to the input terminal of the gate drive module according to the actual dead time. The first counter unit includes a counter A U1 and a counter A counting and reset condition judgment unit U14. The output terminal of the counter A counting and reset condition judgment unit U14 is connected to the input terminal of counter A U1.
[0047] The gate drive monitoring module also includes a fault control unit connected to the output of the gate drive feedback module and the second input of the drive control signal unit; the fault control unit is also connected to a blanking time control unit; the blanking time control unit is also connected to a second counter unit. The second counter unit is used to count the actual blanking time; the blanking time control unit is used to control the drive control signal unit to send the corresponding high-side MOSFET control signal and low-side MOSFET control signal to the gate drive module when the feedback signal does not change with the control signal within the preset blanking time. After the preset blanking time, if the feedback signal VGS_GL does not change from 1 to 0 with GL_CTRL, it indicates that the MOSFET may be faulty or the gate voltage may be too high or too low. The fault control unit then considers a low-side MOSFET gate fault detected, disables the gate drive, and both GH_CTRL and GL_CTRL output 0. Similarly, after the preset blanking time Tblank, if the feedback signal VGS_GH does not change from 0 to 1 with GH_CTRL during the high-side MOSFET's open blanking period, the fault control unit considers a high-side MOSFET gate fault detected, and both GH_CTRL and GL_CTRL output 0.
[0048] The gate drive monitoring module also includes a duty cycle compensation unit. This unit is connected to the output of the blanking time control unit and the second counter unit, as well as the third input of the drive control signal unit. The duty cycle compensation unit is also connected to the output of the drive control signal unit via the blanking time control unit. Specifically, the duty cycle compensation unit obtains the control signals of the high-side and low-side MOSFET switches before duty cycle compensation, and the compensation dead time of the second counter (which is equal to the actual blanking time and is therefore directly obtained from the second counter), thereby controlling the drive control signal unit to send the corresponding high-side MOSFET control signals and low-side MOSFET control signals to the gate drive module.
[0049] The first counter unit includes counter A U1 and a counter A counting and reset condition judgment unit U14. The output of the counter A counting and reset condition judgment unit U14 is connected to the input of counter A U1. The second counter unit includes counter B U2 and a counter B counting and reset condition judgment unit U15. The output of the counter B counting and reset condition judgment unit U15 is connected to the input of counter B.
[0050] The current adjustment register unit includes a high-side current adjustment register U8 and a low-side current adjustment register U9. The output of the high-side current adjustment register U8 is connected to the input of the first current adjustment unit, and the output of the low-side current adjustment register U9 is connected to the input of the second current adjustment unit.
[0051] The dead time control unit includes a dead time register U5, an adder / subtractor BU3, an adder / subtractor CU4, and a dead time signal comparison and judgment unit U10. The output of the dead time register U5 is connected to the input of the adder / subtractor CU4. The outputs of the adder / subtractor BU3 and the adder / subtractor CU4 are respectively connected to the second and third inputs of the dead time signal comparison and judgment unit U10. The output of the dead time register U5 is connected to the fourth input of the dead time signal comparison and judgment unit U10. The first input of the dead time signal comparison and judgment unit U10 is connected to the output of the counter A U1.
[0052] The duty cycle compensation unit includes register D (counting condition judgment U16) and subtractor D (U7). The output of register D (counting condition judgment U16) is connected to the second input of subtractor D (U7), and the first input of subtractor D (U7) is connected to the output of counter B (U2).
[0053] The blanking time control unit includes a blanking time register U6 and a blanking signal comparison and judgment U11. The output of the blanking time register U6 is connected to the second input of the blanking signal comparison and judgment U11, and the first input of the blanking signal comparison and judgment U11 is connected to the output of the counter B U2.
[0054] The fault control unit includes a fault judgment unit U13, the input of which is connected to the output of the blanking signal comparison judgment U11.
[0055] The drive control signal unit includes a drive control logic processing unit U12. The first input of the drive control logic processing unit U12 is connected to the output of the dead-time signal comparison and judgment unit U10. The third input of the drive control logic processing unit U12 is connected to the output of the fault judgment unit U13. The second input of the drive control logic processing unit U12 is connected to the output of the subtractor D U7. The first output of the drive control logic processing unit U12 is connected to the input of the high-side pre-drive circuit unit, and the second output is connected to the input of the low-side pre-drive circuit unit.
[0056] The specific working process of the gate drive monitoring circuit is as follows.
[0057] Dead time and blanking time are fixed times that are set, such as Figure 6 The diagram shown is a circuit timing diagram of this embodiment. Figure 1Where Tdead is the set dead time and Tblank is the set blanking time. GH_CTRL is the control signal for the high-side MOSFET switch, and GL_CTRL is the control signal for the low-side MOSFET switch. When GH_CTRL is 1, it indicates that the high-side MOSFET switch is on; when GH_CTRL is 0, it indicates that the high-side MOSFET switch is off. Similarly, when GL_CTRL is 1, it indicates that the low-side MOSFET switch is on; when GL_CTRL is 0, it indicates that the low-side MOSFET switch is off. GH_BLANK is the high-side MOSFET blanking signal, and GL_BLANK is the low-side MOSFET blanking signal.
[0058] During the process of the low-side MOSFET being turned off and the high-side MOSFET being turned on, such as Figure 7 The diagram shown is a circuit timing diagram of this embodiment. Figure 2 Wherein, GH_CTRL is the control signal for the high-side MOSFET switch, and GL_CTRL is the control signal for the low-side MOSFET switch; GH_CTRL' is the control signal for the high-side MOSFET switch before duty cycle compensation; Tcnt is the time segment counted by counter A, and Tcnt2 is the time segment counted by counter B; Tdly is the propagation delay, and the two Tdly durations are not the same, but both are propagation delays; VGS_GH is the feedback signal sent to the gate drive monitoring module corresponding to the high-side MOSFET, and VGS_GL is the feedback signal sent to the gate drive monitoring module corresponding to the low-side MOSFET; GH_BLANK is the blanking signal for the high-side MOSFET, and GL_BLANK is the blanking signal for the low-side MOSFET; Tblank is the set blanking time.
[0059] When GL_CTRL changes from 1 to 0, GL_BLANK changes from 0 to 1, entering the low-side MOSFET blanking period, and counter B starts counting. Due to propagation delay and MOSFET charging / discharging delays, the actual turn-off time of the low-side MOSFET will be delayed compared to GL_CTRL. If the value of counter B, Tcnt2, equals Tblank, meaning that after the set blanking time, the feedback signal VGS_GL does not change from 1 to 0 following GL_CTRL, it indicates that the MOSFET may have a fault or the gate voltage may be too high or too low. In this case, the gate drive monitoring module will consider that a low-side MOSFET gate fault has been detected, and the gate drive will be disabled, with both GH_CTRL and GL_CTRL outputting 0. However, when the feedback signal VGS_GL changes from 1 to 0 within the set blanking time, it indicates that the low-side MOSFET is truly turned off. The dead time at which counter A is reset and starts counting will be the actual dead time used on the MOSFET. In other words, the dead time can be set small enough to ensure that the high-side and low-side MOSFETs do not turn on simultaneously.
[0060] When counter A (Tcnt) counts to the value CNTB of adder / subtractor B (the initial value of CNTB is equal to Tdead), GH_CTRL' changes from 0 to 1, ending the low-side MOSFET's blanking period. GL_BLANK changes from 1 to 0, and simultaneously, GH_BLANK changes from 0 to 1, entering the high-side MOSFET's blanking period. Counter B assigns its value to subtractor D (Tcnt2), then resets it and restarts counting. When the value of counter B, Tcnt2, equals Tblank, i.e., after the set blanking time Tblank, GH_BLANK changes from 1 to 0. If the feedback signal VGS_GH does not change from 0 to 1 with GH_CTRL during the high-side MOSFET's blanking period, the gate drive monitoring module considers a high-side MOSFET gate fault detected, and both GH_CTRL and GL_CTRL output 0. Counter A continues counting until the feedback signal VGS_GH changes from 0 to 1, indicating that the high-side MOSFET is truly turned on. Counter A then stops counting. If the value of counter A, Tcnt, is greater than Tdead plus 3, the value CNTB in adder / subtractor B is equal to CNTB minus 1. If the value of counter A, Tcnt, is equal to Tdead plus 3, the value CNTB in adder / subtractor B is equal to CNTB. If the value of counter A, Tcnt, is less than Tdead plus 3, the value CNTB in adder / subtractor B is equal to CNTB plus 1. This minimizes dead time and reduces power consumption.
[0061] When GL_CTRL' changes from 1 to 0, GL_CTRL remains 1. Meanwhile, the value in subtractor D is decremented by 1 every clock pulse. When the value in subtractor D reaches 0, GL_CTRL changes from 1 to 0, thus compensating for the duty cycle.
[0062] During the process of the high-side MOSFET being turned off and the low-side MOSFET being turned on, such as Figure 8 The diagram shown is a circuit timing diagram of this embodiment. Figure 3 Wherein, GH_CTRL is the control signal for the high-side MOSFET switch, GL_CTRL is the control signal for the low-side MOSFET switch; GL_CTRL' is the control signal for the low-side MOSFET switch before duty cycle compensation; Tcnt is the time segment counted by counter A, Tcnt2 is the time segment counted by counter B; Tdly is the propagation delay, the two Tdly durations are not the same, but both are propagation delays; VGS_GH is the feedback signal sent to the gate drive monitoring module corresponding to the high-side MOSFET, VGS_GL is the feedback signal sent to the gate drive monitoring module corresponding to the low-side MOSFET; GH_BLANK is the blanking signal for the high-side MOSFET, GL_BLANK is the blanking signal for the low-side MOSFET; Tblank is the set blanking time.
[0063] When GH_CTRL changes from 1 to 0, GH_BLANK changes from 0 to 1, entering the high-side MOSFET blanking period, and counter B starts counting. Due to propagation delay and MOSFET charging / discharging delays, the actual turn-off time of the high-side MOSFET will be delayed compared to GH_CTRL. If the value of counter B, TcntB, equals Tblank, meaning that after the set blanking time, the feedback signal VGS_GH does not change from 1 to 0 following GH_CTRL, it indicates that the MOSFET may have a fault or the gate voltage may be too high or too low. In this case, the gate drive monitoring module will consider that a high-side MOSFET gate fault has been detected, and both GH_CTRL and GL_CTRL will output 0. When the feedback signal VGS_GH changes from 1 to 0 within the set blanking time, it indicates that the high-side MOSFET is truly turned off. The dead time at which counter A is reset and starts counting at this point will be the actual dead time used on the MOSFET. In other words, the dead time can be set small enough to ensure that the high-side and low-side MOSFETs do not turn on simultaneously.
[0064] After counter A counts to adder / subtractor C (the initial value of CNTC equals Tdead), GL_CTRL' changes from 0 to 1, ending the high-side MOSFET's blanking period. GH_BLANK changes from 1 to 0, and simultaneously, GL_BLANK changes from 0 to 1, entering the low-side MOSFET's blanking period. Counter B assigns its value to subtractor D (Tcnt2), then clears it and restarts counting. When the value of counter B, TcntB, equals Tblank, i.e., after the set blanking time Tblank, GL_BLANK changes from 1 to 0. If the feedback signal VGS_GL does not change from 0 to 1 with GL_CTRL during the low-side MOSFET's blanking period, the gate drive monitoring module considers a low-side MOSFET gate fault detected, and both GH_CTRL and GL_CTRL output 0. Counter A will continue counting until the feedback signal VGS_GL changes from 0 to 1, indicating that the low-side MOSFET is truly turned on. Counter A will then stop counting. If the value of counter A, Tcnt, is greater than the value of Tdead plus 3, the value CNTC in adder / subtractor C is equal to the value of CNTC minus 1. If the value of counter A, Tcnt, is equal to the value of Tdead plus 3, the value CNTC in adder / subtractor C is equal to CNTC. If the value of counter A, Tcnt, is less than the value of Tdead plus 3, the value CNTC in adder / subtractor C is equal to the value of CNTC plus 1.
[0065] When GL_CTRL' changes from 1 to 0, GL_CTRL remains 1. Meanwhile, the value in subtractor D is decremented by 1 every clock pulse. When the value in subtractor D reaches 0, GL_CTRL changes from 1 to 0, thus compensating for the duty cycle.
[0066] Example 2.
[0067] This application also provides a gate drive monitoring device, including the gate drive monitoring circuit in the above embodiments. Figure 5 This is a circuit diagram of the gate drive monitoring module of this utility model.
[0068] The first counter unit includes counter A U1 and a counter A counting and reset condition judgment unit U14. The output of the counter A counting and reset condition judgment unit U14 is connected to the input of counter A U1. The second counter unit includes counter B U2 and a counter B counting and reset condition judgment unit U15. The output of the counter B counting and reset condition judgment unit U15 is connected to the input of counter B.
[0069] The current adjustment register unit includes a high-side current adjustment register U8 and a low-side current adjustment register U9. The output of the high-side current adjustment register U8 is connected to the input of the first current adjustment unit, and the output of the low-side current adjustment register U9 is connected to the input of the second current adjustment unit.
[0070] The dead time control unit includes a dead time register U5, an adder / subtractor BU3, an adder / subtractor CU4, and a dead time signal comparison and judgment unit U10. The output of the dead time register U5 is connected to the input of the adder / subtractor CU4. The outputs of the adder / subtractor BU3 and the adder / subtractor CU4 are respectively connected to the second and third inputs of the dead time signal comparison and judgment unit U10. The output of the dead time register U5 is connected to the fourth input of the dead time signal comparison and judgment unit U10. The first input of the dead time signal comparison and judgment unit U10 is connected to the output of the counter A U1.
[0071] The duty cycle compensation unit includes register D (counting condition judgment U16) and subtractor D (U7). The output of register D (counting condition judgment U16) is connected to the second input of subtractor D (U7), and the first input of subtractor D (U7) is connected to the output of counter B (U2).
[0072] The blanking time control unit includes a blanking time register U6 and a blanking signal comparison and judgment U11. The output of the blanking time register U6 is connected to the second input of the blanking signal comparison and judgment U11, and the first input of the blanking signal comparison and judgment U11 is connected to the output of the counter B U2.
[0073] The fault control unit includes a fault judgment unit U13, the input of which is connected to the output of the blanking signal comparison judgment U11.
[0074] The drive control signal unit includes a drive control logic processing unit U12. The first input of the drive control logic processing unit U12 is connected to the output of the dead-time signal comparison and judgment unit U10. The third input of the drive control logic processing unit U12 is connected to the output of the fault judgment unit U13. The second input of the drive control logic processing unit U12 is connected to the output of the subtractor D U7. The first output of the drive control logic processing unit U12 is connected to the input of the high-side pre-drive circuit unit, and the second output is connected to the input of the low-side pre-drive circuit unit.
[0075] The specific working process of the gate drive monitoring device is as follows.
[0076] Dead time and blanking time are fixed times that are set, such as Figure 6 The diagram shown is a circuit timing diagram of this embodiment. Figure 1Where Tdead is the set dead time and Tblank is the set blanking time. GH_CTRL is the control signal for the high-side MOSFET switch, and GL_CTRL is the control signal for the low-side MOSFET switch. When GH_CTRL is 1, it indicates that the high-side MOSFET switch is on; when GH_CTRL is 0, it indicates that the high-side MOSFET switch is off. Similarly, when GL_CTRL is 1, it indicates that the low-side MOSFET switch is on; when GL_CTRL is 0, it indicates that the low-side MOSFET switch is off. GH_BLANK is the high-side MOSFET blanking signal, and GL_BLANK is the low-side MOSFET blanking signal.
[0077] During the process of the low-side MOSFET being turned off and the high-side MOSFET being turned on, such as Figure 7 The diagram shown is a circuit timing diagram of this embodiment. Figure 2 Wherein, GH_CTRL is the control signal for the high-side MOSFET switch, and GL_CTRL is the control signal for the low-side MOSFET switch; GH_CTRL' is the control signal for the high-side MOSFET switch before duty cycle compensation; Tcnt is the time segment counted by counter A, and Tcnt2 is the time segment counted by counter B; Tdly is the propagation delay, and the two Tdly durations are not the same, but both are propagation delays; VGS_GH is the feedback signal sent to the gate drive monitoring module corresponding to the high-side MOSFET, and VGS_GL is the feedback signal sent to the gate drive monitoring module corresponding to the low-side MOSFET; GH_BLANK is the blanking signal for the high-side MOSFET, and GL_BLANK is the blanking signal for the low-side MOSFET; Tblank is the set blanking time.
[0078] When GL_CTRL changes from 1 to 0, GL_BLANK changes from 0 to 1, entering the low-side MOSFET blanking period, and counter B starts counting. Due to propagation delay and MOSFET charging / discharging delays, the actual turn-off time of the low-side MOSFET will be delayed compared to GL_CTRL. If the value of counter B, Tcnt2, equals Tblank, meaning that after the set blanking time, the feedback signal VGS_GL does not change from 1 to 0 following GL_CTRL, it indicates that the MOSFET may have a fault or the gate voltage may be too high or too low. In this case, the gate drive monitoring module will consider that a low-side MOSFET gate fault has been detected, and the gate drive will be disabled, with both GH_CTRL and GL_CTRL outputting 0. However, when the feedback signal VGS_GL changes from 1 to 0 within the set blanking time, it indicates that the low-side MOSFET is truly turned off. The dead time at which counter A is reset and starts counting will be the actual dead time used on the MOSFET. In other words, the dead time can be set small enough to ensure that the high-side and low-side MOSFETs do not turn on simultaneously.
[0079] When counter A (Tcnt) counts to the value CNTB of adder / subtractor B (the initial value of CNTB is equal to Tdead), GH_CTRL' changes from 0 to 1, ending the low-side MOSFET's blanking period. GL_BLANK changes from 1 to 0, and simultaneously, GH_BLANK changes from 0 to 1, entering the high-side MOSFET's blanking period. Counter B assigns its value to subtractor D (Tcnt2), then resets it and restarts counting. When the value of counter B, Tcnt2, equals Tblank, i.e., after the set blanking time Tblank, GH_BLANK changes from 1 to 0. If the feedback signal VGS_GH does not change from 0 to 1 with GH_CTRL during the high-side MOSFET's blanking period, the gate drive monitoring module considers a high-side MOSFET gate fault detected, and both GH_CTRL and GL_CTRL output 0. Counter A continues counting until the feedback signal VGS_GH changes from 0 to 1, indicating that the high-side MOSFET is truly turned on. Counter A then stops counting. If the value of counter A, Tcnt, is greater than Tdead plus 3, the value CNTB in adder / subtractor B is equal to CNTB minus 1. If the value of counter A, Tcnt, is equal to Tdead plus 3, the value CNTB in adder / subtractor B is equal to CNTB. If the value of counter A, Tcnt, is less than Tdead plus 3, the value CNTB in adder / subtractor B is equal to CNTB plus 1. This minimizes dead time and reduces power consumption.
[0080] When GL_CTRL' changes from 1 to 0, GL_CTRL remains 1. Meanwhile, the value in subtractor D is decremented by 1 every clock pulse. When the value in subtractor D reaches 0, GL_CTRL changes from 1 to 0, thus compensating for the duty cycle.
[0081] During the process of the high-side MOSFET being turned off and the low-side MOSFET being turned on, such as Figure 8 The diagram shown is a circuit timing diagram of this embodiment. Figure 3 Wherein, GH_CTRL is the control signal for the high-side MOSFET switch, GL_CTRL is the control signal for the low-side MOSFET switch; GL_CTRL' is the control signal for the low-side MOSFET switch before duty cycle compensation; Tcnt is the time segment counted by counter A, Tcnt2 is the time segment counted by counter B; Tdly is the propagation delay, the two Tdly durations are not the same, but both are propagation delays; VGS_GH is the feedback signal sent to the gate drive monitoring module corresponding to the high-side MOSFET, VGS_GL is the feedback signal sent to the gate drive monitoring module corresponding to the low-side MOSFET; GH_BLANK is the blanking signal for the high-side MOSFET, GL_BLANK is the blanking signal for the low-side MOSFET; Tblank is the set blanking time.
[0082] When GH_CTRL changes from 1 to 0, GH_BLANK changes from 0 to 1, entering the high-side MOSFET blanking period, and counter B starts counting. Due to propagation delay and MOSFET charging / discharging delays, the actual turn-off time of the high-side MOSFET will be delayed compared to GH_CTRL. If the value of counter B, TcntB, equals Tblank, meaning that after the set blanking time, the feedback signal VGS_GH does not change from 1 to 0 following GH_CTRL, it indicates that the MOSFET may have a fault or the gate voltage may be too high or too low. In this case, the gate drive monitoring module will consider that a high-side MOSFET gate fault has been detected, and both GH_CTRL and GL_CTRL will output 0. When the feedback signal VGS_GH changes from 1 to 0 within the set blanking time, it indicates that the high-side MOSFET is truly turned off. The dead time at which counter A is reset and starts counting at this point will be the actual dead time used on the MOSFET. In other words, the dead time can be set small enough to ensure that the high-side and low-side MOSFETs do not turn on simultaneously.
[0083] After counter A counts to adder / subtractor C (the initial value of CNTC equals Tdead), GL_CTRL' changes from 0 to 1, ending the high-side MOSFET's blanking period. GH_BLANK changes from 1 to 0, and simultaneously, GL_BLANK changes from 0 to 1, entering the low-side MOSFET's blanking period. Counter B assigns its value to subtractor D (Tcnt2), then clears it and restarts counting. When the value of counter B, TcntB, equals Tblank, i.e., after the set blanking time Tblank, GL_BLANK changes from 1 to 0. If the feedback signal VGS_GL does not change from 0 to 1 with GL_CTRL during the low-side MOSFET's blanking period, the gate drive monitoring module considers a low-side MOSFET gate fault detected, and both GH_CTRL and GL_CTRL output 0. Counter A will continue counting until the feedback signal VGS_GL changes from 0 to 1, indicating that the low-side MOSFET is truly turned on. Counter A will then stop counting. If the value of counter A, Tcnt, is greater than the value of Tdead plus 3, the value CNTC in adder / subtractor C is equal to the value of CNTC minus 1. If the value of counter A, Tcnt, is equal to the value of Tdead plus 3, the value CNTC in adder / subtractor C is equal to CNTC. If the value of counter A, Tcnt, is less than the value of Tdead plus 3, the value CNTC in adder / subtractor C is equal to the value of CNTC plus 1.
[0084] When GL_CTRL' changes from 1 to 0, GL_CTRL remains 1. Meanwhile, the value in subtractor D is decremented by 1 every clock pulse. When the value in subtractor D reaches 0, GL_CTRL changes from 1 to 0, thus compensating for the duty cycle.
[0085] The main functions of the gate drive monitoring circuit and device of this invention are implemented by digital circuits, enabling more complex and diverse functions while effectively reducing chip area and cost. The adaptive dead time is achieved by removing the MOSFET turn-on and turn-off propagation delay during dead time calculation, preventing cross-conduction or breakdown of the high-side and low-side MOSFETs in the half-bridge while minimizing dead time, thus reducing power consumption. It also allows for independent automatic adjustment of dead time by the high-side and low-side MOSFETs. The duty cycle compensation unit acquires the control signals and compensation dead time of the high-side and low-side MOSFET switches before duty cycle compensation, achieving duty cycle compensation and improving duty cycle accuracy. Adaptive blanking time is considered and implemented together with the adaptive dead time, simplifying the implementation and improving fault detection accuracy while reducing area and cost. A gate fault judgment function is included, enabling timely detection of valid faults when gate faults occur and taking corresponding measures to prevent device damage.
[0086] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the present utility model. Any simple modifications, alterations, or equivalent structural transformations made to the above embodiments based on the technical essence of the present utility model shall still fall within the protection scope of the present utility model.
Claims
1. A gate drive monitoring circuit, characterized by, The system includes a gate drive feedback module and a gate drive monitoring module connected to a gate drive module. The gate drive feedback module is connected to the gate drive monitoring module. The gate drive monitoring module includes a dead time control unit and a duty cycle compensation unit. The dead time control unit is connected between the gate drive module and the gate drive feedback module, and the duty cycle compensation unit is connected to the gate drive module.
2. The gate drive monitoring circuit of claim 1, wherein, The gate drive module includes a high-side pre-drive circuit unit connected to the gate of the high-side MOSFET and a low-side pre-drive circuit unit connected to the gate of the low-side MOSFET; the source of the high-side MOSFET is connected to the drain of the low-side MOSFET, the drain is connected to a power supply, and the source of the low-side MOSFET is grounded; the input terminals of the low-side pre-drive circuit unit and the high-side pre-drive circuit unit serve as the input terminals of the gate drive module.
3. A gate drive monitoring circuit according to claim 2, characterised in that, The gate drive module further includes a first diode D1 and a second diode D2; the anode of the first diode D1 is connected to the source of the high-side MOSFET, and the cathode is connected to the drain of the high-side MOSFET; the anode of the second diode D2 is connected to the source of the low-side MOSFET, and the cathode is connected to the drain of the low-side MOSFET.
4. A gate drive monitoring circuit according to claim 2 or 3, characterised in that, The gate drive feedback module includes a first comparator C1, a first current adjustment unit, and a first resistor R1; the gate drive monitoring module further includes a current adjustment register unit connected to the input terminal of the first current adjustment unit; the non-inverting input terminal of the first comparator C1 is connected to the gate of the high-side MOSFET, and the inverting input terminal is connected to the output terminal of the first current adjustment unit and the second terminal of the first resistor R1, respectively; the first terminal of the first resistor R1 is connected to the source of the high-side MOSFET and the drain of the low-side MOSFET, respectively.
5. A gate drive monitoring circuit according to claim 4, characterised in that, The gate drive feedback module further includes a second comparator C2, a second current adjustment unit, and a second resistor R2; the current adjustment register unit is also connected to the input terminal of the second current adjustment unit; the non-inverting input terminal of the second comparator C2 is connected to the gate of the low-side MOSFET, and the inverting input terminal is connected to the output terminal of the second current adjustment unit and the second terminal of the second resistor R2, and the first terminal of the second resistor R2 is connected to the source of the low-side MOSFET and ground respectively; the output terminals of the first comparator C1 and the second comparator C2 together serve as the output terminal of the gate drive feedback module.
6. The gate drive monitoring circuit of claim 1, wherein, The gate drive monitoring module further includes a first counter unit connected to the output terminal of the gate drive feedback module, and a drive control signal unit connected to the input terminal of the gate drive module; the output terminal of the dead time control unit is connected to the first input terminal of the drive control signal unit, and the input terminal is connected to the output terminal of the first counter unit.
7. A gate drive monitoring circuit according to claim 6, wherein The gate drive monitoring module further includes a fault control unit connected to the output terminal of the gate drive feedback module and the second input terminal of the drive control signal unit; the fault control unit is also connected to a blanking time control unit; the blanking time control unit is also connected to a second counter unit.
8. A gate drive monitoring circuit according to claim 7, characterised in that, The duty cycle compensation unit is connected to the output terminal of the blanking time control unit and the second counter unit, as well as the third input terminal of the drive control signal unit. The duty cycle compensation unit is also connected to the output terminal of the drive control signal unit through the blanking time control unit.
9. A gate drive monitoring apparatus characterized by comprising: The circuit includes a gate drive monitoring circuit according to any one of claims 1 to 8, wherein the dead time control unit includes an adder / subtractor BU3 and an adder / subtractor CU4, a dead time register U5, and a dead time signal comparison and judgment U10; and the duty cycle compensation unit includes a subtractor D U7 and a register D counting condition judgment unit U16.
10. A gate drive monitoring device according to claim 9, characterized in that, The first counter unit includes counter A U1 and counter A counting and reset condition judgment unit U14; the second counter unit includes counter B U2 and counter B counting and reset condition judgment unit U15; the blanking time control unit includes blanking time register U6 and blanking signal comparison and judgment U11; the current adjustment register unit includes high-side current adjustment register U8 and low-side current adjustment register U9; the drive control signal unit includes drive control logic processing unit U12; The fault control unit includes a fault judgment unit U13.