Planar gate MOSFET integrating PN junction and Schottky junction and its fabrication method

Abstract

A planar gate MOSFET integrating a PN junction and a Schottky junction, and its fabrication method. This relates to the field of semiconductor technology. The method includes the following steps: Step S100, fabricating a plurality of spaced P-body regions within an epitaxial wafer, fabricating an N+ region within the P-body regions, and fabricating a plurality of spaced P-channel regions within the N+ regions; Step S200, fabricating a gate dielectric on the epitaxial wafer, and fabricating a plurality of spaced polysilicon on the gate dielectric above the P-channel regions; Step S300, depositing an isolation layer on the epitaxial wafer, and creating a source trench that penetrates the N+ regions and extends into the P-body regions; Step S400, fabricating an N-region at the bottom of the source trench, connecting the N-region to the N-type breakdown voltage region of the epitaxial wafer; Step S500, fabricating a Schottky contact metal on the top surface of the N-region, forming a Schottky contact with the N-region, wherein the upper surface of the Schottky contact metal is lower than the lower surface of the N+ region; The planar gate MOSFET with enhanced body diode freewheeling capability and its fabrication method prepared by this invention have superior performance and process advantages.

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