An OCP interface compatible with large sizes and dual small sizes and an implementation method thereof

Abstract

The present invention provides a large-size compatible dual-channel small-size OCP interface and an implementation method, belonging to the technical field of server OCP interface design. The OCP interface includes a server motherboard, a first RISER card and a second RISER card, an OCP LFF slot, a CPLD, a first CPU and a second CPU, a first OCP interface and a second OCP interface. The CPLD is also connected to the first CPU and the second CPU; the OCP LFF slot is connected to the CPLD, the first OCP interface and the second OCP interface; the OCP LFF slot is plugged into the first RISER card or the second RISER card; the second RISER card is provided with OCP LFF connector gold fingers, a first 4C+ connector and a second 4C+ connector. The present invention realizes the compatibility of the OCP LFF interface with the expansion of 2-way SFF 4C+ interfaces, and improves the resource utilization rate of the server OCP interface.

Description

Technical Field

[0001] The present invention belongs to the technical field of server OCP interface design, and particularly relates to an OCP interface that is compatible with large size and dual small sizes and an implementation method thereof. Background Art

[0002] SFF is the abbreviation of Small Form Factor, which means small size.

[0003] LFF is the abbreviation of Large Form Factor, which means large size.

[0004] OCP is the abbreviation of OPEN Compute Project, which means a general computer platform.

[0005] CPLD is the abbreviation of Complex Programmable Logic Device, which means a complex programmable logic device.

[0006] As a mezzanine card, the OCP card has been widely used in the server field. OCP3.0 usually supports two network card size standard interfaces, namely SFF and LFF. The interface of the SFF network card is a 4C+ interface, while the interface of the LFF network card is a combination of a 4C interface and a 4C+ interface. The LFF network card interface supports one LFF network card or supports one 4C+ network card with reduced resources. There is a situation where the resources of the LFF interface for supporting the 4C+ network card are not maximally utilized. How to make full use of the LFF interface to implement the application of the 4C+ network card is an important technical issue.

[0007] Currently, the mainstream server OCP3.0 interface is designed as a standard OCP interface. The SFF interface is used to insert a 4C+ interface network card, and the LFF interface is used to insert an LFF network card. The application of the network card is relatively fixed.

[0008] With the full application of servers, the requirements for server functions and performance are getting higher and higher, and there are more and more resources on the server motherboard. Currently, there are demands for using LFF OCP network cards and two-way SFF 4C+ OCP network cards. The LFF interface has only one 4C+ interface. Therefore, there is a situation where the resources of the LFF interface for supporting the SFF 4C+ network card are not maximally utilized. Expanding the OCP network card poses challenges to the utilization of server space and the layout of signal wiring. Under the condition of meeting customer requirements, it poses challenges to the implementation of the extended optimization design of the OCP LFF interface.

[0009] This is the deficiency of the prior art. Therefore, it is very necessary to provide an OCP interface that is compatible with large size and dual small sizes and an implementation method thereof to address the above-mentioned defects in the prior art. Summary of the Invention

[0010] In view of the defect that the existing LFF interface for SFF 4C+ network cards in the prior art fails to maximize the utilization of resources, the present invention provides a large-size compatible dual-channel small-size OCP interface and an implementation method to solve the above technical problems.

[0011] In a first aspect, the present invention provides a large-size compatible dual-channel small-size OCP interface, including a server motherboard, a first RISER card, and a second RISER card;

[0012] The server motherboard is provided with an OCP LFF slot, a CPLD, a first CPU, and a second CPU;

[0013] The CPLD is connected with a first OCP interface and a second OCP interface, and the CPLD is also connected with the first CPU and the second CPU;

[0014] The OCP LFF slot is connected with the CPLD, the first OCP interface, and the second OCP interface;

[0015] The OCP LFF slot is plugged into the first RISER card or the second RISER card;

[0016] The second RISER card is provided with an OCP LFF connector gold finger, a first 4C+ connector, and a second 4C+ connector;

[0017] The OCP LFF connector gold finger is connected with the first 4C+ connector and the second 4C+ connector;

[0018] The CPLD allocates PCIe resource bandwidth for the first OCP interface and the second OCP interface according to the type of the RISER card inserted into the OCP LFF slot and the presence information of the first OCP interface and the second OCP interface. Both the first CPU and the second CPU adopt siryn model ampere CPU processors.

[0019] Further, the first CPU is provided with a first PCIE port, and the second CPU is provided with a second PCIE port;

[0020] The first PCIE port, the second PCIE port, the first OCP interface, and the second OCP interface all adopt X16 PCIE interfaces;

[0021] The lower 8 bits of the first PCIE port are connected with the lower 8 bits of the first OCP interface, and the lower 8 bits of the second PCIE port are connected with the lower 8 bits of the second OCP interface;

[0022] The upper 8 bits of the first PCIE port are connected with a first PCIE MCIO interface, and the upper 8 bits of the first OCP interface are connected with a second PCIE MCIO interface;

[0023] The high 8 bits of the second PCIE IE port are connected to a third PCIE MCIO interface, and the high 8 bits of the second OCP interface are connected to a fourth PCIE MC IO interface;

[0024] The first PCIE MC IO interface is connected to the second PCIE MC IO interface or the fourth PCIE MC IO interface;

[0025] The third PCIE MC IO interface is connected to the fourth PCIE MC IO interface or the second PCIE MC IO interface. A PCIE MC IO interface is plugged into at most one PCIE MCIO interface.

[0026] Furthermore, the first CPU and the second CPU are connected by two groups of 16-bit CCIX buses.

[0027] Furthermore, the first CPU is also provided with a first OCP bandwidth information receiving port, and the second CPU is also provided with a second OCP bandwidth information receiving port;

[0028] The CPLD is provided with a first OCP bandwidth information sending port, a second OCP bandwidth information sending port, a first OCP interface address port, a second OCP interface address port, a board ID port, a first OCP presence information port, and a second OCP presence information port;

[0029] The first OCP bandwidth information receiving port is connected to the first OCP bandwidth information sending port, and the second OCP bandwidth information receiving port is connected to the second OCP bandwidth information sending port;

[0030] The first OCP interface address port is connected to the second PCIE MCIO interface through the first OCP interface, and the second OCP interface address port is connected to the fourth PCIE MCIO interface through the second OCP interface.

[0031] Furthermore, the second RISER card is plugged into the OCP LFF slot through the OCP LFF connector gold fingers;

[0032] The first 4C+ connector is provided with a first OCP interface presence information pin group, and the second 4C+ connector is provided with a second OCP interface presence information pin group;

[0033] The first OCP interface presence information pin group is connected to the first OCP presence information port of the CPLD through the OCP LFF connector gold fingers and the OCP LFF slot;

[0034] The second OCP port presence information pin group is connected to the second OCP presence information port of the CPLD through the OCP LFF connector gold fingers and the OCP LFF slot.

[0035] Further, the first OCP bandwidth information receiving port of the first CPU, the second OCP bandwidth information receiving port of the second CPU, the first OCP bandwidth information sending port of the CPLD, and the second OCP interface address information port use a six-bit data interface;

[0036] The first OCP presence information port and the second OCP presence information port of the CPLD, the first OCP interface presence information pin group on the first 4C+ connector, and the second OCP interface presence information pin group on the second 4C+ connector all use a four-bit data interface;

[0037] The board ID port, the first OCP interface address port, and the second OCP interface address port of the CPLD use a one-bit data interface.

[0038] Further, a pull-up resistor is provided on the first RI SER card;

[0039] One end of the pull-up resistor is connected to the power supply, and the other end of the pull-up resistor is connected to the board ID port of the CPLD through the OCP LFF slot.

[0040] Further, the first RI SER card uses an LFF OCP network card.

[0041] In a second aspect, the present invention provides a method for implementing a large-size compatible dual-channel small-size OCP interface based on the above first aspect, including the following steps:

[0042] The CPLD allocates bandwidth for the PCIe resources of the first OCP interface and the second OCP interface according to the type of the RISER card inserted into the OCP LFF slot and the presence information of the first OCP interface and the second OCP interface.

[0043] Further, the CPLD determines the type of the RISER card inserted into the OCP LFF slot according to the level of the data bit of the board ID port;

[0044] When the data bit of the board ID port is at a high level, the CPLD determines that the RISER card inserted into the OCP LFF slot is the first RISER card;

[0045] When the data bit of the board ID port is at a low level, the CPLD determines that the RISER card inserted into the OCP LFF slot is the second RISER card.

[0046] Further, when the first RISER card is inserted into the OCP LFF slot,

[0047] The CPLD transfers the data of the first OCP in-position information port to the lower four bits of the first OCP bandwidth information sending port, and transfers the data of the second OCP in-position information port to the lower four bits of the second OCP bandwidth information sending port;

[0048] The CPLD transfers the data of the first OCP interface address port to the fifth bit of the first OCP bandwidth information sending port, and transfers the data of the second OCP interface address port to the fifth bit of the second OCP bandwidth information sending port;

[0049] The CPLD transfers the data of the board ID port to the sixth bit of both the first OCP bandwidth information sending port and the second OCP bandwidth information sending port;

[0050] The CPLD sends the data of the first OCP bandwidth information sending port to the first OCP bandwidth information receiving port of the first CPU, and sends the data of the second OCP bandwidth information sending port to the second OCP bandwidth information receiving port of the second CPU;

[0051] The first CPU allocates PCIe resource bandwidth for the first OCP interface and the second OCP interface according to the data of the first OCP bandwidth information receiving port, and the second CPU allocates PCIe resource bandwidth for the first OCP interface and the second OCP interface according to the data of the second OCP bandwidth information receiving port.

[0052] Further, when the second RISER card is inserted into the OCP LFF slot,

[0053] The CPLD first sets the sixth-bit data of both the first OCP bandwidth information sending port and the second OCP bandwidth information sending port to high level, transfers the data of the first OCP interface address port to the fifth bit of the first OCP bandwidth information sending port, and transfers the data of the second OCP interface address port to the fifth bit of the second OCP bandwidth information sending port;

[0054] The CPLD then judges the PCIe resource bandwidth of the first OCP interface according to the data of the first OCP in-position information port and the first OCP interface address port, and then judges the output of the lower four bits of the first OCP bandwidth information sending port according to the PCIe resource bandwidth of the first OCP interface, and sends it to the first CPU,

[0055] and judges the PCIe resource bandwidth of the second OCP interface according to the data of the second OCP in-position information port and the second OCP interface address port, and then judges the output of the lower four bits of the second OCP bandwidth information sending port according to the PCIe resource bandwidth of the second OCP interface, and sends it to the second CPU.

[0056] The present invention utilizes the rich interface resources of the CPLD to identify the board ID, allocates the PCIe bandwidth by itself, and makes full use of the OCP LFF interface resources.

[0057] The beneficial effects of the present invention are as follows:

[0058] The large-size compatible dual-channel small-size OCP interface and implementation method provided by the present invention make full use of the LFF PCIe resources. It can support 1 LFF OCP network card or insert 2 SFF 4C+ OCP network cards for use, realizing the compatibility of the OCP LFF interface with the 2-way SFF 4C+ interface expansion, optimizing the functional design of the LFF interface, and improving the utilization rate of the server OCP interface resources.

[0059] In addition, the design principle of the present invention is reliable, the structure is simple, and it has a very broad application prospect.

[0060] Thus, compared with the prior art, the present invention has prominent substantial features and remarkable progress, and the beneficial effects of its implementation are also obvious. Description of the Drawings

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0062] Figure 1 It is a schematic diagram of the large-size compatible dual-channel small-size OCP interface of the present invention.

[0063] Figure 2 It is a schematic flow diagram of the implementation method of the large-size compatible dual-channel small-size OCP interface of the present invention.

[0064] Figure 3 It is a truth table for judging the PCIe resource bandwidth when the large-size compatible dual-channel small-size OCP interface of the present invention inserts the first RISER card.

[0065] Figure 4 It is a truth table for judging the PCIe resource bandwidth when the large-size compatible dual-channel small-size OCP interface of the present invention inserts the second RISER card.

[0066] In the figure, 1 - server motherboard; 2 - second RISER card; 3 - OCP LFF slot; 4 - CPLD; 5 - first CPU; 6 - second CPU; 7 - first OCP interface; 8 - second OCP interface; 9 - OCP LFF connector gold finger; 10 - first 4C+ connector; 11 - second 4C+ connector; 12 - first PCIE MCI O interface; 13 - second PCIE MC IO interface; 14 - third PCIE MC IO interface; 15 - fourth PCIE MCI O interface; OPCA_PCIe_x16 - first PCIE port; OPCB_PCIe_x16 - second PCIE port; R0CPA_BW_ID[5:0] - first OCP bandwidth information receiving port; R0CPB_BW_ID[5:0] - second OCP bandwidth information receiving port; T0CPA_BW_ID[5:0] - first OCP bandwidth information sending port; T0CPB_BW_ID[5:0] - second OCP bandwidth information sending port; OCPA_CPU_ADDR - first OCP interface address port; OCPB_CPU_ADDR - second OCP interface address port; BOARD_ID - board ID port; ROCPA_PRESENTn[3:0] - first OCP presence information port; ROCPB_PRESENTn[3:0] - second OCP presence information port; TOCPA_PRESENTn[3:0] - first OCP interface presence information pin group; TOCPB_PRESENTn[3:0] - second OCP interface presence information pin group. Detailed implementation mode

[0067] In order to enable those skilled in the art of this technology to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0068] CCIX, short for Cache Coherent Interconnect for Accelerators, is also read as "see 6" and is a cache coherent interconnect standard.

[0069] Embodiment 1:

[0070] As Figure 1As shown in the figure, the present invention provides a large-size compatible dual-channel small-size OCP interface, including a server motherboard 1, a first RI SER card, and a second RISER card 2;

[0071] An OCP LFF slot 3, a CPLD 4, a first CPU 5, and a second CPU 6 are provided on the server motherboard 1;

[0072] The CPLD 4 is connected to a first OCP interface 7 and a second OCP interface 8, and the CPLD 4 is also connected to the first CPU 5 and the second CPU 6;

[0073] The OCP LFF slot 3 is connected to the CPLD 4, the first OCP interface 7, and the second OCP interface 8;

[0074] The OCP LFF slot 3 is plugged into the first RI SER card or the second RISER card 2;

[0075] An OCP LFF connector gold finger 9, a first 4C+ connector 10, and a second 4C+ connector 11 are provided on the second RI SER card 2;

[0076] The OCP LFF connector gold finger 9 is connected to the first 4C+ connector 10 and the second 4C+ connector 11;

[0077] The CPLD 4 allocates PCIe resource bandwidth for the first OCP interface 7 and the second OCP interface 8 according to the type of the RI SER card inserted into the OCP LFF slot 3 and the presence information of the first OCP interface 7 and the second OCP interface 8.

[0078] The large-size compatible dual-channel small-size OCP interface provided by the present invention makes full use of the LFF PCIe resources, can support either 1 LFF OCP network card or 2 SFF 4C+ OCP network cards, realizes the OCP LFF interface compatible with the 2-way SFF 4C+ interface expansion, optimizes the LFF interface function design, and improves the utilization rate of the server OCP interface resources.

[0079] Embodiment 2:

[0080] As Figure 2 shown in the figure, the present invention provides a large-size compatible dual-channel small-size OCP interface, including a server motherboard 1, a first RI SER card, and a second RISER card 2;

[0081] The server motherboard 1 is provided with an OCP LFF slot 3, a CPLD 4, a first CPU 5 and a second CPU 6; both the first CPU 5 and the second CPU 6 adopt ampere CPU processors of the siryn model; the first CPU 5 and the second CPU 6 are connected through two groups of 16-bit CC IX buses;

[0082] The CPLD 4 is connected with a first OCP interface 7 and a second OCP interface 8, and the CPLD 4 is also connected with the first CPU 5 and the second CPU 6;

[0083] The OCP LFF slot 3 is connected with the CPLD 4, the first OCP interface 7 and the second OCP interface 8;

[0084] The OCP LFF slot 3 is plugged with a first RISER card or a second RISER card 2;

[0085] The second RISER card 2 is provided with an OCP LFF connector gold finger 9, a first 4C+ connector 10 and a second 4C+ connector 11;

[0086] The OCP LFF connector gold finger 9 is connected with the first 4C+ connector 10 and the second 4C+ connector 11;

[0087] The CPLD 4 allocates PCIe resource bandwidth for the first OCP interface 7 and the second OCP interface 8 according to the type of the RISER card inserted into the OCP LFF slot 3 and the presence information of the first OCP interface 7 and the second OCP interface 8;

[0088] The first CPU 5 is provided with a first PCIE port OPCA_PCIe_x16, and the second CPU 6 is provided with a second PCIE port OPCB_PCIe_x16;

[0089] The first PCIE port OPCA_PCIe_x16, the second PCIE port OPCB_PCIe_x16, the first OCP interface 7 and the second OCP interface 8 all adopt X16 PCIE interfaces;

[0090] The lower 8 bits of the first PCIE port OPCA_PCIe_x16 are connected with the lower 8 bits of the first OCP interface 7, and the lower 8 bits of the second PCIE port OPCB_PCIe_x16 are connected with the lower 8 bits of the second OCP interface 8;

[0091] The upper 8 bits of the first PCIE port OPCA_PCIe_x16 are connected with a first PCIE MC IO interface 12, and the upper 8 bits of the first OCP interface 7 are connected with a second PCIE MC IO interface 13;

[0092] The high 8 bits of the second PCIE port OPCB_PC I e_x 16 are connected to the third PCIE MC IO interface 14, and the high 8 bits of the second OCP interface 8 are connected to the fourth PCIE MC IO interface 15;

[0093] The first PCIE MC IO interface 12 is connected to the second PCIE MC IO interface 13 or the fourth PCIE MCI O interface 15;

[0094] The third PCIE MC IO interface 14 is connected to the fourth PCIE MCI O interface 15 or the second PCIE MC IO interface 12;

[0095] One PCIE MC IO interface is plugged into at most one PCIE MC IO interface. That is, when the first PCIE MC IO interface 12 is connected to the second PCIE MC IO interface 13, the third PCIE MC IO interface 14 is connected to the fourth PCIE MCI O interface 15. Or, when the first PCIE MC IO interface 12 is connected to the fourth PCIE MCI O interface 15, the third PCIE MC IO interface 14 is connected to the second PCIE MC IO interface 12;

[0096] The first CPU 5 is also provided with a first OCP bandwidth information receiving port R0CPA_BW_ID[5:0], and the second CPU 6 is also provided with a second OCP bandwidth information receiving port R0CPB_BW_ID[5:0];

[0097] The CPLD 4 is provided with a first OCP bandwidth information sending port T0CPA_BW_ID[5:0], a second OCP bandwidth information sending port T0CPB_BW_ID[5:0], a first OCP interface address port OCPA_CPU_ADDR, a second OCP interface address port OCPB_CPU_ADDR, a board ID port BOARD_ID, a first OCP presence information port ROCPA_PRESENTn[3:0], and a second OCP presence information port ROCPB_PRESENTn[3:0];

[0098] The first OCP bandwidth information receiving port R0CPA_BW_ID[5:0] is connected to the first OCP bandwidth information sending port T0CPB_BW_ID[5:0], and the second OCP bandwidth information receiving port R0CPB_BW_ID[5:0] is connected to the second OCP bandwidth information sending port T0CPB_BW_ID[5:0];

[0099] The first OCP interface address port OCPA_CPU_ADDR is connected to the second PCIE MCIO interface 12 through the first OCP interface 7, and the second OCP interface address port OCPB_CPU_ADDR is connected to the fourth PCIE MCI O interface 15 through the second OCP interface 8;

[0100] The second RISER card 2 is plugged into the OCP LFF slot 3 through the OCP LFF connector gold finger 9;

[0101] The first 4C+ connector 10 is provided with a first OCP interface in-position information pin group TOCPA_PRESENTn[3:0], and the second 4C+ connector 11 is provided with a second OCP interface in-position information pin group TOCPB_PRESENTn[3:0];

[0102] The first OCP interface in-position information pin group TOCPA_PRESENTn[3:0] is connected to the first OCP in-position information port ROCPA_PRESENTn[3:0] of the CPLD 4 through the OCP LFF connector gold finger 9 and the OCP LFF slot 3;

[0103] The second OCP port in-position information pin group TOCPB_PRESENTn[3:0] is connected to the second OCP in-position information port ROCPB_PRESENTn[3:0] of the CPLD 4 through the OCP LFF connector gold finger 9 and the OCP LFF slot 3;

[0104] The first OCP bandwidth information receiving port R0CPA_BW_ID[5:0] of the first CPU 5, the second OCP bandwidth information receiving port R0CPB_BW_ID[5:0] of the second CPU, the first OCP bandwidth information sending port T0CPB_BW_ID[5:0] of the CPLD 4, and the second OCP interface address information port T0CPB_BW_ID[5:0] adopt a six-bit data interface;

[0105] The first OCP in-position information port ROCPA_PRESENTn[3:0] and the second OCP in-position information port ROCPB_PRESENTn[3:0] of the CPLD 4, the first OCP interface in-position information pin group TOCPA_PRESENTn[3:0] on the first 4C+ connector 10, and the second OCP interface in-position information pin group TOCPB_PRESENTn[3:0] on the second 4C+ connector 11 all adopt a four-bit data interface;

[0106] The board ID port BOARD_ID, the first OCP interface address port OCPA_CPU_ADDR, and the second OCP interface address port OCPB_CPU_ADDR of the CPLD 4 adopt a one-bit data interface;

[0107] A pull-up resistor is provided on the first RI SER card;

[0108] The first end of the pull-up resistor is connected to the power supply, and the second end of the pull-up resistor is connected to the board ID port BOARD_ID of the CPLD 4 through the OCP LFF slot 3;

[0109] The first RISER card adopts an LFF OCP network card.

[0110] In Embodiment 2 of the present invention, the first 4C+ connector 10 is a standard OCP SFF 4C+ external connector for the 0CP LFF to 2*SFF 4C+ RISER card, which is inserted into the server 4C+ first OCP card to realize the expansion of the first OCP interface 7 of the OCP3.0 card;

[0111] The first 4C+ connector 11 is a standard OCP SFF 4C+ external connector for the 0CP LFF to 2*SFF 4C+ RI SER card, which is inserted into the server 4C+ second OCP card to realize the expansion of the second OCP interface 8 of the OCP3.0 card;

[0112] The OCP LFF connector gold finger 9 is a standard OCP LFF gold finger for the 0CP LFF to 2*SFF 4C+ RISER card, which is inserted into the server motherboard 1 OCP LFF slot 3 to realize the input of PCI e signals of the 0CP LFF to 2*SFF 4C+ RI SER card and the transmission of the OCP card in-position information and the RISER card board ID port number BOARD_ID to the server motherboard 1;

[0113] The CPLD 4 receives the BOARD_ID signal, OCPA_CPU_ADDR, OCPB_CPU_ADDR, ROCPAPRESENTn[3:0] and ROCPBPRESENTn[3:0] signals, and controls the output states of the T0CPA_BW_ID[5:0] and T0CPB_BW_ID[5:0] signals;

[0114] Such as Figure 3As shown in the table, when the BOARD ID signal is 0, CPLD 4 directly passes the ROCPAPRESENTn[3:0] signal to T0CPA_BW_ID[3:0], directly passes the ROCPBPRESENTn[3:0] signal to T0CPB_BW_ID[3:0], passes the respective CPU_ADDR signals to the respective BW_ID[4], and passes the BOARD_ID to each BW_ID[5];

[0115] As Figure 4 shown in the table, when the BOARD_ID signal is 1, CPLD 4 detects that the BOARD_ID is at a high level, sets the TOCPA_BW_ID[5] and TOCPB_BW_ID[5] signals to high-level outputs, and in addition, the ROCPA_PRESENTn[3:0] and OCPA_CPU_ADDR signals are judged for the PCIE resource bandwidth of the first OCP interface according to the Figure 4 truth table shown in; similarly, the ROCPB_PRESENTn[3:0] and OCPB_CPU_ADDR signals are judged for the PCIE resource bandwidth of the second OCP interface according to the Figure 4 truth table shown in;

[0116] The first CPU externally expands the first PCIE port OCPA_PCIe_x16 signal through RC6. Among them, the lower 8-bit signals are directly connected to the lower 8-bit of the first OPC interface 7, and the higher 8-bit signals are connected to the first PCIe MCIO interface 12. CPU1 externally expands the first PCIE port OCPB_PCIe_x16 signal through RC5. Among them, the lower 8-bit signals are directly connected to the lower 8-bit of the second OPC interface 8, and the higher 8-bit signals are connected to the third PCIe MCIO interface 14;

[0117] The second PCIe MCIO interface 13 uses an MCIO connector to connect to the higher 8-bit signal interface of the first OCPA interface 7. It can be plugged into the first PCIe MCIO interface 12 through a cable to implement a single-host x16 design for the first OCP interface 7; or it can be plugged into the third PCIe MCIO interface 14 through a cable to implement a multi-host x8+x8 design for the first OPC interface 7;

[0118] The first PCIe MCIO interface 12 uses an MCIO connector to lead out the higher 8-bit PCIe signals of the first CPU's RC6. It can be plugged into the second PCIe MCIO interface 13 or the fourth PCIe MCIO interface 15 through a cable;

[0119] The fourth PCIE MCI O interface 15 uses an MC IO connector to connect to the high 8-bit signal interface of the second OCP interface 8. It can be plugged into the third PCIE MC IO interface 14 through a cable to implement the host x16 design of the second OCP interface 8; or it can be plugged into the first PCIE MC IO interface 12 through a cable to implement the multi x8+x8 design of the second OPC interface 8.

[0120] The PCIe MCI O interface D10 uses an MC IO connector, and the outgoing signal is the high 8-bit PCIe signal of the CPU 1RC5. It can be plugged into the PCIe MC IO interface A7 or the PCIe MCIO interface C9 through a cable.

[0121] The present invention designs and uses two types of RISER cards. The first RISER card is an OCP LFF to LFF RISER card, and the second RISER card is an OCP LFF to 2*SFF 4C+RISER card. When the first RISER card is inserted, the server motherboard can expand the OCP network card interface with an LFF interface. When the second RISER card is inserted, two OCP network cards with SFF4C+ interfaces can be expanded.

[0122] The large-size compatible dual-channel small-size OCP interface provided by the present invention makes full use of the LFF PCIe resources. It can support either 1 LFF OCP network card or 2 SFF 4C+ OCP network cards, realizing the compatibility of the OCP LFF interface with the expansion of 2 SFF 4C+ interfaces, optimizing the functional design of the LFF interface, and improving the utilization rate of the server OCP interface resources.

[0123] Embodiment 3:

[0124] The present invention provides a method for implementing a large-size compatible dual-channel small-size OCP interface based on the above Embodiment 1 or Embodiment 2, including the following steps:

[0125] The CPLD allocates bandwidth for the PCIe resources of the first OCP interface and the second OCP interface according to the type of the RISER card inserted into the OCP LFF slot and the presence information of the first OCP interface and the second OCP interface.

[0126] The method for implementing a large-size compatible dual-channel small-size OCP interface provided by the present invention makes full use of the LFF PCIe resources. It can support either 1 LFF OCP network card or 2 SFF 4C+ OCP network cards, realizing the compatibility of the OCP LFF interface with the expansion of 2 SFF 4C+ interfaces, optimizing the functional design of the LFF interface, and improving the utilization rate of the server OCP interface resources.

[0127] Embodiment 4:

[0128] As shown Figure 2 in the figure, the present invention provides a method for implementing an OCP interface that is compatible with large sizes and dual small sizes, including the following steps:

[0129] S1. The CPLD determines the type of the RI SER card inserted into the OCP LFF slot according to the level of the data bit of the board ID port;

[0130] When the data bit of the board ID port is at a high level, the CPLD determines that the RI SER card inserted into the OCP LFF slot is the first RI SER card, and proceeds to step S2;

[0131] When the data bit of the board ID port is at a low level, the CPLD determines that the RI SER card inserted into the OCP LFF slot is the second RI SER card, and proceeds to step S3;

[0132] S2. When the first RISER card is inserted into the OCP LFF slot,

[0133] the CPLD transfers the data of the first OCP presence information port to the lower four bits of the first OCP bandwidth information sending port, and transfers the data of the second OCP presence information port to the lower four bits of the second OCP bandwidth information sending port;

[0134] S3. The CPLD transfers the data of the first OCP interface address port to the fifth bit of the first OCP bandwidth information sending port, and transfers the data of the second OCP interface address port to the fifth bit of the second OCP bandwidth information sending port;

[0135] S4. The CPLD transfers the data of the board ID port to the sixth bit of the first OCP bandwidth information sending port and the second OCP bandwidth information sending port;

[0136] S5. The CPLD sends the data of the first OCP bandwidth information sending port to the first OCP bandwidth information receiving port of the first CPU, and sends the data of the second OCP bandwidth information sending port to the second OCP bandwidth information receiving port of the second CPU;

[0137] S6. The first CPU allocates PCIe resource bandwidth for the first OCP interface and the second OCP interface according to the data of the first OCP bandwidth information receiving port, and the second CPU allocates PCIe resource bandwidth for the first OCP interface and the second OCP interface according to the data of the second OCP bandwidth information receiving port, and ends;

[0138] S7. When the second RISER card is inserted into the OCP LFF slot,

[0139] First, the CPLD sets the sixth bit data of both the first OCP bandwidth information sending port and the second OCP bandwidth information sending port to high level, transfers the first OCP interface address port data to the fifth bit of the first OCP bandwidth information sending port, and transfers the second OCP interface address port data to the fifth bit of the second OCP bandwidth information sending port;

[0140] S8. Then, the CPLD determines the PCIE resource bandwidth of the first OCP interface according to the first OCP in-position information port data and the first OCP interface address port, and then determines the low four-bit output of the first OCP bandwidth information sending port according to the PCIE resource bandwidth of the first OCP interface, and sends it to the first CPU;

[0141] S9. The CPLD determines the PCIE resource bandwidth of the second OCP interface according to the second OCP in-position information port data and the second OCP interface address port, and then determines the low four-bit output of the second OCP bandwidth information sending port according to the PCIE resource bandwidth of the second OCP interface, and sends it to the second CPU.

[0142] In the above Embodiment 4, in step S8, the CPLD further determines according to Figure 4 the truth table in it the PCIE resource bandwidth of the first OCP interface according to the first OCP in-position information port data and the first OCP interface address port, and then determines according to Figure 4 the truth table in it the low four-bit output of the first OCP bandwidth information sending port according to the PCIE resource bandwidth of the first OCP interface, and sends it to the first CPU;

[0143] The second PCIE MC IO interface 13 uses an MCIO connector to connect to the high 8-bit signal interface of the first OCPA interface 7. It can be plugged into the first PCIE MC IO interface 12 through a cable to achieve a single host x16 design of the first OCP interface 7; or it can be plugged into the third PCIE MCIO interface 14 through a cable to achieve a multi-host x8+x8 design of the first OPC interface 7;

[0144] The fourth PCIE MC IO interface 15 uses an MCIO connector to connect to the high 8-bit signal interface of the second OCP interface 8. It can be plugged into the third PCIE MCIO interface 14 through a cable to achieve a single host x16 design of the second OCP interface 8; or it can be plugged into the first PCIE MC IO interface 12 through a cable to achieve a multi-x8+x8 design of the second OPC interface 8.

[0145] The present invention is designed to use two RISER cards. The first RISER card is an OCP LFF to LFF RISER card, and the second RISER card is an OCP LFF to 2*SFF 4C+ RISER card. When the first RISER card is inserted, the server motherboard can expand the OCP network card interface with LFF interfaces. When the second RISER card is inserted, two OCP network card interfaces with SFF4C+ interfaces can be expanded.

[0146] The method for implementing the OCP interface that is compatible with large-size and dual-channel small-size provided by the present invention makes full use of the LFF PCIe resources. It can support either one LFF OCP network card or two SFF 4C+ OCP network cards. It realizes the compatibility of the OCP LFF interface with the expansion of two SFF 4C+ interfaces, optimizes the functional design of the LFF interface, and improves the utilization rate of the OCP interface resources of the server.

[0147] Although the present invention has been described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions should all be within the scope covered by the present invention. / Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A large-size compatible dual-channel small-size OCP interface, characterized in that, it includes a server motherboard, a first RISER card and a second RISER card; the server motherboard is provided with an OCP LFF slot, a CPLD, a first CPU and a second CPU; the CPLD is connected with a first OCP interface and a second OCP interface, and the CPLD is also connected with the first CPU and the second CPU; the OCP LFF slot is connected with the CPLD, the first OCP interface and the second OCP interface; the OCP LFF slot is plugged with the first RISER card or the second RISER card; the second RISER card is provided with an OCP LFF connector gold finger, a first 4C+ connector and a second 4C+ connector; the OCP LFF connector gold finger is connected with the first 4C+ connector and the second 4C+ connector; the CPLD allocates PCIe resource bandwidth for the first OCP interface and the second OCP interface according to the type of the RISER card inserted into the OCP LFF slot and the in-position information of the first OCP interface and the second OCP interface; the first CPU is provided with a first PCIE port, and the second CPU is provided with a second PCIE port; the first PCIE port, the second PCIE port, the first OCP interface and the second OCP interface all adopt X16 PCIE interfaces; the lower 8 bits of the first PCIE port are connected with the lower 8 bits of the first OCP interface, and the lower 8 bits of the second PCIE port are connected with the lower 8 bits of the second OCP interface; the upper 8 bits of the first PCIE port are connected with a first PCIE MCIO interface, and the upper 8 bits of the first OCP interface are connected with a second PCIE MCIO interface; the upper 8 bits of the second PCIE port are connected with a third PCIE MCIO interface, and the upper 8 bits of the second OCP interface are connected with a fourth PCIE MCIO interface; the first PCIE MCIO interface is connected with the second PCIE MCIO interface or the fourth PCIE MCIO interface; the third PCIE MCIO interface is connected with the fourth PCIE MCIO interface or the second PCIE MCIO interface.

2. The large-size compatible dual-channel small-size OCP interface according to claim 1, characterized in that, the first CPU is further provided with a first OCP bandwidth information receiving port, and the second CPU is further provided with a second OCP bandwidth information receiving port; the CPLD is provided with a first OCP bandwidth information sending port, a second OCP bandwidth information sending port, a first OCP interface address port, a second OCP interface address port, a board ID port, a first OCP in-position information port and a second OCP in-position information port; the first OCP bandwidth information receiving port is connected with the first OCP bandwidth information sending port, and the second OCP bandwidth information receiving port is connected with the second OCP bandwidth information sending port; the first OCP interface address port is connected with the second PCIE MCIO interface through the first OCP interface, and the second OCP interface address port is connected with the fourth PCIE MCIO interface through the second OCP interface.

3. The large-size compatible dual-channel small-size OCP interface according to claim 2, characterized in that, the second RISER card is plugged into the OCP LFF slot through the gold fingers of the OCP LFF connector; the first 4C+ connector is provided with a first OCP interface in-position information pin group, and the second 4C+ connector is provided with a second OCP interface in-position information pin group; the first OCP interface in-position information pin group is connected to the first OCP in-position information port of the CPLD through the gold fingers of the OCP LFF connector and the OCP LFF slot; the second OCP port in-position information pin group is connected to the second OCP in-position information port of the CPLD through the gold fingers of the OCP LFF connector and the OCP LFF slot.

4. The large-size compatible dual-channel small-size OCP interface according to claim 3, characterized in that, the first OCP bandwidth information receiving port of the first CPU, the second OCP bandwidth information receiving port of the second CPU, the first OCP bandwidth information sending port of the CPLD and the second OCP interface address information port adopt a six-bit data interface; the first OCP in-position information port and the second OCP in-position information port of the CPLD, the first OCP interface in-position information pin group on the first 4C+ connector and the second OCP interface in-position information pin group on the second 4C+ connector all adopt a four-bit data interface; the board ID port of the CPLD, the first OCP interface address port and the second OCP interface address port adopt a one-bit data interface.

5. The large-size compatible dual-channel small-size OCP interface according to claim 2, characterized in that, a pull-up resistor is provided on the first RISER card; the first end of the pull-up resistor is connected to the power supply, and the second end of the pull-up resistor is connected to the board ID port of the CPLD through the OCP LFF slot.

6. A method for implementing a large-size compatible dual-channel small-size OCP interface based on any one of the above claims 1-5, characterized in that, it includes the following steps: The CPLD allocates bandwidth for the first OCP interface and the second OCP interface according to the type of the RISER card inserted into the OCP LFF slot and the in-position information of the first OCP interface and the second OCP interface.

7. The method for implementing a large-size compatible dual-channel small-size OCP interface according to claim 6, characterized in that, the CPLD judges the type of the RISER card inserted into the OCP LFF slot according to the high and low levels of the data bit of the board ID port; when the data bit of the board ID port is at a high level, the CPLD determines that the RISER card inserted into the OCP LFF slot is the first RISER card; when the data bit of the board ID port is at a low level, the CPLD determines that the RISER card inserted into the OCP LFF slot is the second RISER card.

8. The method for implementing a large-size compatible dual-channel small-size OCP interface according to claim 7, characterized in that, when the first RISER card is inserted into the OCP LFF slot, The CPLD transfers the data of the first OCP in-position information port to the lower four bits of the first OCP bandwidth information sending port, and transfers the data of the second OCP in-position information port to the lower four bits of the second OCP bandwidth information sending port; The CPLD transfers the data of the first OCP interface address port to the fifth bit of the first OCP bandwidth information sending port, and transfers the data of the second OCP interface address port to the fifth bit of the second OCP bandwidth information sending port; The CPLD transfers the data of the board ID port to the sixth bit of both the first OCP bandwidth information sending port and the second OCP bandwidth information sending port; The CPLD sends the data of the first OCP bandwidth information sending port to the first OCP bandwidth information receiving port of the first CPU, and sends the data of the second OCP bandwidth information sending port to the second OCP bandwidth information receiving port of the second CPU; The first CPU performs PCIe resource bandwidth allocation for the first OCP interface based on the data of the first OCP bandwidth information receiving port, and the second CPU performs PCIe resource bandwidth allocation for the second OCP interface based on the data of the second OCP bandwidth information receiving port.

9. The method for implementing a large-size compatible dual-way small-size OCP interface according to claim 7, characterized in that, when the second RISER card is inserted into the OCP LFF slot, the CPLD first sets the sixth-bit data of both the first OCP bandwidth information sending port and the second OCP bandwidth information sending port to high level, transfers the data of the first OCP interface address port to the fifth bit of the first OCP bandwidth information sending port, and transfers the data of the second OCP interface address port to the fifth bit of the second OCP bandwidth information sending port; the CPLD then judges the PCIe resource bandwidth of the first OCP interface according to the data of the first OCP in-position information port and the first OCP interface address port, and then judges the output of the lower four bits of the first OCP bandwidth information sending port according to the PCIe resource bandwidth of the first OCP interface, and sends it to the first CPU, and judges the PCIe resource bandwidth of the second OCP interface according to the data of the second OCP in-position information port and the second OCP interface address port, and then judges the output of the lower four bits of the second OCP bandwidth information sending port according to the PCIe resource bandwidth of the second OCP interface, and sends it to the second CPU.

Images