A universal satellite on-board functions and payload functions interface simulation system

Abstract

This invention discloses a general-purpose satellite service and payload function interface simulation system, implemented based on FPGA. The system includes multiple functional units, a configuration control unit, and a data uplink unit. The functional units simulate the satellite service and payload function interfaces according to the configuration control unit's settings, generating data with corresponding fields to be sent to the on-board device under test. They also receive data from the on-board device under test, parse it, and send it to the data uplink unit. The configuration control unit reads the configuration information table stored in external Flash memory upon power-up and performs corresponding processing and configuration on each unit. It receives the configuration information table input from the host computer and stores it in external Flash memory. It also determines the configuration mode according to the host computer's control commands and performs real-time configuration on the corresponding functional units. The data uplink unit receives data from each functional unit, performs combining, scheduling, and packaging, and then sends it uplink to the host computer.

Description

Technical Field

[0001] This invention relates to the field of integrated aviation and aerospace electronics technology, and in particular to a general-purpose satellite service and payload function interface simulation system. Background Technology

[0002] During the development of onboard products, equipment simulating satellite mission or payload functional interfaces is required for functional performance testing. This equipment is typically purchased or custom-designed boards, all of which require FPGA design to simulate the satellite mission or payload functional interfaces.

[0003] The functional interfaces of satellite service platforms and payloads generally include scientific data interfaces, command and control parameter interfaces, direct telemetry interfaces, direct remote control interfaces, second pulse interfaces, and GPIO interfaces. Ground interfaces are typically implemented using FPGAs to simulate these functions. However, different satellite development missions result in different interfaces and protocols between the satellite service platform and various payloads, leading to incompatibility between board and FPGA designs. Each design requires redesign, resulting in a waste of manpower, cost, and time.

[0004] Therefore, designing a payload and satellite service function simulation system applicable to different missions, and configuring different protocol functions and interfaces through a host computer, can effectively reduce development costs and ensure the timely completion of development tasks. Poor versatility is currently the main difficulty in satellite service or payload function simulation.

[0005] Satellite mission or payload function simulation systems typically consist of off-the-shelf products such as industrial PCs and PCIe interface 1553B boards, analog acquisition boards, RS422 boards, LVDS boards, and digital input boards. Each board contains a programmable FPGA, requiring the design of the host computer interface, FPGA interface, and logic for each board to be performed on the industrial PC. The disadvantages of this approach are the large number of FPGAs requiring programming, poor versatility, high cost, and bulky chassis. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the existing technology and to propose a universal satellite service and payload function interface simulation system.

[0007] To achieve the above objectives, this invention proposes a general-purpose satellite service and payload functional interface simulation system. This system is implemented using an FPGA and is characterized by comprising: multiple functional units, a configuration control unit, and a data uplink unit; wherein...

[0008] The functional unit is used to generate data of the corresponding fields of the functional interface according to the configuration control unit's configuration of the satellite's service and payload functional interface, and send the data to the on-board equipment under test via the external interface circuit; it is also used to receive data from the on-board equipment under test via the external interface circuit, parse it, and send it to the data uplink unit.

[0009] The configuration control unit is used to read the configuration information table stored in the external Flash when powered on, and to perform corresponding processing and configuration on each unit according to the configuration information table; it is also used to receive the configuration information table input by the host computer and store it in the external Flash; and it is also used to determine the configuration mode according to the control commands input by the host computer and to configure the corresponding functional units in real time.

[0010] The data uplink unit is used to receive data from each functional unit, and after combining, scheduling and packaging, send it uplink to the host computer.

[0011] As an improvement to the above system, the functional unit includes:

[0012] The scientific data function unit is used to generate scientific data in the corresponding format fields based on the configuration information written to the register group of the scientific data function unit by the configuration control unit, and send it to the on-board equipment under test via the external interface circuit using the corresponding communication protocol.

[0013] The command parameter function unit is used to receive command data packets sent by the on-board device under test based on the configuration information written to the register group of the command parameter function unit by the configuration control unit, and forward them to the data uplink unit based on the timeout reception method; it is also used to parse the command data packets based on the control sequence parsing method, and generate response data packets with corresponding format fields based on the control sequence generation method; using the corresponding communication protocol, it sends the response data packets to the on-board device under test through the external interface circuit, and forwards the generated response data packets to the data uplink unit;

[0014] The analog quantity acquisition function unit is used to acquire analog quantities from the on-board equipment under test according to the configuration information written to the register group of the analog quantity acquisition function unit by the configuration control unit, and send them to the data uplink unit.

[0015] The analog quantity generation function unit is used to generate corresponding analog quantities according to the configuration information written by the configuration control unit to the register group of the analog quantity generation function unit, and send them to the on-board device under test through the external interface circuit.

[0016] The switch quantity acquisition function unit is used to acquire the switch quantities of the on-board equipment under test according to the configuration information written by the configuration control unit into the register group of the switch quantity acquisition function unit, and send them to the data uplink unit.

[0017] The switch quantity generation function unit is used to generate corresponding switch quantities based on the configuration information written by the configuration control unit to the register group of the switch quantity generation function unit, and send them to the on-board device under test via the external interface circuit.

[0018] The pulse detection function unit is used to detect pulses of the on-board equipment under test according to the configuration information written by the configuration control unit to the register group of the pulse detection function unit, and send the pulses to the data uplink unit.

[0019] The GPIO function unit is used to generate corresponding GPO levels according to the configuration information written to the register group of the GPIO function unit by the configuration control unit, and send them to the on-board device under test via the external interface circuit; it is also used to realize GPI detection of the on-board device under test according to the configuration information written to the unit register group by the configuration control unit, and send it to the data uplink unit.

[0020] The second pulse generation function unit is used to generate corresponding second pulses according to the configuration information written by the configuration control unit to the register group of the second pulse generation function unit, and send them to the on-board equipment under test through the external interface circuit.

[0021] The heartbeat signal generation unit is used to generate a corresponding heartbeat signal based on the configuration information written to the register group of the heartbeat signal generation unit by the configuration control unit, and send it to the on-board device under test via an external interface circuit; and

[0022] The 8b10b / PCM receiving function unit is used to receive 8b / 10b encoded single-wire LVDS data and uncoded three-wire LVDS data from the on-board device under test according to the configuration information written to the register group of the 8b10b / PCM receiving function unit by the configuration control unit, and send them to the data uplink unit.

[0023] As an improvement to the above system, the control sequence generation method includes:

[0024] Read the packet assembly control sequence written to the register group by the host computer, generate or read the corresponding bytes from the register group according to the packet assembly control sequence, assemble the bytes into a data packet and send it to the on-board device under test;

[0025] The control sequence parsing method includes:

[0026] Read the unpacking control sequence written to the register group by the host computer, generate or read the corresponding byte from the register group according to the unpacking control sequence, and compare it with the received byte. If all bytes match, the received data packet is considered correct; otherwise, the received data packet is considered incorrect.

[0027] As an improvement to the above system, the timeout reception method is as follows: if no data is received after a specified time, it is considered that the received command data packets of the on-board device under test have been received.

[0028] As an improvement to the above system, the configuration control unit includes:

[0029] The external memory management module is used to receive the configuration information table sent by the host computer, erase the corresponding sector of the Flash memory according to the fields in the table, and write the configuration information table into the Flash memory; it is also used to read the configuration information table from the external Flash memory after the FPGA is powered on, parse the table into configuration commands, and send them to the configuration control module; and

[0030] The configuration control module is used to receive control commands sent by the host computer to determine the configuration mode, and to receive configuration commands sent by the host computer to write configuration information to the register group of the corresponding functional unit.

[0031] As an improvement to the aforementioned system, the configuration information table includes a header, configuration commands, and a CRC checksum; wherein,

[0032] The table header includes a table synchronization header, total configuration command length, number of sectors to be written, number of sectors to be erased, sector number to be written to Flash, and sector number to be erased from Flash. The sector number to be written to Flash is the storage area of ​​the configuration information table, which stores the current configuration information table of the external memory management module. The sector number to be erased from Flash is the intersection of the sector number of the last time the configuration information table was written, recorded by the host computer, and the sector number to be written now.

[0033] The configuration commands include commands related to the scientific data function unit, the command and parameter function unit, and other function units; for the scientific data function unit, the configuration commands include message format, transmission interval, number of transmissions, and communication protocol selection and configuration; for the command and parameter function unit, the configuration commands include command / response message format, response interval, and communication protocol selection and configuration.

[0034] As an improvement to the above system, the configuration mode includes:

[0035] External serial port configuration mode is used to respond to configuration and control commands sent by the host computer.

[0036] External memory configuration mode, responding to configuration information tables and control commands; in this mode, after recognizing the table synchronization header, the external memory management module erases the corresponding sector according to the erase sector number in the configuration information table; in this mode, the external memory module manages the configuration information table storage area based on a linked list; and

[0037] Pause configuration mode, which only responds to control commands.

[0038] As an improvement to the aforementioned system, the linked list-based configuration information table storage area includes the management of the first sector of the storage area and the management of the entire storage area; wherein...

[0039] The management of the first sector of the storage area specifically includes: sequentially reading each byte from the first sector of the external Flash; when the highest bit of the read byte is 1, recording the address of the current byte to store the starting sector number of the configuration information table storage area; when the highest bit of all bytes is 0, erasing the first sector of the Flash and using address 0 to store the starting sector number of the configuration information table storage area; the address storing the starting sector number of the configuration information table storage area is the storage area boot block; after receiving the first write sector number, writing it into the storage area boot block to guide the external memory management module to power on and read back the configuration information table;

[0040] The management of the entire storage area specifically includes: when a write sector number is received, the currently received sector number is written to the tail address of the sector pointed to by the previous write sector number, and all sectors pointed to by the write sector numbers are linked in a one-way manner as the configuration information table storage area.

[0041] As an improvement to the above system, the functional units are configured and deployed by pre-generated software, specifically including:

[0042] The number of each functional unit is determined based on the functional requirements of the satellite service and payload functional interfaces;

[0043] Receive the requirements of each functional unit, the FPGA model to be deployed, and the location of the project directory;

[0044] Input the above information into the pre-generation software to automatically generate the corresponding TCL script and project top-level file;

[0045] Run the TCL script to create the project;

[0046] While meeting the requirements, the FIFO and RAM depth of the FPGA are reduced to generate a bit file, and the design is then embedded into the FPGA, thereby completing the configuration and deployment of the functional units.

[0047] 10. The general satellite space service and payload function interface simulation system according to claim 1, characterized in that a configuration bus is used between the configuration control unit and each functional unit, a data uplink bus is used between the data uplink unit and each functional unit, and serial communication is used between the configuration control unit and the host computer.

[0048] Compared with the prior art, the advantages of the present invention are:

[0049] 1. This invention supports design-level reconfiguration, and can be adapted to various FPGA models by adding or removing functional units;

[0050] 2. This invention supports register-level reconfiguration, enabling its use in the development of various satellite platforms through dynamic and static configuration reconfiguration.

[0051] 3. The method based on sequence parsing / data packet generation and timeout reception proposed in this invention enables the design to generate and receive data packets conforming to various task data formats under external configuration, thereby enhancing the versatility of the design. Attached Figure Description

[0052] Figure 1 This is a block diagram of the general satellite service and payload function interface simulation system of the present invention;

[0053] Figure 2 This is the pre-generated software workflow designed in this invention;

[0054] Figure 3 This invention configures the host computer's workflow;

[0055] Figure 4 This is a block diagram of the scientific data functional unit design of this invention;

[0056] Figure 5 This is a block diagram of the command / parameter function unit design of this invention;

[0057] Figure 6 This is a design block diagram of the method for generating data packets based on control sequences according to the present invention;

[0058] Figure 7 This is a design block diagram of the data packet parsing method based on control sequence of the present invention. Detailed Implementation

[0059] The system of this invention is used to test the functional interfaces of payload managers on different satellite platforms. The system includes: a configuration control unit, a data uplink unit, various functional units, a configuration control bus, and a data uplink bus; wherein,

[0060] The configuration control unit is used to receive a configuration information table input from an external serial port and store the table in an external Flash memory; it is used to read the configuration information table previously stored in the Flash memory and perform corresponding processing and configuration on each unit according to the configuration information table after each power-on; it is used to receive configuration / control commands input from an external serial port and configure the corresponding unit according to the commands.

[0061] The data uplink unit is used to package, schedule, and uplink data from each functional unit.

[0062] The functional unit is used to simulate the payload and the functional interface between the space service and the manager;

[0063] The configuration bus is used to connect each functional unit with the configuration control unit;

[0064] The data uplink bus is used to connect the functional unit that needs to transmit data back to the data uplink unit.

[0065] As an improvement to the above design, the design achieves configuration reconfiguration by writing configuration information tables or configuration / control commands into a host computer.

[0066] The configuration information table includes a header, a series of configuration commands, and a CRC checksum. The header includes a table synchronization header, the total length of the configuration command section, the number of write / erase sector numbers, and the write / erase Flash sector numbers.

[0067] The sector number written to Flash points to the storage area of ​​the configuration information table, which stores the configuration information table received by the current external memory management module.

[0068] The erased Flash sector number is the intersection of the sector number recorded by the host computer in the previous write configuration information table and the sector number to be written now;

[0069] The configuration commands include the selection and configuration of message format, transmission interval, transmission count, and communication protocol in the scientific data unit; the selection and configuration of command / response message format, response interval, and communication protocol in the command parameter unit; and the configuration of other functional interface units.

[0070] The control command is used to switch the configuration mode of the configuration control unit. The configuration modes include external serial port, external memory, and pause configuration mode.

[0071] The external serial port configuration mode, in which the configuration control unit only responds to configuration commands and control commands, and does not respond to the configuration information table;

[0072] The external memory configuration mode is described in which the configuration control unit only responds to the configuration information table and control commands, and does not respond to configuration commands; in this mode, after recognizing the table synchronization header, the external memory management module erases the corresponding sector according to the received erase sector number; in this mode, the external memory management module adopts a method of managing the configuration information table storage area based on a linked list.

[0073] The pause configuration mode is a mode in which the configuration control unit only responds to control commands and does not respond to configuration commands and configuration information tables.

[0074] As an improvement to the above design, the method for managing the configuration information table storage area based on a linked list includes a method for managing the first sector of the storage area and a method for managing the entire storage area. Among these,

[0075] The external memory management module manages the first sector of the memory area using the following method: After the module starts working, it reads each byte sequentially from the first sector of the Flash memory. When the highest bit of the read byte is 1, the address of the current byte is recorded and used to store the starting sector number of the configuration information table storage area. When the highest bit of all bytes is 0, the first sector of the Flash memory is erased, and the starting sector number of the configuration information table storage area is stored at address 0. The address storing the starting sector number of the configuration information table storage area is the memory area boot block. After receiving the first write sector number, the external memory management module writes it into the memory area boot block to guide the external memory management module to power on and read back the configuration information table.

[0076] The external memory management module manages the entire storage area as follows: when the external memory management module receives a write sector number, it writes the currently received sector number to the tail address of the sector pointed to by the previous write sector number, and unidirectionally links all the sectors pointed to by the write sector numbers as the configuration information table storage area.

[0077] As an improvement to the above design, the configuration control unit and the non-volatile flash memory technology NOR Flash enable static configuration reconfiguration; the configuration control unit and the low-speed serial input interface enable dynamic configuration reconfiguration.

[0078] As an improvement to the above design, the configuration bus, data uplink bus, and design pre-generation software enable design refactoring. Among these,

[0079] The configuration bus is used to isolate the configuration control unit from each functional unit, so that the addition or deletion of functional units in the design can be automatically executed by the design pre-generation software, and the configuration control unit does not need to be changed.

[0080] The data uplink bus is used to isolate the data uplink unit from each functional unit, so that the addition or deletion of functional units in the design can be automatically executed by the design pre-generation software, and the data uplink unit does not need to be modified.

[0081] As an improvement to the above design, the configuration control unit implements configuration reconfiguration with both NOR Flash (non-volatile flash memory) and a low-speed serial input interface. Specifically, it includes: a configuration control module, an external memory management module, a scientific data function unit, a command and parameter function unit, a control logic unit, and an 8b10b / PCM receiving function unit; wherein...

[0082] The configuration control module is used to receive control commands sent by the host computer and control the configuration mode according to the commands. When the configuration mode is set to external serial port, it is used to receive configuration commands sent by the host computer, parse the configuration commands and write them into the register of the corresponding unit through the configuration bus. When the configuration mode is set to external memory, it is used to receive configuration commands sent by the external memory management module, parse the configuration commands and write them into the register of the corresponding unit through the configuration bus.

[0083] The external memory management module is used to receive the configuration information table sent by the host computer, erase the corresponding sector of the Flash according to the fields in the table, and write the configuration information table into the Flash; after the FPGA is powered on, it reads the configuration information table from the Flash and parses the table into configuration commands and sends them to the configuration control module.

[0084] The scientific data functional unit is used to generate scientific data in a corresponding format according to the configuration information;

[0085] The command parameter function unit is used to receive command data packets according to configuration information and generate response data packets in the corresponding format;

[0086] The control logic unit is used to implement the control logic of the external functional chip according to the configuration information and to store the results. The results include output analog quantity, switch quantity acquisition results, output switch quantity pulse, analog quantity acquisition results, pulse detection results, GPI detection results, second pulse and heartbeat signal.

[0087] The 8b10b / PCM receiving function unit is used to receive data of the corresponding communication protocol according to the configuration information.

[0088] As an improvement to the above design, the design supports reconfiguration. The number of any functional unit and the FPGA models supported by the IP cores can be changed through pre-generated design software, enabling rapid deployment to different FPGA models.

[0089] The scientific data function unit supports up to 16 units, and different data formats and output levels can be selected through registers. The data formats include UART, 8b / 10b and PCM, and the output levels include RS422 level and LVDS level.

[0090] The command parameter function unit supports up to 16 units, each of which can correspond to a different data format. The data formats include UART, full-duplex and half-duplex bus modes, with UART being the default.

[0091] The design pre-generation software reconstructs the design by editing Tcl scripts and automatically generating top-level files using Python.

[0092] The Python script automatically generates a top-level file for modifying the number of functional units in the design.

[0093] The Tcl script is used to modify the FPGA models supported by the IP core.

[0094] As an improvement to the above design, the configuration control unit and the host computer use serial communication, including configuration information table transmission operations, control command transmission operations, and configuration command transmission operations; wherein...

[0095] The configuration information table transmission operation includes: an 8-byte synchronization header, a 2-byte erase sector number field length, N bytes of erase sector numbers (one sector number is 1 byte), a 2-byte write sector number field length, N bytes of write sector numbers (one sector number is 1 byte), a 4-byte configuration command table length, N bytes of configuration commands, and a 2-byte CRC checksum, using high byte order;

[0096] The control command transmission operation includes: a 4-byte synchronization header and a 1-byte control command, using high byte order;

[0097] The configuration command transmission operation includes: a 4-byte synchronization header, a 1-byte configuration command identifier, a 2-byte address to be configured, and a 1-byte value to be configured.

[0098] As an improvement to the above design, the scientific data unit and command parameter unit are implemented based on a sequence-based data packet generation / parsing method and a timeout reception method. Among them,

[0099] The sequence-based data packet generation / parsing method first classifies and encodes the fields in the data format according to their characteristics, then converts each field in the specific data packet into a packet assembly / decompression control sequence represented by the encoding rules, and finally performs packet assembly / decompression operations according to the control sequence.

[0100] The timeout reception method is used to solve the problem that the length of the instruction data packet in the command parameters is unknown, and to determine whether the instruction data packet has been received completely based on the waiting time.

[0101] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0102] Example

[0103] like Figure 1 As shown, embodiments of the present invention propose a universal satellite service and payload function interface simulation system. This system, in conjunction with external interface circuits, can test the payload manager of the device under test and can be applied to the testing of payload manager function interfaces of various satellite platforms.

[0104] This system covers most of the functional interfaces of the platform and payload. Regarding the space platform, the system supports high-speed data interfaces, analog signal acquisition interfaces, and digital signal acquisition interfaces, in addition to the bus. The bus adopts a traditional solution, implemented using a board with a PCI-E interface that supports the bus, with the host computer controlling the bus for payload management and testing. Regarding the payload, the system supports telemetry and remote control input / output interfaces, payload scientific data interfaces, and payload command / engineering response interfaces.

[0105] The system's functions include: receiving and parsing commands and configuration tables sent by the host computer; controlling external Flash reading, writing, and erasing; configuring and reconfiguring each functional module according to the configuration table or configuration commands; combining, packaging, and sending data collected or generated by each functional unit; simulating the output of scientific data from the load, receiving and responding to commands, outputting analog signals, and detecting pulses; and simulating the platform's analog signal acquisition, switch control, second pulse generation, GPIO input / output, heartbeat signal output, and high-speed data reception.

[0106] The high versatility of this system design is achieved through configurable functional units, a configuration control unit, a configuration bus, and a data uplink bus. Based on the satellite platform's requirements for interface type, quantity, and format, configuration reconfiguration is achieved through the host computer configuring the registers of each functional unit, enabling the design to be applied to various different satellite platforms. Configuration information is organized into a configuration information table according to pre-defined address definitions and written to external Flash memory via the configuration control module. Upon power-up, no dynamic configuration reconfiguration by the host computer is required; the reconfiguration information is automatically loaded from the Flash memory, achieving static configuration reconfiguration. If the FPGA supporting this design is changed, the IP core can be changed to support a different FPGA model through the design pre-generation software. Functional units can be added or removed according to the satellite platform's requirements, adjusting the resources and area used in the design to make it compatible with various FPGA models.

[0107] This invention also designs and implements pre-generation software, the workflow of which is as follows: Figure 2 As shown: Based on specific development requirements, and considering the available resources and area of ​​the FPGA used, the required number of functional units that the FPGA can support is determined. The corresponding functional units are selected in the design pre-generation software, and the design is generated and synthesized. The synthesized design file is then fixed to the FPGA, and the FPGA is powered on again to begin FPGA configuration.

[0108] Configure the host computer workflow as follows Figure 3As shown: Based on specific development requirements, the payload command, response, and scientific data formats are determined. Based on these formats and other telemetry, remote control, and receiving data requirements, a configuration information table is formed. Commands for erasing and writing to the external Flash memory are generated according to the write status of each sector, and combined with the configuration section to form a complete configuration information table. The host computer writes the configuration information table to the FPGA via serial port. The FPGA then performs the corresponding erase and write operations on the Flash memory according to the table's contents, thus embedding the configuration information table into the Flash memory. After the FPGA powers on, it first checks the Flash's boot address and retrieves the complete configuration information table based on it. The usability of the data in the configuration information table is verified: if usable, the register groups of each functional unit are configured according to the configuration commands in the configuration information table; if unusable, it enters a waiting mode for configuration commands. During FPGA operation, the host computer can send configuration switching commands via serial port to switch the configuration model to dynamic configuration. The host computer can also directly send configuration commands via serial port to configure a specific register of a functional unit.

[0109] The configuration information stored in the payload configuration table Flash includes: table length, starting sector number for writing to Flash, sector number for erasing Flash, and a series of configuration commands. These configuration commands include settings for message format, transmission interval, number of transmissions, and communication protocol selection and configuration in the scientific data unit; command / response message format, response interval, and communication protocol selection and configuration in the command parameters unit; and configuration for other functional interface units.

[0110] The FPGA design for the ground inspection system consists of a configuration control unit, a data uplink unit, a scientific data function unit, a command / parameter function unit, an analog signal acquisition function unit, an analog signal generation function unit, a digital signal acquisition function unit, a digital signal generation function unit, a pulse detection function unit, a GPIO function unit, a second pulse generation function unit, a heartbeat signal generation function unit, and an 8b10b / PCM receiving function unit.

[0111] 1) The configuration control unit is used to parse and execute configuration commands from the host computer. It parses the address and the value to be written from the configuration command and writes the value to the target register according to the address. It is also used to parse and execute control commands from the host computer. The host computer controls the configuration mode of the configuration control unit through these commands. Specifically, the configuration mode of this unit is external Flash static configuration, external serial port dynamic configuration, and configuration disabled. Furthermore, it receives the configuration information table and writes it into the Flash memory according to the fields in the table. Upon each power-on, it first reads the Flash memory. If an available configuration information table is available, it reads the table and parses out a series of configuration information for configuring the register groups of each functional unit.

[0112] 2) The data uplink unit is used to receive, schedule, package, and transmit back the data that each functional unit needs to transmit to the host computer. This includes data acquired by analog signal acquisition, digital signal acquisition, pulse detection, and GPIO functional units, as well as data received and transmitted by scientific data, command / engineering parameters, and 8b10b / PCM receiving functional units. The acquired data is transmitted to the host computer via RS422, and the data received and transmitted by the functional units is transmitted to the host computer via 10 Gigabit Ethernet.

[0113] 3) The scientific data unit, which is implemented by a data packet generation module based on control sequences, such as... Figure 4 As shown. The data packet generation module generates scientific data in the corresponding format according to the configuration information of the host computer, and then sends it to the external circuit according to the transmission mode selected by the configuration information. The transmission modes include UART, 8b / 10b encoding and three-wire (PCM).

[0114] 4) The instruction / engineering functional unit, which is implemented by a data packet generation / parsing module based on control sequences and a timeout reception method, such as... Figure 5 As shown. When this unit receives a command data packet, according to the timeout reception method, it waits for a given period of time. If no new data is received, it considers the command reception complete and then sends the command to the data packet parsing module for parsing. The data packet parsing module parses the command type of the received command and determines the correctness of each field within the command. It then sends the command type and correctness information as the parsing result to the data packet generation module. The data packet generation module generates the corresponding response data packet based on the parsing result and sends it to the UART module to be sent back to the payload manager.

[0115] 5) The analog quantity acquisition function unit, analog quantity generation function unit, digital quantity acquisition function unit, digital quantity generation function unit, pulse detection function unit, GPIO function unit, second pulse generation function unit and heartbeat signal generation function unit are used to implement the control logic of the external function chip according to the configuration information and store the results.

[0116] 6) The 8b10b / PCM receiving function unit is used to receive external 8b / 10b encoded single-wire LVDS data and uncoded three-wire LVDS data according to the configuration information, and upload the received data to the data uplink unit.

[0117] The data packet generation module in the scientific data unit is implemented by a method for generating data packets based on control sequences; the instruction / engineering function unit is implemented by a data packet generation / parsing module based on control sequences and a timeout reception method.

[0118] 1) The method for generating data packets based on control sequences classifies and encodes fields in the data format according to their characteristics. Fixed fields in scientific data and command parameters data packets, such as packet synchronization codes, version numbers, packet identifiers, and payload identifiers, are defined as fixed bytes; fields that need to be calculated according to verification rules, such as CRC and checksums, are defined as check bytes; fields that need to be filled with random numbers or ordered auto-incrementing numbers, such as valid data and scientific data, are defined as padding bytes; timecode fields that need to be filled with real-time information are defined as timecode bytes; fields that serve a counting function, such as packet sequence counts, group identifiers, and packet counts, are defined as count bytes; in command parameters, since there is no need to focus on timecodes, packet counts, etc., they are all classified as irrelevant bytes. Then, according to the above rules, each field in the specific data packet is converted into a packet control sequence represented by encoding. The host computer writes the sequence and corresponding data into the scientific data module, and the scientific data module fills in the corresponding data at the corresponding byte position in the data packet according to the read encoding. The specific FPGA implementation is as follows: Figure 6 As shown, the process is divided into three stages: reading, generating, and sending. Reading involves reading the packet assembly control sequence sent by the host computer; generating involves filling data packets according to the encoding of the packet assembly control sequence; and sending involves generating the corresponding timing output according to the protocol required by the task.

[0119] 2) The method for parsing data packets based on control sequences is a derived method of generating data packets based on control sequences. It replaces the sending part of the data packet generation module with byte comparison. This method first pre-generates a byte based on the encoded sequence. When a byte is received, it compares the currently received byte with the pre-generated byte, and then generates the next byte based on the encoded sequence, repeating this process. If the two bytes are different, an error message is generated and sent to the acknowledgment control module to control the generation of acknowledgment data packets. The specific FPGA implementation is as follows... Figure 7 As shown, the process is divided into three stages: reading, generating, and comparing. Reading involves reading the packet control sequence sent by the host computer; generating involves generating fields based on the encoding of the packet control sequence; and comparing involves comparing the received command data packet with the generated fields.

[0120] 3) The timeout reception method converts the length-based instruction data packet reception into a time-based instruction data packet reception. When the data receiving interface fails to receive data within the specified time, the instruction data packet reception is considered complete.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A universal satellite on-board functions and payload functions interface simulation system, the system is implemented based on FPGA, characterized in that, The system includes: multiple functional units, a configuration control unit, and a data uplink unit; wherein... The functional unit is used to generate data of the corresponding fields of the functional interface according to the configuration control unit's configuration of the satellite's service and payload functional interface, and send the data to the on-board equipment under test via the external interface circuit; it is also used to receive data from the on-board equipment under test via the external interface circuit, parse it, and send it to the data uplink unit. The configuration control unit is used to read the configuration information table stored in the external Flash when powered on, and to perform corresponding processing and configuration on each unit according to the configuration information table; it is also used to receive the configuration information table input by the host computer and store it in the external Flash; and it is also used to determine the configuration mode according to the control commands input by the host computer and to configure the corresponding functional units in real time. The data uplink unit is used to receive data from each functional unit, and after combining, scheduling and packaging, send it uplink to the host computer. The configuration control unit includes: The external memory management module is used to receive the configuration information table sent by the host computer, erase the corresponding sector of the Flash memory according to the fields in the table, and write the configuration information table into the Flash memory; it is also used to read the configuration information table from the external Flash memory after the FPGA is powered on, parse the table into configuration commands, and send them to the configuration control module; and The configuration control module is used to receive control commands sent by the host computer to determine the configuration mode, and to receive configuration commands sent by the host computer to write configuration information to the register group of the corresponding functional unit. The configuration information table includes a header, configuration commands, and CRC checksum; wherein... The table header includes a table synchronization header, total configuration command length, number of sectors to be written, number of sectors to be erased, sector number to be written to Flash, and sector number to be erased from Flash. The sector number to be written to Flash is the storage area of ​​the configuration information table, which stores the current configuration information table of the external memory management module. The sector number to be erased from Flash is the intersection of the sector number of the last time the configuration information table was written, recorded by the host computer, and the sector number to be written now. The configuration commands include commands related to the scientific data function unit, the command parameter function unit, and other function units; wherein, for the scientific data function unit, the configuration commands include message format, transmission interval, number of transmissions, communication protocol selection and configuration; for the command parameter function unit, the configuration commands include command / response message format, response interval, communication protocol selection and configuration; The configuration modes include: External serial port configuration mode is used to respond to configuration and control commands sent by the host computer. External memory configuration mode, responding to configuration information tables and control commands; in this mode, after recognizing the table synchronization header, the external memory management module erases the corresponding sector according to the erase sector number in the configuration information table; in this mode, the external memory module manages the configuration information table storage area based on a linked list; and Pause configuration mode, which only responds to control commands.

2. The universal satellite space service and payload function interface simulation system according to claim 1, characterized in that, The functional unit includes: The scientific data function unit is used to generate scientific data in the corresponding format fields based on the configuration information written to the register group of the scientific data function unit by the configuration control unit, and send it to the on-board equipment under test via the external interface circuit using the corresponding communication protocol. The command parameter function unit is used to receive command data packets sent by the on-board device under test based on the configuration information written to the register group of the command parameter function unit by the configuration control unit, and forward them to the data uplink unit based on the timeout reception method; it is also used to parse the command data packets based on the control sequence parsing method, and generate response data packets with corresponding format fields based on the control sequence generation method; using the corresponding communication protocol, it sends the response data packets to the on-board device under test through the external interface circuit, and forwards the generated response data packets to the data uplink unit; The analog quantity acquisition function unit is used to acquire analog quantities from the on-board equipment under test according to the configuration information written to the register group of the analog quantity acquisition function unit by the configuration control unit, and send them to the data uplink unit. The analog quantity generation function unit is used to generate corresponding analog quantities according to the configuration information written by the configuration control unit to the register group of the analog quantity generation function unit, and send them to the on-board device under test through the external interface circuit. The switch quantity acquisition function unit is used to acquire the switch quantities of the on-board equipment under test according to the configuration information written by the configuration control unit into the register group of the switch quantity acquisition function unit, and send them to the data uplink unit. The switch quantity generation function unit is used to generate corresponding switch quantities based on the configuration information written by the configuration control unit to the register group of the switch quantity generation function unit, and send them to the on-board device under test via the external interface circuit. The pulse detection function unit is used to detect pulses of the on-board equipment under test according to the configuration information written by the configuration control unit to the register group of the pulse detection function unit, and send the pulses to the data uplink unit. The GPIO function unit is used to generate corresponding GPO levels according to the configuration information written to the register group of the GPIO function unit by the configuration control unit, and send them to the on-board device under test via the external interface circuit; it is also used to realize GPI detection of the on-board device under test according to the configuration information written to the unit register group by the configuration control unit, and send it to the data uplink unit. The second pulse generation function unit is used to generate corresponding second pulses according to the configuration information written by the configuration control unit to the register group of the second pulse generation function unit, and send them to the on-board equipment under test through the external interface circuit. The heartbeat signal generation unit is used to generate a corresponding heartbeat signal based on the configuration information written to the register group of the heartbeat signal generation unit by the configuration control unit, and send it to the on-board device under test via an external interface circuit; and The 8b10b / PCM receiving function unit is used to receive 8b / 10b encoded single-wire LVDS data and uncoded three-wire LVDS data from the on-board device under test according to the configuration information written to the register group of the 8b10b / PCM receiving function unit by the configuration control unit, and send them to the data uplink unit.

3. The universal satellite service and payload function interface simulation system according to claim 2, characterized in that, The control sequence generation method includes: Read the packet assembly control sequence written to the register group by the host computer, generate or read the corresponding bytes from the register group according to the packet assembly control sequence, assemble the bytes into a data packet and send it to the on-board device under test; The control sequence parsing method includes: Read the unpacking control sequence written to the register group by the host computer, generate or read the corresponding byte from the register group according to the unpacking control sequence, and compare it with the received byte. If all bytes match, the received data packet is considered correct; otherwise, the received data packet is considered incorrect.

4. The universal satellite service and payload function interface simulation system according to claim 2, characterized in that, The timeout reception method is as follows: if no data is received after a specified time, it is considered that the received command data packets of the on-board device under test have been received.

5. The universal satellite service and payload function interface simulation system according to claim 1, characterized in that, The linked list-based configuration information table storage area includes the management of the first sector of the storage area and the management of the entire storage area; wherein... The management of the first sector of the storage area specifically includes: sequentially reading each byte from the first sector of the external Flash; when the highest bit of the read byte is 1, recording the address of the current byte to store the starting sector number of the configuration information table storage area; when the highest bit of all bytes is 0, erasing the first sector of the Flash and using address 0 to store the starting sector number of the configuration information table storage area; the address storing the starting sector number of the configuration information table storage area is the storage area boot block; after receiving the first write sector number, writing it into the storage area boot block to guide the external memory management module to power on and read back the configuration information table; The management of the entire storage area specifically includes: when a write sector number is received, the currently received sector number is written to the tail address of the sector pointed to by the previous write sector number, and all sectors pointed to by the write sector numbers are linked in a one-way manner as the configuration information table storage area.

6. The universal satellite service and payload function interface simulation system according to claim 2, characterized in that, The functional units are configured and deployed by pre-generated software, specifically including: The number of each functional unit is determined based on the functional requirements of the satellite service and payload functional interfaces; Receive the requirements of each functional unit, the FPGA model to be deployed, and the location of the project directory; Input the above information into the pre-generation software to automatically generate the corresponding TCL script and project top-level file; Run the TCL script to create the project; While meeting the requirements, the FIFO and RAM depth of the FPGA are reduced to generate a bit file, and the design is then embedded into the FPGA, thereby completing the configuration and deployment of the functional units.

7. The universal satellite service and payload function interface simulation system according to claim 1, characterized in that, The configuration control unit and each functional unit are connected via a configuration bus, the data uplink unit and each functional unit are connected via a data uplink bus, and the configuration control unit and the host computer are connected via serial communication.

Images