A display panel and a display device

Abstract

The present application provides a display panel and a display device. The display panel includes a display area and a non-display area at least partially surrounding the display area. The display area includes a first display area and a second display area. The display panel further includes a first shift register group, a second shift register group, a first signal line group, and a second signal line group. Among them, the first shift register group receives a first control signal through the first signal line group and is used to provide a first driving signal for the first display area. The second shift register group receives a second control signal through the second signal line group and is used to provide a second driving signal for the second display area. At least one signal line in the first signal line group is located in the display area. By arranging at least one signal line in the first signal line group in the display area of the display panel, the number of signal lines in the non-display area of the display panel is reduced, and further the width of the non-display area of the display panel is narrowed, thereby achieving the narrow bezel of the partitioned refreshed display screen.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] For the zoned refresh technology of a display screen, the display screen is divided into several zones, and the screen refresh rate of each zone can be set independently. Zones with low requirements for the refresh rate in the display screen can be set at a lower refresh rate, thereby reducing the driving power consumption of the display screen while ensuring the display effect.

[0003] The zoned refresh technology needs to provide independent vertical shift register (VSR) driving start signals for each zone of the screen. To provide independent driving start signals for multiple zones, multiple signal lines need to be arranged. In the prior art, the signal lines are generally arranged at the positions of the left and right borders of the screen. Therefore, the arrangement of multiple signal lines increases the width of the left and right borders of the screen, which is not conducive to the realization of a narrow border for the display screen. Summary of the Invention

[0004] In view of this, the present application provides a display panel and a display device, which can realize the narrow border of the zoned refresh display screen.

[0005] In a first aspect, an embodiment of the present application provides a display panel. The display panel includes: a display area and a non-display area at least partially surrounding the display area. The display area includes a first display area and a second display area. The display panel further includes: a first shift register group, a second shift register group, a first signal line group, and a second signal line group. Among them, the first shift register group receives a first control signal through the first signal line group and is used to provide a first driving signal for the first display area. The second shift register group receives a second control signal through the second signal line group and is used to provide a second driving signal for the second display area. At least one signal line in the first signal line group is located in the display area.

[0006] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display device, including the display panel as described in the embodiment of the first aspect.

[0007] A display panel and a display device provided by an embodiment of the present application. The display panel includes a display area and a non-display area at least partially surrounding the display area. The display area includes a first display area and a second display area. The display panel further includes a first shift register group, a second shift register group, a first signal line group, and a second signal line group. Among them, the first shift register group receives a first control signal through the first signal line group and is used to provide a first driving signal for the first display area. The second shift register group receives a second control signal through the second signal line group and is used to provide a second driving signal for the second display area. At least one signal line in the first signal line group is located in the display area. By arranging at least one signal line in the first signal line group in the display area of the display panel, the number of signal traces in the non-display area of the display panel is reduced, and thus the width of the non-display area of the display panel is narrowed, thereby realizing the narrow bezel of the partitioned refreshed display screen. Description of the Drawings

[0008] By reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, other features, objects, and advantages of the present application will become more apparent. Among them, the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0009] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present application;

[0010] Figure 2 A schematic structural diagram of another display panel provided by an embodiment of the present application;

[0011] Figure 3 A schematic structural diagram of a pixel circuit provided by an embodiment of the present application;

[0012] Figure 4 A schematic structural diagram of a first shift register VSR1 provided by an embodiment of the present application;

[0013] Figure 5 A timing schematic diagram of the first shift register VSR1 provided by an embodiment of the present application;

[0014] Figure 6 A schematic structural diagram of yet another display panel provided by an embodiment of the present application;

[0015] Figure 7 A schematic structural diagram of yet another display panel provided by an embodiment of the present application;

[0016] Figure 8 A schematic structural diagram of yet another display panel provided by an embodiment of the present application;

[0017] Figure 9 A schematic structural diagram of yet another display panel provided by an embodiment of the present application;

[0018] Figure 10 It is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0019] Figure 11 It is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0020] Figure 12 It is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0021] Figure 13 It is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0022] Figure 14 It is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0023] Figure 15 It is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0024] Figure 16 It is a schematic structural diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0025] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0026] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0027] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0028] It should be understood that the term "and / or" used herein is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship.

[0029] In the embodiments of the present application, the term "connection" may refer to the direct electrical connection of two components, or may refer to the connection between two components via one or more other components.

[0030] Without departing from the spirit or scope of the present application, various modifications and changes can be made in the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0031] As introduced in the background art, the partition refresh technology of the display screen requires providing independent VSR drive start signals for each partition of the screen. Providing independent drive start signals for multiple partitions requires laying multiple signal lines on the display panel. Thus, the laying of multiple signal lines increases the width of the left and right borders of the screen, which is not conducive to the realization of a narrow border of the display screen.

[0032] Based on this, the embodiments of the present application provide a display panel and a display device, which can achieve the narrow border of the partition-refreshed display screen. The embodiments of the display panel and the display device will be described below with reference to the accompanying drawings.

[0033] The display panel provided by the embodiments of the present application can be an organic light-emitting diode (OLED) display panel, or a micro light-emitting diode display panel, or other types of display panels.

[0034] Figure 1 A top view schematic diagram of the display panel provided by the embodiments of the present application is shown. As Figure 1As shown, the display panel 100 provided by the embodiment of the present application may include a display area AA and a non-display area NA that at least partially surrounds the display area AA. Among them, the display area AA may include a first display area AA1 and a second display area AA2.

[0035] Corresponding to the first display area AA1 and the second display area AA2, the display panel 100 further includes a first shift register group 10, a second shift register group 20, as well as a first signal line group (not shown in the figure) and a second signal line group (not shown in the figure).

[0036] The first shift register group 10 receives a first control signal through the first signal line group and generates a first driving signal according to the first control signal. The first driving signal is used to control the working state of the pixel circuit in the first display area AA1, such as the refresh frequency. The second shift register group 20 receives a second control signal through the second signal line group and generates a second driving signal according to the second control signal. The second driving signal is used to control the working state of the pixel circuit in the second display area AA2, such as the refresh frequency.

[0037] The wiring of at least one signal line (such as S1) in the first signal group is located in the display area AA.

[0038] In the embodiment of the present application, aiming at the problem in the prior art solution that independent driving start signals are provided for multiple partitions of the screen, so that multiple signal lines need to be arranged on the left and right borders (non-display areas) of the screen, resulting in the inability to implement the narrow border scheme of the screen, the following technical solution is used for improvement: at least one signal line in the first signal line group is located in the display area AA. Thus, at least one signal line in the first signal line group is arranged in the display area of the display panel, reducing the number of signal lines in the non-display area of the display panel, and further narrowing the width of the non-display area of the display panel, thereby realizing the narrow border of the partition-refreshed display screen.

[0039] It should be noted that the circuit structures of the first shift register group 10 and the second shift register group 20 are not limited in this embodiment. The circuit structures of the two may be the same or different. The two receive control signals and output driving signals to meet different display requirements of the first display area AA1 and the second display area AA2.

[0040] The control signals received by the first shift register group 10 may include different types of control signals. For example, the control signals received by the first shift register group 10 may all include a first trigger signal and a first clock signal. Correspondingly, the first signal line group may include different types of signal lines. For example, the first signal line group may include a first trigger signal line STV1 and a first clock signal line CLK1. Further, the first clock signal CLK1 in this article may include a first sub-clock signal CK1 and a second sub-clock signal XCK1.

[0041] The following will describe in conjunction with Figure 2 the connection relationship of the signal traces involved in this application. The display panel 100 provided in the embodiment of this application may include a first display area 101 and a second display area 102. Pixel circuits Pixel are distributed in both the first display area 101 and the second display area 102. The pixel circuit Pixel can be used to drive a light-emitting element ( Figure 2 not shown in the figure) to emit light. In order to better distinguish the areas to which the pixel circuits Pixel belong, Figure 2 different filling colors are used in the figure to represent the pixel circuits Pixel in the first display area 101 and the second display area 102. The pixel circuit Pixel may include components such as transistors and capacitors, and the transistors can be turned on or off under the control of a driving signal.

[0042] Corresponding to the first display area 101 and the second display area 102, the display panel 100 may be respectively provided with a first shift register group 10 and a second shift register group 20.

[0043] Specifically, the first shift register group 10 may include multiple stages of first shift registers VSR1. The first shift register group 10 provides the first driving signal generated by it to the pixel circuit Pixel in the first display area 101, so that the transistors of the pixel circuit Pixel in the first display area 101 can be turned on or off under the control of the first driving signal.

[0044] The second shift register group 20 may include multiple stages of first shift registers VSR2. The second shift register group 20 provides the second driving signal generated by it to the pixel circuit Pixel in the second display area 102, so that the transistors of the pixel circuit Pixel in the second display area 102 can be turned on or off under the control of the second driving signal.

[0045] The display panel 100 further includes a first signal line group 40 and a second signal line group 50. The first signal line group 40 can be used to provide a first control signal for the first shift register group 10, and the second signal line group 50 can be used to provide a second control signal for the second shift register group 20.

[0046] Specifically, the first signal line group 40 may include a first trigger signal line 41 and a first clock signal line 42. The first clock signal line 42 may include a first sub-clock signal line 421 and a second sub-clock signal line 422. The first trigger signal line 41 is connected to the first stage of the first shift register VSR1, and the first trigger signal line 41 is used to provide a first trigger signal STV1 for the first stage of the first shift register VSR1. The first sub-clock signal line 421 and the second sub-clock signal line 422 are connected to each first shift register VSR1, and are used to provide a first sub-clock signal CK1 and a second sub-clock signal XCK1 for each first shift register VSR1.

[0047] The second signal line group 50 may include a second trigger signal line 51 and a second clock signal line 52. The second clock signal line 52 may include a third sub-clock signal line 521 and a fourth sub-clock signal line 522. The second trigger signal line 51 is connected to the first-stage second shift register VSR2, and the second trigger signal line 51 is used to provide a second trigger signal STV2 for the first-stage second shift register VSR2. The third sub-clock signal line 521 and the fourth sub-clock signal line 522 are connected to each second shift register VSR2, and are used to provide a third sub-clock signal CK2 and a fourth sub-clock signal XCK2 for each second shift register VSR2.

[0048] It should be noted that Figure 2 the first signal line group 40 and the second signal line group 50 in Figure 2 are both arranged in the non-display area NA for the convenience of explaining the connection relationship between the signal traces, and it does not constitute a limitation on the signal line layout of the present application. For example, the first trigger signal line 41 and the second trigger signal line 51 in

[0049] Next, in conjunction with Figure 3 the pixel circuit Pixel in the display panel of the present application will be described. The pixel circuit Pixel may include transistors M1 to M7 and a storage capacitor Cst. Among them, S1 and S2 represent scan signals, EMIT represents a light emission control signal, Vdata represents a data signal, PVDD represents a first power signal terminal, PVEE represents a second power signal terminal, Vref1 represents a reset signal, Vref2 represents an initialization signal, and D represents a light-emitting element. Figure 2 The circuit structure of the pixel circuit shown is only an example and does not limit the present application.

[0050] Next, in conjunction with Figure 4 the first shift register VSR1 in the display panel of the present application will be described. The first shift register VSR1 may include transistors M11 to M18 and capacitors C1 and C2. Figure 4 In

[0051] The first control signal received by the first driving circuit 10 may include a first trigger signal STV1 and a first clock signal. In this article, it is described by taking the first clock signal may include a first sub-clock signal CK1 and a second sub-clock signal XCK1 as an example. The working process of the first shift register VSR1 may be as Figure 5As shown, under the control of the first trigger signal STV1 and the first clock signal, the output terminal OUT1 of the first shift register VSR1 can output the first driving signal.

[0052] It can be understood that the signal output by the output terminal of the upper-stage first shift register VSR1 can be used as the first trigger signal of the lower-stage first shift register VSR1. As an optional implementation manner, at least one signal line in the first signal line group is located in the display area AA, and may include: the first trigger signal line STV1 is located in the display area AA, and the first clock signal line CLK1 is located in the non-display area NA; or, the first clock signal line CLK1 is located in the display area AA, and the first trigger signal line STV1 is located in the non-display area NA; or, both the first trigger signal line STV1 and the first clock signal line CLK1 are located in the display area.

[0053] As an example, as Figure 6 shown, both the first trigger signal line STV1 and the first clock signal line CLK1 (including the first sub-clock signal CK1 and the second sub-clock signal XCK1) in the display panel 100 are located in the display area. All the signal traces in the first signal group are evenly arranged in the display area AA, which can greatly reduce the number of traces in the non-display area of the display panel, and further narrow the width of the non-display area of the display panel, thereby realizing the narrow border of the partitioned refreshed display screen.

[0054] It should be noted that in the embodiment of the present application, the shift register group is composed of multiple levels of shift registers VSR. Each level of shift register VSR in the shift register group needs to have a corresponding clock signal input. In the accompanying drawings provided in the embodiment of the present application, several clock signal lines are shown for illustration. In actual applications, the terminal sets corresponding clock signal inputs for each level of shift register VSR in the shift register group.

[0055] It can be understood that setting the trace of any signal line in the first signal line group in the display area AA can reduce the number of traces in the non-display area of the display panel, and thus provide the hardware conditions for realizing the narrow border of the display panel.

[0056] As an optional implementation manner, at least one signal line in the first signal line group is located in the display area AA, and may include: the first trigger signal line STV1 is located in the display area AA, and the first clock signal line CLK1 is located in the non-display area NA.

[0057] Specifically, refer to Figure 7, in this embodiment, the routing of the first trigger signal line STV1 is arranged in the display area AA, and the routing of the first clock signal line CLK1 is arranged in the non-display area NA. Arranging the trigger signal line in the display area AA can reduce the number of signal lines in the non-display area of the display panel, thereby providing hardware conditions for realizing the narrow border of the display panel. Moreover, since the electrical signal frequency of the clock signal line is relatively high, arranging the clock signal line in the non-display area NA can avoid signal interference caused by high-frequency signals to the display area AA in the display panel and ensure the picture display quality of the display panel.

[0058] Corresponding to the first shift register group 10, the control signals received by the second shift register group 20 in this embodiment can include different types of control signals. For example, the control signals received by the second shift register group 20 can all include a second trigger signal STV2 and a second clock signal CLK2. Further, the first clock signal CLK2 herein can include a first sub-clock signal CK2 and a second sub-clock signal XCK2.

[0059] As an alternative implementation, any signal line in the second signal line group is located in the display area AA or the non-display area NA, including: the second trigger signal line STV2 is located in the display area AA, and the second clock signal line CLK2 is located in the non-display area; or, the second clock signal line CLK2 is located in the display area AA, and the second trigger signal line STV2 is located in the non-display area NA; or, both the second trigger signal line STV2 and the second clock signal line CLK2 are located in the display area AA.

[0060] It can be understood that the routing of the second trigger signal STV2 and the second clock signal CLK2 in the second signal line group for providing the second control signal to the second shift register group 20 can be arbitrarily arranged in the display area AA or the non-display area NA. Since at least one signal line in the first signal line group in the display panel is arranged in the display area AA, the number of signal lines in the non-display area of the display panel is reduced, thereby narrowing the width of the non-display area of the display panel, and thus realizing the narrow border of the partition-refreshed display screen.

[0061] As an alternative implementation, referring to Figure 8 , the display panel 100 further includes a driving chip IC. Along the first direction y, the second display area AA2 is located between the first display area AA1 and the driving chip IC. Along the second direction x, the first shift register group 10 includes a first shift register unit 101 on one side of the first display area AA1 and a second shift register unit 102 on the other side of the first display area AA1.

[0062] The first trigger signal line STV1 includes a first A trigger signal line STV1-A connected to the first shift register unit 101 and a first B trigger signal line STV1-B connected to the second shift register unit 102;

[0063] When the first trigger signal line STV1 is located in the display area AA, the first A trigger signal line STV1-A includes a first sub-trigger signal line STV1-A-1 extending along the first direction y and a second sub-trigger signal line STV1-A-2 extending along the second direction x; the first B trigger signal line STV1-B includes a first sub-trigger signal line STV1-B-1 extending along the first direction y and a second sub-trigger signal line STV1-B-2 extending along the second direction x; wherein, the length of the second sub-trigger signal line STV1-A-2 of the first A trigger signal line STV1-A is equal to the length of the second sub-trigger signal line STV1-B-2 of the first B trigger signal line STV1-B.

[0064] It should be noted that the driving chip IC is generally arranged in the non-display area of the lower border of the screen, and the driving chip IC is electrically connected to the signal line group through fan-out lines.

[0065] It should also be noted that in the embodiment of the present application, the second direction x is perpendicular to the first direction y.

[0066] In this embodiment of the present application, the signal line lengths of the first A trigger signal line STV1-A and the first B trigger signal line STV1-B disposed in the display area AA in the second direction x are equal, thereby ensuring that the first shift register unit 101 and the second shift register unit 102 can simultaneously receive the control signals sent by the driving chip IC and control the pixel circuits in the first display area AA1, ensuring that the bit register units on both sides can simultaneously control the display area AA, avoiding display errors caused by control time delay, and ensuring the normal display function of the display panel.

[0067] Furthermore, referring to Figure 9 , in the embodiment of the present application, the first sub-trigger signal line STV1-A-1 of the first A trigger signal line STV1-A is multiplexed as the first sub-trigger signal line STV1-B-1 of the first B trigger signal line STV1-B.

[0068] Specifically, the first A trigger signal line STV1-A and the first B trigger signal line STV1-B share the signal line in the first direction y, thereby reducing the number of signal line traces on the basis of ensuring that the bit register units on both sides can simultaneously control the display area AA.

[0069] Further, in the embodiment of the present application, the length of the first sub-trigger signal line of the first trigger signal line is greater than that of the first sub-trigger signal line of the second trigger signal line; the length of the second sub-trigger signal line of the first trigger signal line is greater than that of the second sub-trigger signal line of the second trigger signal line.

[0070] Specifically, referring to Figure 10 , the length of the first sub-trigger signal line STV1-A-1 of the first A trigger signal line STV1-A is greater than that of the first sub-trigger signal line STV2-A-1 of the second A trigger signal line STV2-A; the length of the second sub-trigger signal line STV1-A-2 of the first A trigger signal line STV1-A is greater than that of the second sub-trigger signal line STV2-A-2 of the second A trigger signal line STV2-A.

[0071] Correspondingly, the length of the first sub-trigger signal line STV1-B-1 of the first B trigger signal line STV1-B is greater than that of the first sub-trigger signal line STV2-B-1 of the second B trigger signal line STV2-B; the length of the second sub-trigger signal line STV1-B-2 of the first B trigger signal line STV1-B is greater than that of the second sub-trigger signal line STV2-B-2 of the second B trigger signal line STV2-B.

[0072] Further, referring to Figure 11 , in the embodiment of the application, the second shift register group 20 includes a third shift register unit 201 located on one side of the second display area AA2 or a fourth shift register unit 202 located on the other side of the second display area AA2; the second trigger signal line STV2 includes a second A trigger signal line STV2-A connected to the third shift register unit 201, or a second B trigger signal line STV2-B connected to the fourth shift register unit 202.

[0073] Specifically, the second shift register group 20 may include a shift register unit located on either side of the second display area and a trigger signal line connected to the shift register unit on that side. Thus, for the second display area closer to the driving chip IC, only a shift register unit and the corresponding trigger signal line are provided on one side of the display area. Since the second display area is closer to the driving chip IC and receives the control signal faster than the first display area farther from the driving chip IC, only setting the register unit on one side to control the pixel circuit of the second display area AA2 can meet the signal delay requirement, ensure the display effect, simplify the circuit structure, and save the circuit hardware investment of the display panel.

[0074] As an alternative embodiment, referring to Figure 12, the display panel 100 further includes a third display area AA3, the second display area AA2 is located between the first display area AA1 and the third display area AA3, the display panel further includes a third shift register group 30 and a third signal line group (not shown in the figure); the third shift register group 30 receives a third control signal through the third signal line group and is used to provide a third driving signal for the third display area AA3; any signal line in the third signal line group is disposed in the display area AA or the non-display area NA.

[0075] Further, any signal line in the third signal line group is located in the display area AA or the non-display area NA, including: the third trigger signal line STV3 is located in the display area AA, and the second clock signal line CLK3 is located in the non-display area; or, the second clock signal line CLK3 is located in the display area AA, and the second trigger signal line STV3 is located in the non-display area NA; or, both the second trigger signal line STV3 and the second clock signal line CLK3 are located in the display area AA.

[0076] It can be understood that the wiring of the third trigger signal STV3 and the third clock signal CLK3 in the third signal line group for providing the third control signal to the third shift register group 30 can be arbitrarily set in the display area AA or the non-display area NA. Since at least one signal line in the first signal line group in the display panel is arranged in the display area AA, the number of signal lines in the non-display area of the display panel is reduced, and thus the width of the non-display area of the display panel is narrowed, thereby realizing the narrow border of the partitioned refreshed display screen.

[0077] Further, referring to Figure 13 , in the embodiment of the present application, the first trigger signal line STV1, the second trigger signal line STV2, and the third trigger signal line STV3 are all connected to the trigger signal bus STV. The trigger signal bus STV is used to transmit the trigger mother signal to the first trigger signal line STV1, the second trigger signal line STV2, and the third trigger signal line STV3. The trigger signal bus STV is disposed at the longitudinal central axis position of the display area AA.

[0078] Specifically, the trigger signal bus STV is disposed at the longitudinal central axis position of the display area AA, so that the distances from the trigger signal bus STV to the shift register units on both sides of the display area AA are equal. That is, the first trigger signal line STV1-A and the first trigger signal line STV1-B share the same section of the first sub-trigger signal line, and the lengths of the second sub-trigger signal lines of the first trigger signal line STV1-A and the first trigger signal line STV1-B are equal. Correspondingly, the second trigger signal line STV2-A and the second trigger signal line STV2-B share the same section of the first sub-trigger signal line, and the lengths of the second sub-trigger signal lines of the second trigger signal line STV2-A and the second trigger signal line STV2-B are equal. The third trigger signal line STV3-A and the third trigger signal line STV3-B share the same section of the first sub-trigger signal line, and the lengths of the second sub-trigger signal lines of the third trigger signal line STV3-A and the third trigger signal line STV3-B are equal.

[0079] It can be understood that in this embodiment, the trigger signal bus STV is multiplexed as the first sub-trigger signal line of each trigger signal line, which can simplify the routing of signal lines in the display area, reduce the proportion of the routing layout area in the display area, simplify the circuit structure, and save the circuit hardware investment of the display panel.

[0080] Furthermore, the working states of the pixel circuits in each display area of the partitioned refresh display panel are controlled by partitions, and the control signals received by each display area should also be controllable. For this purpose, referring to Figure 14 , the display panel provided in the embodiment of the present application may further include: a first gating device G1, a second gating device G2, and a third gating device G3;

[0081] The first control signal includes a first trigger signal. The first gating device G1 is disposed between the first shift register group 10 and the first trigger signal line STV1, and the first gating device is used to generate the first trigger signal according to the trigger master signal. The second control signal includes a second trigger signal. The second gating device is disposed between the second shift register group 20 and the second trigger signal line STV2, and the second gating device is used to generate the second trigger signal according to the trigger master signal. The third control signal includes a third trigger signal. The third gating device is disposed between the third shift register group 30 and the third trigger signal line STV3, and the third gating device is used to generate the third trigger signal according to the trigger master signal.

[0082] It can be understood that in this embodiment, by reusing a trigger signal bus STV, the shift registers corresponding to each display area convert the received trigger mother signal into a corresponding trigger signal via a gating device. The gating device can selectively conduct or cut off the received trigger mother signal, thereby realizing the controllability of the trigger mother signal and the partition controllability of the working states of the pixel circuits in each display area.

[0083] Furthermore, in order to reduce the space occupation ratio of circuit elements in the display area of the display panel and ensure the normal layout and operation of the pixel circuit, therefore, referring to Figure 15 , in the embodiment of the present application, the first gating device G1 is located in the first edge area of the display panel. The first edge area is the intersection area of the first row pixel group and the first column pixel group of the display panel, or the intersection area of the first row pixel group and the Mth column pixel group of the display panel; the third gating device G3 is located in the second edge area of the display panel. The second edge area is the intersection area of the Nth row pixel group and the first column pixel group of the display panel, or the intersection area of the Nth row pixel group and the Mth column pixel group of the display panel; wherein, the number of light-emitting units in the first row pixel group is less than that in the Xth row pixel group, and the number of light-emitting units in the first column pixel group is less than that in the Yth column pixel group, X is greater than 1 and less than the total number of pixel rows N of the display panel, and Y is greater than 1 and less than the total number of pixel columns M of the display panel.

[0084] Specifically, the first gating device G1 is arranged in the first edge area of the display panel. The first edge area is the intersection area of the first row pixel group and the first column pixel group of the display panel, or the intersection area of the first row pixel group and the Mth column pixel group of the display panel, that is, the outer edge area of the chamfer area of the first display area. The third gating device G3 is arranged in the second edge area of the display panel. The second edge area is the intersection area of the Nth row pixel group and the first column pixel group of the display panel, or the intersection area of the Nth row pixel group and the Mth column pixel group of the display panel, that is, the outer edge area of the chamfer area of the third display area.

[0085] It should be noted that in order to improve the screen strength and beauty of the display screen, during the design process, arc chamfers are respectively made at the four corners of the screen body in the display area of the display panel, and the edge pixels in the area where the arc chamfers need to be made are removed along the arc, corresponding to forming a chamfer area. Since some pixels in the chamfer area are removed, therefore, the number of light-emitting units in the first row pixel group of the display panel should be less than that in the Xth row pixel group, and the number of light-emitting units in the first column pixel group is less than that in the Yth column pixel group, X is greater than 1 and less than the total number of pixel rows N of the display panel, and Y is greater than 1 and less than the total number of pixel columns M of the display panel.

[0086] It should also be noted that after the third gating device G3 is disposed in the second edge region of the display panel, the third trigger signal generated by the third gating device G3 needs to be input to the signal input end of the third shift register group 30 through signal traces. Figure 10 The signal trace from the third gating device G3 to the signal input end of the third shift register group 30 in Figure 10 is only for illustration, and the signal traces of the actual product can be set according to the actual situation.

[0087] It can be seen that in this embodiment, the first gating device G1 and the third gating device G3 are disposed in the outer edge region of the chamfer area of the display panel body, without occupying the display area of the display panel, optimizing the circuit structure of the display panel, and further making use of the spatial position of the display panel.

[0088] Based on the same inventive concept, an embodiment of the present application further provides a display device, which includes the display panel provided by the embodiment of the present application. Therefore, the display device has the technical features of the display panel and its driving method provided by the embodiment of the present application, and can achieve the beneficial effects of the display panel provided by the embodiment of the present application. The same parts can refer to the description of the display panel provided by the embodiment of the present application above, and will not be repeated here.

[0089] Exemplarily, Figure 16 is a schematic structural diagram of a display device provided by an embodiment of the present application. Figure 11 The provided display device 1000 includes the display panel 100 provided by any one of the above embodiments of the present application. Figure 11 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided by the embodiment of the present application can be other display devices with display functions such as wearable products, computers, televisions, in-vehicle display devices, etc. The present application does not make specific limitations in this regard. The display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application. Specifically, reference can be made to the specific descriptions of the display panel in the above embodiments. This embodiment will not be repeated here.

[0090] In accordance with the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, the display panel includes: a display area and a non-display area at least partially surrounding the display area, the display area includes a first display area, a second display area, and a third display area; the display panel further includes: a first shift register group, a second shift register group, a third shift register group, a first signal line group, a second signal line group, and a third signal line group; wherein, the first shift register group receives a first control signal through the first signal line group and is used to provide a first driving signal for the first display area; the second shift register group receives a second control signal through the second signal line group and is used to provide a second driving signal for the second display area; the third shift register group receives a third control signal through the third signal line group and is used to provide a third driving signal for the third display area; at least one signal line in the first signal line group is located in the display area; the first signal line group includes a first trigger signal line and a first clock signal line, the second signal line group includes a second trigger signal line and a second clock signal line, and the third signal line group includes a third trigger signal line and a third clock signal line; the first trigger signal line, the second trigger signal line, and the third trigger signal line are all connected to a trigger signal bus, the trigger signal bus is used to transmit a trigger mother signal to the first trigger signal line, the second trigger signal line, and the third trigger signal line, and the trigger signal bus is disposed at the longitudinal central axis position of the display area.

2. The display panel according to claim 1, characterized in that, at least one signal line in the first signal line group is located in the display area, including: the first trigger signal line is located in the display area and the first clock signal line is located in the non-display area; or, both the first trigger signal line and the first clock signal line are located in the display area.

3. The display panel according to claim 1, characterized in that, at least one signal line in the first signal line group is located in the display area, including: the first trigger signal line is located in the display area and the first clock signal line is located in the non-display area.

4. The display panel according to claim 2 or 3, characterized in that, any signal line in the second signal line group is located in the display area or the non-display area, including: the second trigger signal line is located in the display area and the second clock signal line is located in the non-display area; or, both the second trigger signal line and the second clock signal line are located in the display area.

5. The display panel according to any one of claims 1 to 3, characterized in that, any signal line in the third signal line group is disposed in the display area or the non-display area.

6. The display panel according to claim 5, characterized in that, Any signal line in the third signal line group is disposed in the display area or the non-display area, including: both the third trigger signal line and the third clock signal line are disposed in the display area, or the third trigger signal line is disposed in the display area and the third clock signal line is disposed in the non-display area.

7. The display panel according to claim 1, wherein, the display panel further includes: a first gating device, a second gating device, and a third gating device; the first control signal includes a first trigger signal, the first gating device is disposed between the first shift register group and the first trigger signal line, and the first gating device is configured to generate the first trigger signal according to the trigger master signal; the second control signal includes a second trigger signal, the second gating device is disposed between the second shift register group and the second trigger signal line, and the second gating device is configured to generate the second trigger signal according to the trigger master signal; the third control signal includes a third trigger signal, the third gating device is disposed between the third shift register group and the third trigger signal line, and the third gating device is configured to generate the third trigger signal according to the trigger master signal.

8. The display panel according to claim 7, wherein, it further includes: the first gating device is located in a first edge area of the display panel, and the first edge area is an intersection area of the first row pixel group and the first column pixel group of the display panel, or an intersection area of the first row pixel group and the Mth column pixel group of the display panel; the third gating device is located in a second edge area of the display panel, and the second edge area is an intersection area of the Nth row pixel group and the first column pixel group of the display panel, or an intersection area of the Nth row pixel group and the Mth column pixel group of the display panel; wherein, the number of light emitting units in the first row pixel group is less than that in the Xth row pixel group, the number of light emitting units in the first column pixel group is less than that in the Yth column pixel group, X is greater than 1 and less than the total number of pixel rows N of the display panel, and Y is greater than 1 and less than the total number of pixel columns M of the display panel.

9. A display device, wherein, it includes the display panel according to any one of claims 1 to 8.

Images