Source driving circuit, method and display driving system, display terminal

Abstract

The application provides a source driving circuit, a method, a display driving system and a display terminal. The circuit comprises a plurality of source driving units, each of which comprises a first latch, a second latch, a lookup table circuit and an operational amplifier. The first latch is used to latch received nth row display data to the first latch. The second latch is used to latch the value of the high m bits in the (n-1)th row display data latched by the first latch to the second latch before the first latch latches the nth row display data to the output end of the first latch. The lookup table circuit is used to determine a first control signal according to the value of the high m bits in the nth row display data and the value of the high m bits in the (n-1)th row display data. The operational amplifier is used to control the number of transistors of the operational amplifier according to the first control signal, and drive the nth row display data to the output end of the operational amplifier by using the transistors corresponding to the number of transistors.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display driving, in particular to a source driving circuit, a source driving method, a display driving system and a display terminal. BACKGROUND

[0002] With the popularity of electronic products, display devices are increasingly diversified. Liquid crystal display devices (LCD) have many advantages such as thinness, energy saving, etc., and are widely used in high-definition electronic devices.

[0003] In a liquid crystal display device, a source driving circuit is used to provide display data to corresponding pixel units in a display panel. The current adjustment method for the source driving circuit can be realized by controlling the input reference current at the front end of the operational amplifier, or by controlling the driving current of the operational amplifier. However, the above method is for all source driving units of the source driving circuit, which can cause low flexibility and low accuracy of current adjustment. SUMMARY

[0004] The present application provides a source driving circuit, a source driving method, a display driving system and a display terminal, which can improve the flexibility and accuracy of current adjustment.

[0005] The technical solution of the present application is as follows:

[0006] In a first aspect, the present application provides a source driving circuit, which comprises a plurality of source driving units, each source driving unit comprising: a first latch, a second latch, a lookup table circuit and an operational amplifier; the output end of the first latch is connected with the first input end of the operational amplifier, the input end of the second latch and the first input end of the lookup table circuit respectively, the second input end of the lookup table circuit is further connected with the output end of the second latch, and the output end of the lookup table circuit is connected with the second input end of the operational amplifier;

[0007] The first latch is configured to receive row display data, and latch the received nth row display data to the first latch according to a first latch enable signal; n is a positive integer greater than 1.

[0008] The second latch is configured to latch the value of the high m bits in the (n-1)th row display data latched by the first latch to the second latch according to a second latch enable signal before the first latch latches the nth row display data to the first latch; m is a positive integer greater than or equal to 1.

[0009] The lookup table circuit is configured to determine a first control signal according to a value of high m bits in the n-th row display data output by the first latch and a value of high m bits in the (n-1)-th row display data output by the second latch.

[0010] The operational amplifier is configured to control a number of transistors of the operational amplifier according to the first control signal, and drive the n-th row display data to an output terminal of the operational amplifier by using a driving current provided by a transistor corresponding to the number of transistors.

[0011] In a second aspect, an embodiment of the present application provides a source driving method applied to the source driving circuit, and the method comprises the following steps.

[0012] The first latch receives row display data, and the n-th row display data received is latched to the first latch according to a first latch enable signal; n is a positive integer greater than 1.

[0013] Before the n-th row display data is latched to the first latch, the second latch latches a value of high m bits in the (n-1)-th row display data latched by the first latch to the second latch according to a second latch enable signal; m is a positive integer greater than or equal to 1.

[0014] The lookup table circuit is configured to determine a first control signal according to a value of high m bits in the n-th row display data output by the first latch and a value of high m bits in the (n-1)-th row display data output by the second latch.

[0015] The operational amplifier is configured to control a number of transistors of the operational amplifier according to the first control signal, and drive the n-th row display data to an output terminal of the operational amplifier by using a driving current provided by a transistor corresponding to the number of transistors.

[0016] In a third aspect, an embodiment of the present application provides a display driving system, which comprises the source driving circuit and a display panel; and an output terminal of the operational amplifier in each source driving unit is connected to a data line of the display panel in a one-to-one manner, so that each data line is driven by the source driving unit in a corresponding channel.

[0017] In a fourth aspect, an embodiment of the present application provides a display terminal, which comprises the display driving system or is configured to execute the source driving method.

[0018] The embodiment of the present application provides a source driving circuit, a method, a display driving system and a display terminal, the source driving circuit comprises a plurality of source driving units, each source driving unit comprises: a first latch, a second latch, a lookup table circuit and an operational amplifier; the output end of the first latch is connected with the first input end of the operational amplifier, the input end of the second latch and the first input end of the lookup table circuit respectively, the second input end of the lookup table circuit is also connected with the output end of the second latch, and the output end of the lookup table circuit is connected with the second input end of the operational amplifier; the first latch is used for receiving row display data; and according to the first latch enable signal, the received nth row display data is latched to the first latch; n is a positive integer greater than 1; the second latch is used for latching the value of the high m bits in the (n-1)th row display data latched by the first latch to the second latch according to the second latch enable signal before the first latch latches the nth row display data to the first latch; m is a positive integer greater than or equal to l; the lookup table circuit is used for determining the first control signal according to the value of the high m bits in the nth row display data output by the first latch and the value of the high m bits in the (n-1)th row display data output by the second latch; the operational amplifier is used for controlling the transistor number of the operational amplifier according to the first control signal; and the transistor corresponding to the transistor number is used to drive the nth row display data to the output end of the operational amplifier. By using the above implementation scheme, the first latch is used to latch the nth row display data, the second latch is used to latch the value of the high m bits in the (n-1)th row display data, then the lookup table circuit generates the first control signal for controlling the transistor number in the corresponding operational amplifier by using the values of the high m bits in the adjacent two rows of display data, so that each source driving unit can dynamically adjust the transistor number in the operational amplifier according to the change of the display data of the source driving unit, and further dynamically adjust the driving current of the source driving unit, different current adjustments can be performed for different source driving units, and the flexibility and accuracy of current adjustment are improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A structural schematic diagram of a source driving circuit provided by the embodiment of the present application;

[0020] Figure 2A A structural schematic diagram of an exemplary operational amplifier provided by the embodiment of the present application;

[0021] Figure 2B A structural schematic diagram of another exemplary operational amplifier provided by the embodiment of the present application;

[0022] Figure 3 A structural schematic diagram of an exemplary output stage circuit provided by the embodiment of the present application;

[0023] Figure 4A schematic diagram of an exemplary source drive circuit provided in an embodiment of this application;

[0024] Figure 5 A control timing diagram of a source drive circuit provided in an embodiment of this application;

[0025] Figure 6 A flowchart illustrating a source-driven method provided in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the structure of a display driving system provided in an embodiment of this application. Detailed Implementation

[0027] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0029] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. However, it is understood that "some embodiments" can be the same or different subsets of all possible embodiments and can be combined with each other without conflict. It should also be noted that the terms "first, second, third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. It should also be noted that the term "connection" can refer to a direct connection or a connection via other components.

[0030] This application provides a source drive circuit, which includes multiple source drive units 1, such as... Figure 1 As shown, the source drive unit 1 includes: a first latch 10, a second latch 11, a lookup table circuit 12, and an operational amplifier 13; the output terminal of the first latch 10 is connected to the first input terminal of the operational amplifier 13, the input terminal of the second latch 11, and the first input terminal of the lookup table circuit 12, respectively; the second input terminal of the lookup table circuit 12 is connected to the output terminal of the second latch 11; and the output terminal of the lookup table circuit 12 is connected to the second input terminal of the operational amplifier 13.

[0031] the first latch 10 is configured to receive a row of display data, and latch the received nth row of display data to the first latch according to a first latch enable signal; n is a positive integer greater than 1;

[0032] the second latch 11 is configured to latch the value of the high m bits in the (n-1)th row of display data latched by the first latch to the second latch according to a second latch enable signal before the first latch latches the nth row of display data to the first latch; m is a positive integer greater than or equal to 1;

[0033] the lookup table circuit 12 is configured to determine a first control signal according to the value of the high m bits in the nth row of display data output by the first latch and the value of the high m bits in the (n-1)th row of display data output by the second latch;

[0034] the operational amplifier 13 is configured to control the number of transistors of the operational amplifier according to the first control signal, and drive the nth row of display data to the output terminal of the operational amplifier using the transistors corresponding to the number of transistors.

[0035] In the embodiment of the present application, the operational amplifier determines the number of transistors turned on according to the first control signal, and then the transistors corresponding to the number of transistors turned on obtain corresponding driving current for outputting the nth row of display data.

[0036] In the embodiment of the present application, the first latch and the second latch each include an enable terminal configured to receive a first latch enable signal and a second latch enable signal, respectively, wherein the first latch enable signal and the second latch enable signal are other timing control signals in the source driving chip or are transmitted to the enable terminal of the first latch and the enable terminal of the second latch by a front-end timing controller (TCON); the first latch enable signal is configured to control the first latch to latch the input row of display data to the first latch, and the second latch enable signal is configured to control the second latch to latch the value of the high m bits in the previous row of display data latched by the first latch to the second latch.

[0037] It should be noted that the trigger timing of the second latch enable signal is before triggering the next first latch enable signal, wherein the next first latch enable signal is used to control the first latch to latch the next row of display data. Specifically, the row synchronization signal controls the transmission of the row display data to the source driving circuit, and each adjacent two row synchronization signals correspond to a synchronization period of one row of display data; the trigger timing of the first latch enable signal and the second latch enable signal is that: in the synchronization period of the first row of display data, the first latch enable signal is triggered once, and the first row of display data is latched to the first latch by the first latch; in the synchronization period of the second row of display data, the second latch enable signal is triggered once first, and the first row of display data latched by the first latch is latched to the second latch by the second latch, and then the first latch enable signal is triggered again, and the second row of display data is latched to the first latch by the first latch; and the above process is repeated.

[0038] It should be noted that the first latch includes two latches in series. The first-stage latch is used to receive the row display data and latch the nth row of display data according to the latch enable signal of the first-stage latch. The latch enable signal of each first-stage latch is the output of the shift register, which sequentially enables the data on the data bus to be latched into the first-stage latch of each channel according to the output of the shift register. The latch enable timing of the first-stage latch is based on the time when each channel needs to receive the display data.

[0039] It should be noted that the second-stage latch in the first latch latches the nth row of display data latched by the first-stage latch according to the latch enable signal of the second-stage latch. The second-stage latch of each channel simultaneously latches the data of the corresponding first-stage latch in all channels into the second-stage latch according to the row synchronization signal, and the enable signal of the second-stage latch is basically synchronized with the rising edge of the row synchronization signal.

[0040] In an optional embodiment, the lookup table circuit performs a logical operation on the value of the high m bits in the nth row of display data output by the first latch and the value of the high m bits in the nth-1 row of display data output by the second latch, to obtain difference data between the value of the high m bits in the nth row of display data and the value of the high m bits in the nth-1 row of display data; and then converts the difference data into the first control signal.

[0041] In another alternative embodiment, the look-up table circuit includes a corresponding relation table of display data and control signals, the value of the high m bits of the n-th row display data and the value of the high m bits of the n-1-th row display data are matched with the corresponding relation table, and a first control signal corresponding to the value of the high m bits of the n-th row display data and the value of the high m bits of the n-1-th row display data is found. The logic of the corresponding relation table is to generate a corresponding control signal according to the binary difference between the value of the high m bits of the n-th row display data and the value of the high m bits of the n-1-th row display data.

[0042] Optionally, the second latch 11 is further configured to reset the data latched by the second latch to reset data according to the reset signal.

[0043] The look-up table circuit 12 is further configured to determine a second control signal according to the value of the high m bits of the current row display data output by the first latch and the reset data output by the second latch and transmit the second control signal to the operational amplifier; the current row display data is the display data latched by the first latch when the reset signal is generated.

[0044] In the embodiment of the present application, the second latch further includes a reset terminal, when the polarity control signal (POL) changes, the reset terminal receives an L3RST signal (reset signal), at this time, the second latch resets the display data latched by the second latch to reset data according to the L3RST signal.

[0045] In the embodiment of the present application, the reset signal is generated by other timing control modules in the source driving chip according to the input signal and transmitted to the reset terminal of the second latch.

[0046] It should be noted that the reset data can be data with 0 on each valid bit, and the number of valid bits of the reset data is the same as m.

[0047] In the embodiment of the present application, if the L3RST signal is generated, the look-up table circuit determines the second control signal according to the value of the high m bits of the current row display data output by the first latch and the reset data.

[0048] Optionally, the first latch 10 is further configured to transmit the value of the high m bits of the n-th row display data to the look-up table circuit; m is greater than or equal to 1.

[0049] The second latch 11 is further configured to transmit the value of the high m bits of the n-1-th row display data to the look-up table circuit.

[0050] The look-up table circuit 12 is further configured to determine m control signals according to the value of the high m bits of the n-th row display data and the value of the high m bits of the (n-1)-th row display data and transmit the m control signals to the operational amplifier.

[0051] In the embodiment of the present application, the second latch can latch the value of the high m bits of the (n-1)-th row display data output by the first latch to the second latch. Then, the second latch directly transmits the value of the high m bits of the latched (n-1)-th row display data to the look-up table circuit.

[0052] Optionally, m can be 1, 2, 3, 4, etc., as long as m is not greater than the bit length of the row display data. For m equal to 1, a one-bit look-up table is set in the look-up table circuit, for m equal to 2, a two-bit look-up table is set in the look-up table, for m equal to 3, a three-bit look-up table is set in the look-up table, and the specific selection is made according to the actual situation, which is not limited in the embodiment of the present application.

[0053] For example, the row display data is a 6-bit binary data, for the value of the 5th-6th bit of the n-th row display data DATA n[6:5] and the value of the 5th-6th bit of the (n-1)-th row display data DATA n-1[6:5], the two-bit look-up table of the two-bit control signal control[1:0] is shown in Table 1, and the specific value of control[1:0] is determined according to the binary difference between DATA n[6:5] and DATA n-1[6:5].

[0054] Table 1

[0055] DATA n-1[6:5] DATA n[6:5] control[1:0] 00 00 00 00 01 01 00 10 10 00 11 11 01 00 01 01 01 00 01 10 01 01 11 10 10 00 10 10 01 01 10 10 00 10 11 01 11 00 11 11 01 10 11 10 01 11 11 00

[0056] Optionally, the operational amplifier comprises a first transistor, a plurality of second transistors and m control switches, wherein each control switch is configured to control at least one parallel second transistor in the plurality of second transistors to be connected in parallel with the first transistor; the m control signals are respectively configured to control the on and off of the m control switches, so as to control the number of parallel second transistors in the operational amplifier.

[0057] The source of the first transistor and the source of the plurality of second transistors are connected in parallel, and the drain of the first transistor and the drain of the plurality of second transistors are connected in parallel; a gate wire is led out from the gate of the first transistor, and at least one gate of at least one parallel second transistor is connected to the gate wire through a corresponding control switch.

[0058] In the embodiments of the present application, the bit number of the lookup table determines the bit position of the control signal, the bit number of the control signal is the same as the number of the control switch, and the number of the control switch determines the total number of the plurality of second transistors. Therefore, the bit number of the lookup table determines the number of the plurality of second transistors. The more the bit number of the lookup table is, the more the number of the plurality of second transistors is, so that the area occupied by the operational amplifier is larger, and the driving control precision is higher.

[0059] In the embodiments of the present application, the number of the transistors controlled by the m control switches is 1, 2, 4, and so on. m-1 In this way, the number of the second transistors connected in parallel in the operational amplifier can be selected as 1, 2, 3, 4, and so on.

[0060] In the embodiments of the present application, the number of the first transistors is 1 or more, which is selected according to actual conditions, and the embodiments of the present application are not limited in this regard.

[0061] In the embodiments of the present application, each control signal controls the conduction and closure of one control switch. For Table 1, control[1:0] includes two control signals, which correspond to two control switches. The control signal 0 is used to control the disconnection of the corresponding control switch, and the control signal 1 is used to control the closure of the corresponding control switch. In actual applications, the control signal 1 can also be used to control the disconnection of the corresponding control switch, and the control signal 0 can be used to control the closure of the corresponding control switch. The specific selection can be made according to actual conditions, and the embodiments of the present application are not limited in this regard.

[0062] For the operational amplifier of the source driving circuit, the structure of the operational amplifier can refer to Figure 2A and Figure 2B The operational amplifier includes an input stage circuit and an output stage circuit. The input stage circuit is used to provide a differential voltage signal to the first input end and the second input end of the output stage circuit. The input stage circuit can include a differential input circuit and an AB class control circuit. It should be understood that this is only an example, and the specific implementation of the input stage circuit is related to the function to be achieved by itself. A person skilled in the art can set it according to actual conditions, and this is not limited in this regard. The output stage circuit is mainly composed of a plurality of transistors (each transistor level here corresponds to a transistor of the present application) and control switches. For example, as shown in Figure 3 Each transistor level includes a PMOS tube and an NMOS tube, and the PMOS and NMOS work at the same time. If the input voltage of the previous time is lower than the input voltage of the current time, it indicates that the voltage is rising. At this time, the current flowing out of the NMOS is less than the current provided by the PMOS. If the input voltage of the previous time is higher than the input voltage of the current time, it indicates that the voltage is falling. At this time, the current flowing out of the NMOS is greater than the current provided by the PMOS.

[0063] In the embodiments of the present application, for the scenario of voltage increase, if the control switch 0 and the control switch 1 are disconnected, x1 and y1 are connected in parallel, and the current provided by x1 to the outside is greater than the current output by y1; if the control switch 0 is closed and the control switch 1 is disconnected, x1 and x2, y1 and y2 are connected in parallel, and the current provided by x1 and x2 connected in parallel to the outside is greater than the current output by y1 and y2 connected in parallel to the outside; if the control switch 0 is disconnected and the control switch 1 is closed, x1 and x3, y1 and y3 are connected in parallel, and the current provided by x1 and x3 connected in parallel to the outside is greater than the current output by y1 and y3 connected in parallel to the outside; if the control switch 0 is closed and the control switch 1 is closed, x1, x2 and x3, y1, y2 and y3 are connected in parallel, and the current provided by x1, x2 and x3 connected in parallel to the outside is greater than the current output by y1, y2 and y3 connected in parallel to the outside.

[0064] For the scenario of voltage decrease, if the control switch 0 and the control switch 1 are disconnected, x1 and y1 are connected in parallel, and the current provided by x1 to the outside is less than the current output by y1; if the control switch 0 is closed and the control switch 1 is disconnected, x1 and x2, y1 and y2 are connected in parallel, and the current provided by x1 and x2 connected in parallel to the outside is less than the current output by y1 and y2 connected in parallel to the outside; if the control switch 0 is disconnected and the control switch 1 is closed, x1 and x3, y1 and y3 are connected in parallel, and the current provided by x1 and x3 connected in parallel to the outside is less than the current output by y1 and y3 connected in parallel to the outside; if the control switch 0 is closed and the control switch 1 is closed, x1, x2 and x3, y1, y2 and y3 are connected in parallel, and the current provided by x1, x2 and x3 connected in parallel to the outside is less than the current output by y1, y2 and y3 connected in parallel to the outside.

[0065] Referring to Figure 3 , a scheme of four transistors connected in parallel, wherein M=1 represents one transistor, M=2 represents two transistors, the control switch 0 is used to control the parallel connection of x2 and y2, the control switch 1 is used to control the parallel connection of x3 and y3; the gate of the PMOS tube x1 is connected to the first input end, the gate of the NMOS tube y1 is connected to the second input end, the sources of x1, x2 and x3 are connected in parallel to the VSS line, the sources of y1, y2 and y3 are connected in parallel to the VCC line, and the drains of x1, x2, x3, y1, y2 and y3 are connected in parallel to the output end; a gate connection line is further led out from the gate of x1, x2 is connected to the gate connection line through the control switch 0, and x3 is connected to the gate connection line through the control switch 1; a gate connection line is further led out from the gate of y1, y2 is connected to the gate connection line through the control switch 0, and y3 is connected to the gate connection line through the control switch 1.

[0066] In combination with Table 1 and Figure 3The value of the first bit in control[1:0] is used to control control switch 1, and the value of the second bit in control[1:0] is used to control control switch 0. For example, control[1:0] = 00 indicates that control switch 1 is open and control switch 0 is open; control[1:0] = 01 indicates that control switch 1 is open and control switch 0 is closed; control[1:0] = 10 indicates that control switch 1 is closed and control switch 0 is open; and control[1:0] = 11 indicates that control switch 1 is closed and control switch 0 is closed.

[0067] In combination with Table 1 and Figure 3 The logic of the lookup table is that if the difference of the high two bits is 0 code, control[1:0] = 00, at this time, both control switches are open, and the output stage corresponds to 1 transistor drive; if the difference of the high two bits is 1 code, control[1:0] = 01, at this time, control switch 0 is closed and control switch 1 is open, and the output stage corresponds to 2 transistor drive; if the difference of the high two bits is 2 code, control[1:0] = 10, at this time, control switch 0 is open and control switch 1 is closed, and the output stage corresponds to 3 transistor drive; and if the difference of the high two bits is 3 code, control[1:0] = 11, at this time, control switch 0 is closed and control switch 1 is closed, and the output stage corresponds to 4 transistor drive.

[0068] Optionally, the first transistor and the plurality of second transistors are input stage tail current source transistors of the operational amplifier, or are output stage transistors of the operational amplifier, or are input stage tail current source transistors of the operational amplifier and output stage transistors of the operational amplifier, respectively.

[0069] It should be noted that the number of output stage transistors of the operational amplifier can be controlled to adjust the driving current, or the number of input stage tail current source transistors of the operational amplifier can be controlled to adjust the driving current, or the number of output stage transistors of the operational amplifier and the number of input stage tail current source transistors of the operational amplifier can be controlled to adjust the driving current.

[0070] In the embodiment of the present application, a first level shifter and a decoder are further connected in series between the first latch and the operational amplifier; and a second level shifter is further included between the lookup table circuit and the operational amplifier.

[0071] The first level shifter is configured to boost the row display data and input high-voltage display data obtained by boosting into the decoder.

[0072] The decoder is configured to select a corresponding gamma voltage according to the high-voltage display data and output the corresponding gamma voltage to the operational amplifier.

[0073] The second level shifter is configured to convert the first control signal into a high-voltage control signal and transmit the high-voltage control signal to the operational amplifier.

[0074] The operational amplifier is further configured to control the number of transistors of the input stage or the output stage of the operational amplifier according to the high-voltage control signal, and drive the gamma signal to the output terminal of the operational amplifier by using the driving number of transistors.

[0075] Referring to Figure 4 A source driving circuit is provided for the embodiment of the present application, which comprises a latch L1, a latch L2 (L1 and L2 jointly constitute a first latch), a latch L3 (a second latch), a level shifter LS1, a decoder DEC, an operational amplifier AMP, a lookup table circuit LUT and a level shifter LS2. L1, L2, LS1, DEC and AMP constitute a path of an existing source driving circuit, and a driving control path composed of L3, LUT and LS2 is connected in parallel between L2 and AMP. Among them, Figure 4 The " / " and the corresponding numbers on the connection lines of the respective module circuits in the above embodiment represent the number of data channels between two modules. For example, 6-bit binary data are transmitted on the connection lines of L1, L2, LS1 and DEC, the values of the 6th and 5th bits of the (n-1)th row data Dn-1[6:5] are transmitted on the connection line between L2 and L3, the values of the 6th and 5th bits of the nth row data Dn[6:5] are transmitted on the connection line between L2 and LUT, the values of the 6th and 5th bits of the (n-1)th row data Dn-1[6:5] are transmitted on the connection line between L3 and LUT, 2-bit binary data are transmitted on the connection line between LUT and LS2, and 2-bit control signals control[1:0] are transmitted on the connection line between LS2 and AMP.

[0076] Based on Figure 4L1 and L2 latch display data according to their respective latch enable signals. Under the control of its latch enable signal, L1 latches the input row display data to L1, and L2 latches the row display data latched by L1 to L2 under the control of its latch enable signal. L3 latches the row display data latched by L2 to L3 under the control of its latch enable signal, or resets the data latched by L3 under the control of the reset signal. LS1 converts the level across different voltage domains, transforming the output signal of L2 (i.e., the row display data latched by L2) from logic points to analog points. The decoder DEC selects the corresponding analog voltage output to the AMP based on the output of the level shifter. The AMP then drives the analog voltage from DEC to its output, ultimately driving the data lines of the LCD panel. The LUT generates a 2-bit signal based on the two high-order bits of the nth row of display data output from L2 and the two high-order bits of the (n-1)th row of display data output from L3, through logical operations. This signal is converted into a high-voltage control signal by the level shifter, ultimately controlling the number of transistors in the operational amplifier output stage. This allows for the use of more transistors to provide a larger drive current when the two rows of data change significantly, and the use of fewer transistors to save quiescent current when the two rows of data change little or remain unchanged.

[0077] based on Figure 4 ,like Figure 5 The diagram shows the control timing of the source drive circuit. After generating the row synchronization signal for the nth row of displayed data, L1EN (L1's latch enable signal) is generated. L1 latches the nth row of displayed data into L1 (see...). Figure 5 In step ①), then during the rising edge or high interval of the line synchronization signal for the (n+1)th line of data displayed, L2EN (L2's latch enable signal) is generated, and L2 latches the nth line of display data output by L1 into L2 (see ①). Figure 5 In step ②), after generating the line synchronization signal for the (n+1)th row of displayed data, the next L1EN is generated, and L1 latches the (n+1)th row of displayed data into L1 (see...). Figure 5 (④) Then, L3EN (L3's latch enable signal) is generated. L3 latches the two most significant bits of the nth row of display data output from L2 into L3 (see ④). Figure 5 (③) After that, during the rising edge or high level interval of the row synchronization signal for the (n+2)th row of displayed data, L2EN is generated, and L2 latches the (n+1)th row of displayed data output by L1 into L2 (see ③). Figure 5 (⑤) The lookup table obtains a 2-bit control signal based on the values ​​of the two most significant bits in the nth row of data displayed in L3 and the two most significant bits in the (n+1)th row of data displayed in L2. It should be noted that when the POL signal changes during the row synchronization cycle of the nth row of data displayed, L3rst (the reset signal for L3) is generated (see [reference]). Figure 5In step ⑥), the output of reset L3 is 00. The lookup table circuit obtains a 2-bit control signal based on 00 and the high two bits of the currently latched (n-1)th row of display data of L2.

[0078] Understandably, the first latch latches the nth row of display data, and the second latch latches the high m bits of the (n-1)th row of display data. Then, the lookup table circuit uses the high m bits of the adjacent two rows of display data to generate a first control signal that controls the number of transistors in the corresponding operational amplifier. This allows each source drive unit to dynamically adjust the number of transistors in its own operational amplifier based on changes in its own display data, thereby dynamically adjusting its own drive current. Different current adjustments can be performed for different source drive units, improving the flexibility and accuracy of current adjustment.

[0079] Based on the above source drive circuit, a source drive method is also proposed, such as... Figure 6 As shown, the method may include:

[0080] S101. Receive row display data through the first latch; and latch the received nth row display data to the first latch according to the first latch enable signal; n is a positive integer greater than 1.

[0081] S102. Before the first latch latches the nth row of display data to the first latch, the second latch latches the value of the high m bits of the (n-1)th row of display data latched by the first latch to the second latch according to the second latch enable signal; m is a positive integer greater than or equal to l.

[0082] S103. Determine the first control signal by means of the lookup table circuit and the values ​​of the high m bits in the nth row of the display data output by the first latch and the high m bits in the (n-1)th row of the display data output by the second latch.

[0083] S104. Control the number of transistors in the operational amplifier according to the first control signal; and use the driving current provided by the transistors corresponding to the number of transistors to drive the nth row of display data to the output of the operational amplifier.

[0084] It should be noted that the method descriptions for S101-S104 can be found in the descriptions of the corresponding source drive circuits, and will not be repeated here.

[0085] This application also proposes a display driver system 2, such as Figure 7 As shown, the system 2 includes the above-mentioned source drive circuit and display panel 3; the output terminal of the operational amplifier 13 in each source drive unit 1 is connected to multiple data lines 30 of the display panel 3 in a one-to-one correspondence, so that each data line is driven by the source drive unit of the corresponding channel.

[0086] In the embodiments of the present application, each pixel in the display panel is driven by a separate channel; for each channel, there corresponds one of the above-mentioned source driving circuits, so that each channel can dynamically adjust the number of transistors used by the operational amplifier in the source driving circuit of the channel according to the change of the display data of the front and rear rows in the channel, and further dynamically control the driving current of the channel to drive the data line of the display panel.

[0087] The present application also provides a display terminal comprising the display driving system as described above, or can execute the source driving method as described above. The display terminal is a liquid crystal display device, for example, can be a television, a vehicle-mounted display, a mobile phone, a computer, a wearable electronic device, etc. The specific type of the liquid crystal display device can be selected according to the actual situation, and the embodiments of the present application are not specifically limited.

[0088] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0089] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes a plurality of instructions for causing an image display device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in various embodiments of the present disclosure.

[0090] The above description is only a preferred embodiment of the present application, and is not intended to limit the protection scope of the present application.

Claims

1. A source drive circuit, characterized in that, The source driving circuit comprises a plurality of source driving units, each source driving unit comprising a first latch, a second latch, a lookup table circuit and an operational amplifier; an output terminal of the first latch is connected with a first input terminal of the operational amplifier, an input terminal of the second latch and a first input terminal of the lookup table circuit respectively; a second input terminal of the lookup table circuit is connected with an output terminal of the second latch; and an output terminal of the lookup table circuit is connected with a second input terminal of the operational amplifier; The first latch is configured to receive row display data and latch the received nth row display data to the first latch according to a first latch enable signal; n is a positive integer greater than 1. The second latch is configured to latch the value of the high m bits in the (n-1)th row display data latched by the first latch to the second latch according to a second latch enable signal before the first latch latches the nth row display data to the first latch; m is a positive integer greater than or equal to 1. The lookup table circuit is configured to determine a first control signal according to the value of the high m bits in the nth row display data output by the first latch and the value of the high m bits in the (n-1)th row display data output by the second latch. The operational amplifier is configured to control the number of transistors of the operational amplifier according to the first control signal and drive the nth row display data to the output terminal of the operational amplifier using the transistors corresponding to the number of transistors.

2. The source driving circuit of claim 1, wherein The second latch is further configured to reset the data latched by the second latch to reset data according to a reset signal. The lookup table circuit is further configured to determine a second control signal according to the value of the high m bits in the current row display data output by the first latch and the reset data output by the second latch and transmit the second control signal to the operational amplifier; the current row display data is the display data latched by the first latch when the reset signal is generated.

3. The source driving circuit of claim 1, wherein The first latch is further configured to transmit the value of the high m bits in the nth row display data to the lookup table circuit. The second latch is further configured to transmit the value of the high m bits in the (n-1)th row display data to the lookup table circuit. The lookup table circuit is further configured to determine m control signals according to the value of the high m bits in the nth row display data and the value of the high m bits in the (n-1)th row display data and transmit the m control signals to the operational amplifier.

4. The source driving circuit according to claim 3, wherein The operational amplifier comprises a first transistor, a plurality of second transistors and m control switches; each control switch is configured to control at least one of the plurality of second transistors in parallel with the first transistor; and the m control signals are configured to control the on and off of the m control switches to control the number of transistors in parallel in the operational amplifier. The source of the first transistor and the source of the plurality of second transistors are connected in parallel, and the drain of the first transistor and the drain of the plurality of second transistors are connected in parallel; a gate connection line is led out from the gate of the first transistor, and at least one gate of at least one of the plurality of second transistors is connected to the gate connection line through a corresponding control switch.

5. The source driving circuit according to claim 4, wherein The number of stages of the second transistor controlled by the m control switches is 1, 2, 4, and up to 2 m-1 in turn; wherein the sum of 1, 2, 4, and up to 2 m-1 is the number of the multi-stage second transistor.

6. The source driving circuit according to claim 4, wherein The first transistor and the plurality of second transistors are input stage tail current source transistors of the operational amplifier, or are output stage transistors of the operational amplifier, or are respectively input stage tail current source transistors of the operational amplifier and output stage transistors of the operational amplifier.

7. The source driving circuit according to claim 1, wherein A first level shifter and a decoder are further connected in series between the first latch and the operational amplifier; and a second level shifter is further included between the lookup table circuit and the operational amplifier. The first level shifter is configured to boost the nth row of display data and input high-voltage display data obtained through boosting into the decoder. The decoder is configured to select a corresponding gamma voltage according to the high-voltage display data and output the corresponding gamma voltage to the operational amplifier. The second level shifter is configured to convert the first control signal into a high-voltage control signal and transmit the high-voltage control signal to the operational amplifier. The operational amplifier is further configured to control the number of transistors of the input stage of the operational amplifier or the output stage of the operational amplifier according to the high-voltage control signal, and drive a gamma signal to an output end of the operational amplifier using driving current provided by the number of transistors.

8. A method of driving a source electrode, characterized by, The method is applied to the source driving circuit of any one of claims 1-7, and the method comprises: receiving row display data through a first latch, and latching the nth row of display data received according to a first latch enable signal to the first latch; n is a positive integer greater than 1; before the first latch latches the nth row of display data to the first latch, latching the value of the high m bits in the nth-1 row of display data latched by the first latch to a second latch according to a second latch enable signal; m is a positive integer greater than or equal to 1; determining a first control signal through a lookup table circuit according to the value of the high m bits in the nth row of display data output by the first latch and the value of the high m bits in the nth-1 row of display data output by the second latch; controlling the number of transistors of the operational amplifier through the operational amplifier according to the first control signal, and driving the nth row of display data to an output end of the operational amplifier using driving current provided by the corresponding transistors of the number of transistors.

9. A display driving system, characterized by comprising: The system comprises the source driving circuit of any one of claims 1-7 and a display panel; and the output end of the operational amplifier in each source driving unit is connected to a corresponding data line of the display panel in a one-to-one manner, so that each data line is driven by the source driving unit of the corresponding channel.

10. A display terminal, characterized by The display terminal comprises the display driving system of claim 9, or is configured to execute the source driving method of claim 8. The system comprises the source driving circuit of any one of claims 1-7 and a display panel; and the output end of the operational amplifier in each source driving unit is connected to a corresponding data line of the display panel in a one-to-one manner, so that each data line is driven by the source driving unit of the corresponding channel. The display terminal comprises the display driving system of claim 9, or is configured to execute the source driving method of claim 8.

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