A method for preparing an enhanced GaN-HEMT

Abstract

A preparation method of an enhanced GaN-HEMT. Relate to semiconductor device. The present application realizes the purpose of preparing GaN-HEMT device with same withstand voltage and smaller size or same size and higher withstand voltage by optimizing the epitaxial growth method of GaN-HEMT and subsequent preparation process. By growing regularly arranged AlN layer as a boss on the high-resistance gallium nitride voltage-resistant layer, a uniform-thickness GaN channel layer and AlGaN barrier layer are generated on the basis of the boss, the height Z0 of the high point of the AlGaN barrier layer in the Z direction is detected by using a step detector, at this time, the epitaxial wafer is filled with heavily doped polysilicon, then etched to the Z0 height recorded previously by using a planarization process, then a P-type GaN cap layer is grown, subsequent etching of the gate region is performed, Schottky metal is prepared, and ohmic metal is prepared in the drain-source region, so as to realize the purpose of greatly reducing the device size under the same withstand voltage.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to a method for fabricating an enhanced GaN-HEMT. Background Technology

[0002] Gallium nitride (GaN) is a wide-bandgap semiconductor and a typical representative of third-generation semiconductors. GaN's breakdown electric field is 11 times that of silicon, its bandgap is 3.1 times that of silicon, its heterojunction electron mobility is 1.4 times that of silicon, and its electron saturation drift velocity is 2.7 times that of silicon. Therefore, GaN materials possess characteristics such as high temperature resistance, high voltage resistance, and high frequency performance. Compared with first-generation silicon-based semiconductors, GaN devices have higher voltage withstand capabilities, faster switching frequencies, and lower on-resistance, making them widely used in power electronics.

[0003] Gallium nitride (GaN) material growth is divided into bulk crystal growth and epitaxial growth of crystalline thin films. Bulk crystal growth mainly includes ammonothermal growth, high-pressure growth, and sodium fusion growth, all of which have very low growth rates. Therefore, the mainstream technology for preparing GaN materials is currently heteroepitaxial growth of GaN thin films (from a few micrometers to a few millimeters) on other substrates. Epitaxial growth techniques mainly include MOCVD (Metal-Organic Chemical Vapor Deposition), MBE (Hydride Vapor Phase Epitaxy), and HVPE (Molecular Beam Epitaxy). MOCVD uses a thermal decomposition reaction to perform vapor phase epitaxy on a substrate, growing various compound semiconductors and thin single-crystal materials, and is suitable for generating heterostructure materials. It has advantages such as easy growth control and mass production capability. MBE uses molecular beam or atomic beam deposition on the surface of a heated crystalline substrate for epitaxial deposition, offering the best quality and a hydrogen-free environment. HVPE involves flowing HCl through metallic gallium to form GaCl vapor, which flows to the substrate and reacts with NH3 to deposit GaN. It has the advantages of the fastest growth rate and simplest growth technology.

[0004] The most commonly used substrate materials for GaN heteroepitaxial growth are sapphire, SiC, and Si. Considering factors such as heat dissipation and substrate cost, power devices often choose Si as the substrate material. Because of the large lattice mismatch between Si and GaN, current methods such as transition layers, insertion layers, and in-situ passivation are used to release the stress in the epitaxial material.

[0005] Early GaN materials were primarily used in LED light-emitting devices, laser devices, and photodetectors. It wasn't until 1994 that M.K. Khan discovered that AlGaN and GaN could generate a high-concentration two-dimensional electron gas (2DEG). This is due to the wide bandgap of both AlGaN and GaN materials, resulting in strong voltage withstand capability. Furthermore, the conduction band gradient at the AlGaN and GaN interface exhibits strong piezoelectric and spontaneous polarization effects, which are conducive to forming deep and narrow quantum wells and accumulating high-density 2DEGs. Due to their distribution and transport characteristics, 2DEGs possess significantly higher mobility and saturation velocity than bulk electrons. Therefore, GaN began to be used in ultra-high frequency and high-speed applications. This modulation-doped heterojunction is the basic structure of high electron mobility transistors (HEMTs). The drain and source of the device then form ohmic contacts with the 2DEG, while the gate forms a Schottky contact. The gate voltage controls the switching on and off of the 2DEG. Because depletion-type devices have drawbacks such as false activation, insecurity, and system instability, a P-type GaN layer is often heteroepitaxially grown on top of AlGaN during the epitaxial growth process to prepare enhanced GaNHEMTs.

[0006] Therefore, the traditional fabrication of the entire GaNHEMT includes a silicon substrate, a gradient-grown buffer layer of AlGaN, a high-resistivity breakdown layer of GaN, a GaN channel layer, an AlGaN barrier layer, and a P-type GaN cap layer. The traditional fabrication process includes etching the drain and source regions, depositing ohmic metal in the drain and source regions, etching the P-GaN regions, depositing Schottky metal in the gate regions, and then performing passivation and PAD windowing.

[0007] Although GaNHEMT devices offer superior performance compared to traditional Si devices, several challenges still limit their application. For power devices, size and power density are critical concerns. GaNHEMTs are based on AlGaN and GaN heterojunctions. Currently, the AlGaN barrier layer and GaN channel layer fabricated via heteroepitaxy are planar layers, resulting in horizontal GaNHEMT devices. Compared to SiMOS and SiCMOS devices with vertical structures at the same voltage, they offer advantages in high frequency and heat resistance. However, these devices tend to be larger and have lower power densities, conflicting with the trend towards smaller, more integrated microelectronic devices. Summary of the Invention

[0008] To address the above problems, this invention provides a method for fabricating an enhanced GaN-HEMT device with the same voltage rating but a smaller size, or the same size but a higher voltage rating.

[0009] The technical solution of this invention is: a method for preparing enhanced GaN-HEMT, comprising the following steps:

[0010] S100, a silicon substrate is selected and P-type doped;

[0011] S200, AlGaN transition layer is grown heteroepitaxially on a silicon substrate;

[0012] S300, heteroepitaxial growth of GaN high-resistivity layer on AlGaN transition layer;

[0013] S400, AlN protrusions are heteroepitaxially grown on a GaN high resistivity layer;

[0014] S500, heteroepitaxial growth of GaN channel layer;

[0015] S600, heteroepitaxial growth of AlGaN barrier layer;

[0016] S700, deposited heavily doped polycrystalline silicon;

[0017] S800, deposited P-type GaN cap layer;

[0018] S900, Schottky metal is fabricated in the gate region;

[0019] S100, Grown gate field plate;

[0020] S110, Ohmic metal is prepared in the drain source region.

[0021] Specifically, step S100 includes:

[0022] S110 involves diffusing boron onto a 1mm thick monocrystalline silicon substrate, achieving a resistivity of 1Ω*cm, thus transforming the monocrystalline silicon into a P-type silicon substrate.

[0023] Specifically, step S200 includes:

[0024] S210 uses MOCVD to heteroepitaxially grow an AlGaN layer on a silicon substrate, gradually changing the composition ratio of AlN and GaN, with the first transition layer material being AlN in the order of growth. 0.8 Ga 0.2 N, thickness 0.8µm, second transition layer material Al 0.5 Ga 0.5 N, thickness 0.6µm, third transition layer material Al 0.2 Ga 0.8 N, thickness 0.6um.

[0025] Specifically, in step S210, the first layer is 0.8 μm thick, with an AlN content of 80% and a GaN content of 20%; the second layer is 0.6 μm thick, with an AlN content of 50% and a GaN content of 50%; and the third layer is 0.6 μm thick, with an AlN content of 20% and a GaN content of 80%.

[0026] Specifically, step S300 includes:

[0027] S310, using MOCVD on the transition layer material Al 0.2 Ga 0.8 A GaN high-resistivity layer is heteroepitaxially grown on N-type substrate. The GaN high-resistivity layer has a thickness of 4 μm, is doped with C, and has a resistivity of 10⁻⁶. 9 Ω*cm.

[0028] Specifically, step S400 includes:

[0029] S410 uses MOCVD to heteroepitaxially grow AlN bumps on a GaN high-resistivity layer. The thickness of the AlN bumps is 1µm. After growth, photoresist is coated on the surface of the epitaxial wafer, and exposure and development are performed to form a pattern of 1µm:1µm periodically arranged exposed and unexposed areas. Then, through dry etching and photoresist removal processes, AlN bumps with a thickness of 1µm, a length of 1µm, and a spacing of 1µm between adjacent bumps are finally obtained.

[0030] Specifically, step S500 includes:

[0031] S510, on the periodically arranged AlN protrusions after step S400, a GaN channel layer with a thickness of 0.6 μm is heteroepitaxially grown.

[0032] Specifically, step S600 includes:

[0033] S610 uses MOCVD heteroepitaxial growth of an AlGaN barrier layer with a thickness of 0.1 μm on the GaN channel layer.

[0034] Specifically, step S700 includes:

[0035] S710, a profilometer was used to test the highest point Z0 of the AlGaN barrier layer after suppression epitaxy, and then a 1.2um heavily doped polysilicon was deposited using a PEVCD. After deposition, a planarization process was performed to etch the surface of the epitaxial wafer to the height Z0.

[0036] Specifically, step S800 includes:

[0037] S810 uses MOCVD heteroepitaxial growth of a 0.1µm thick P-type GaN cap layer with Mg as the dopant and a concentration of 5e16.

[0038] This invention optimizes the epitaxial growth method and subsequent fabrication process of GaNHEMTs to achieve the goal of fabricating GaNHEMT devices with the same breakdown voltage but smaller size, or the same size but higher breakdown voltage. It utilizes a regularly arranged AlN layer grown on a high-resistivity gallium nitride breakdown layer as a protrusion. Subsequently, a GaN channel layer and an AlGaN barrier layer of uniform thickness are formed on this protrusion. The height Z0 of the highest point of the AlGaN barrier layer in the Z direction is measured using a profilometer. At this point, the epitaxial wafer is filled with heavily doped polysilicon, and then a planarization process is used to etch to the previously recorded height Z0. A P-type GaN cap layer is then grown, followed by etching of the gate region and fabrication of Schottky metal, and then fabrication of ohmic metal in the drain and source regions. This achieves the goal of significantly reducing the device size while maintaining the same breakdown voltage. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the single-crystal silicon substrate growth and doping in step S100.

[0040] Figure 2 This is a schematic diagram of the AlGaN transition layer generated in step S200.

[0041] Figure 3 This is a schematic diagram of the GaN high-resistivity layer generated in step S300.

[0042] Figure 4 This is a schematic diagram of the structure of the AlN protrusion grown in step S400.

[0043] Figure 5 This is a schematic diagram of the structure of the GaN channel layer grown in step S500.

[0044] Figure 6 This is a schematic diagram of the AlGaN barrier layer generated in step S600.

[0045] Figure 7 This is a schematic diagram of the structure of step S700, which involves depositing heavily doped polycrystalline silicon (planarization treatment onto the AlGaN surface).

[0046] Figure 8 This is a schematic diagram of the structure of the P-type GaN cap layer deposited in step S800.

[0047] Figure 9 This is a schematic diagram of the structure of Schottky metal (0.4 μm) grown in step S900.

[0048] Figure 10 This is a schematic diagram of the structure in step S900 that retains the gate metal and the gate P-type GaN cap layer region.

[0049] Figure 11 This is a schematic diagram of the structure after step S900, which involves depositing a passivation layer and planarizing it.

[0050] Figure 12 This is a schematic diagram of the structure of the gate metal field plate retained in step S1000.

[0051] Figure 13 This is a schematic diagram of the structure after depositing and planarizing the passivation layer in step S1000.

[0052] Figure 14 This is a schematic diagram of the structure from the source / drain region to the GaN high-resistivity layer etched in step S1100.

[0053] Figure 15 This is a schematic diagram of the structure in step S1100 where ohmic metal is deposited in the drain and source regions.

[0054] Figure 16 Both AQ0037 and BZ1023 have an area of ​​4.3 mm². 2 Electrical comparison diagram under different conditions

[0055] Figure 17 The area of ​​AQ0030 is 2.7mm². 2 The area of ​​YFS0584 is 3.6mm². 2 Electrical comparison diagram under different conditions;

[0056] In the figure, 1 is a silicon substrate, and 2 is an Al substrate. 0.8 Ga 0.2 N layers, 3 is Al 0.5 Ga 0.5 N layers, 4 is Al 0.2 Ga 0.8 N is the N-layer, 5 is the GaN high-resistivity layer, 6 is the AlN bump, 7 is the GaN channel layer, 8 is the AlGaN barrier layer, 9 is polysilicon, 10 is the P-type GaN cap layer, 11 is the gate metal, 12 is the metal field plate, 13 is the SiN passivation layer, 14 is the source metal, and 15 is the drain metal. Detailed Implementation

[0057] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0058] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0059] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0060] Process reference Figure 1-15 As shown; taking the newly developed 650V10A GaNHEMT device by the gallium nitride team as an example, the crystal batch number is AQ0037.

[0061] A method for preparing enhanced GaN-HEMT includes the following steps:

[0062] Reference Figure 1 As shown in Figure S100, silicon substrate 1 is selected and P-type doped;

[0063] Further specifying, step S100 includes:

[0064] S110, boron (B) is diffused onto a single-crystal silicon substrate 1 with a thickness of 1 mm, and the resistivity reaches 1 Ω*cm, so that the single-crystal silicon becomes a P-type silicon substrate 1.

[0065] Gallium nitride heteroepitaxial substrate materials are usually silicon carbide, sapphire, or silicon. However, due to the high cost of silicon carbide, which is not suitable for mass production, and the poor heat dissipation performance of sapphire, which is not suitable for power devices, this device uses silicon substrate 1 and the diffusion equipment is HORISD8572A horizontal diffusion furnace.

[0066] Reference Figure 2 As shown, S200, an AlGaN transition layer is heteroepitaxially grown on silicon substrate 1;

[0067] Further specifying, step S200 includes:

[0068] S210, using MOCVD (Metal-Organic Chemical Vapor Deposition) to heteroepitaxially grow an AlGaN layer on silicon substrate 1, gradually changing the composition ratio of AlN and GaN, with the first transition layer material being Al in the order of growth. 0.8 Ga 0.2 N, thickness 0.8µm, second transition layer material Al 0.5 Ga 0.5 N, thickness 0.6µm, third transition layer material Al 0.2 Ga 0.8 N, thickness 0.6um.

[0069] Because silicon and gallium nitride have a high lattice fit, directly growing gallium nitride on silicon substrate 1 will produce many dislocations and defects. Therefore, AlGaN is usually used as a transition layer, and the ratio of AlN to GaN is gradually changed to reduce the lattice fit. The MOCVD equipment used is PrismoUniMax.

[0070] Further specifying, in step S210, the first layer is 0.8 μm thick, with an ALN ​​content of 80% and a GaN content of 20%; the second layer is 0.6 μm thick, with an ALN ​​content of 50% and a GaN content of 50%; and the third layer is 0.6 μm thick, with an ALN ​​content of 20% and a GaN content of 80%.

[0071] Reference Figure 3 As shown, S300, a GaN high-resistivity layer 5 is heteroepitaxially grown on the AlGaN transition layer;

[0072] Further specifying, step S300 includes:

[0073] S310, using MOCVD on the transition layer material Al 0.2 Ga 0.8 A GaN high-resistivity layer 5 is grown heteroepitaxially on N. The GaN high-resistivity layer 5 has a thickness of 4 μm, is doped with C, and has a resistivity of 10⁻⁶. 9 Ω*cm. Since mature GaNHEMT has a horizontal structure, a high-resistivity layer needs to be epitaxially grown to isolate the electrical properties between the device surface and the substrate. The MOCVD equipment used is PrismoUniMax.

[0074] Reference Figure 4 As shown, in S400, AlN protrusions 6 are heteroepitaxially grown on GaN high resistivity layer 5.

[0075] Further specifying, step S400 includes:

[0076] S410 uses MOCVD to heteroepitaxially grow AlN bumps 6 on GaN high resistivity layer 5. The thickness of AlN bumps 6 is 1µm. After growth, photoresist is coated on the surface of the epitaxial wafer, and exposure and development are performed to form a pattern of 1µm:1µm periodically arranged exposed and unexposed areas. Then, through dry etching and photoresist removal processes, AlN bumps 6 with a thickness of 1µm, a length of 1µm, and a spacing of 1µm between adjacent bumps are finally obtained.

[0077] The periodically arranged AlN protrusions 6 generated in this process are designed to allow for a longer two-dimensional electron gas passage distance for the device with the same horizontal width, or in other words, a longer distance between the breakdown interface formed by the AlGaN barrier layer 8 and the GaN channel layer 7, thereby improving the breakdown voltage of the device. The dry etching equipment used is model NIM-4000(M).

[0078] Reference Figure 5 As shown, S500, GaN channel layer 7 is grown heteroepitaxially;

[0079] Further specifying, step S500 includes:

[0080] S510, on the periodically arranged AlN protrusions 6 after step S400, a GaN channel layer 7 with a thickness of 0.6 μm is heteroepitaxially grown. Typically, heteroepitaxial deposition is isotropic. The generated GaN channel layer 7 will have a strong piezoelectric and spontaneous polarization effect with the subsequently epitaxially grown AlGaN, forming a deep and narrow quantum well, resulting in a high concentration of 2DEG.

[0081] Reference Figure 6 As shown, S600, an AlGaN barrier layer 8 is grown heteroepitaxially;

[0082] Further specifying, step S600 includes:

[0083] S610, an AlGaN barrier layer 8 with a thickness of 0.1 μm is grown on the GaN channel layer 7 using MOCVD heteroepitaxial growth.

[0084] Typically, heteroepitaxial deposition is isotropic. The generated AlGaN barrier layer 8 will have a strong piezoelectric and spontaneous polarization effect with the GaN channel layer 7 grown earlier, forming a deep and narrow quantum well and a high concentration of 2DEG.

[0085] Reference Figure 7 As shown, S700 is a deposited heavily doped polycrystalline silicon 9;

[0086] Further specifying, step S700 includes:

[0087] S710, a step tester was used to measure the highest point Z0 of the AlGaN barrier layer 8 after epitaxy. Then, a 1.2µm heavily doped polysilicon 9 was deposited using a PEVCD. After deposition, a planarization process was performed to etch the surface of the epitaxial wafer to the height Z0.

[0088] The deposition of heavily doped polycrystalline silicon (9) process is to avoid affecting the 2DEG concentration between AlGaN and GaN, and to make the surface of the epitaxial wafer flat after the planarization process, so as to ensure that the P-type GaN layer deposition thickness is uniform in the subsequent epitaxial growth process. The deposition equipment used is EquipmentModel PD-520.

[0089] Reference Figure 8 As shown, S800, deposited P-type GaN cap layer 10;

[0090] Further specifying, step S800 includes:

[0091] S810 uses MOCVD heteroepitaxial growth to grow a 0.1 μm thick P-type GaN cap layer 10, with Mg as the dopant element and a concentration of 5e16.

[0092] The GaN cap layer serves to turn on the device only when a positive voltage is applied to the gate, transforming the device from an enhancement-mode to a depletion-mode device. Furthermore, since gallium nitride is a group III-V element, the thickness of the p-type GaN cap layer (10) directly affects the device's Vth; based on the design's typical Vth value of 2.5V, a thickness of 0.1µm is chosen.

[0093] Reference Figure 9 As shown, in S900, Schottky metal is fabricated in the gate region;

[0094] Further specifying, step S900 includes:

[0095] S910: A 0.4µm thick Schottky metal layer is deposited on the P-type GaN cap layer 10. Photoresist is applied to the epitaxial wafer surface, followed by exposure and development processes. The photoresist only protects the gate region. Dry etching and photoresist removal processes are then used to etch away the metal and P-type GaN cap layer 10 in other areas, ultimately obtaining a 1µm wide and 0.4µm thick gate Schottky metal layer and a 1µm wide and 0.1µm thick P-type GaN cap layer 10. The gate metal 11 and P-type GaN cap layer 10 are retained (see reference). Figure 10 After the SiN passivation layer 13 is deposited (as shown), the device surface is then planarized using a planarization process (see reference). Figure 11(As shown). In this step, it is important to ensure that the retained P-type GaN and gate metal 11 regions correspond to the AlN regions grown in S500, so that the gate region is located directly above a certain AlN region. The retained P-type GaN cap layer 10 is parallel to the AlGaN barrier layer 8 below, ensuring the stability of gate control. The deposited Schottky metal is Ni / Au, with thicknesses of 0.1µm / 0.3µm, respectively.

[0096] S100, Grown gate field plate;

[0097] Further specifying, step S1000 includes:

[0098] Based on the S910 process, a gate field plate metal Ti with a thickness of 0.2 μm is deposited. A pattern is formed by coating photoresist on the epitaxial wafer surface and performing exposure and development processes. Then, through dry etching and photoresist removal processes, a metal field plate 12 with a width of 4 μm and a thickness of 0.2 μm is finally obtained. The metal field plate 12 is retained (refer to...). Figure 12 (As shown) After depositing a SiN passivation layer 13, the device surface is then planarized using a planarization process (see reference). Figure 13 (As shown). The function of the metal field plate 12 is to avoid electric field spikes when high voltage is applied, and the field plate plays a role in smoothing the electric field.

[0099] S110, Ohmic metal is prepared in the drain-source region;

[0100] Further specifying, step S1100 includes:

[0101] By coating photoresist on the surface of the epitaxial wafer and performing exposure and development processes to form a pattern, and then through dry etching and photoresist removal processes, the drain and source regions are finally etched down to the GaN high-resistivity layer 5 region (refer to...). Figure 14 As shown), redeposit ohmic metal (refer to...) Figure 15 As shown in the figure, a drain source metal with a width of 3 μm and a thickness of 0.4 μm was obtained. The deposited ohmic metal was Ti / Al / Ni / Au with thicknesses of 0.1 μm / 0.1 μm / 0.1 μm / 0.1 μm, respectively. After the ohmic metal was deposited, aluminum metal was deposited for application-side welding.

[0102] The above completes the fabrication process of the entire device, achieving the goal of having a longer distance between the breakdown voltage interface composed of AlGaN barrier layer 8 and GaN channel layer 7 under the same area, thereby improving the breakdown voltage of the device; or, under the requirement of the same breakdown voltage, this design can be realized on a smaller area device, improving the power density of the device, which is an important innovation in the field of GaNHEMT devices.

[0103] The GaNHEMT product (4.3mm) with batch number AQ0037 was developed using this method. 2Compared to the market-leading BZ1023 product with the same chip area, the AQ0037 has a withstand voltage of 895V, compared to the BZ1023's 670V, a difference of 225V (33.58% higher withstand voltage for the same device area). Figure 16 As shown. The GaNHEMT product (BVDSS typical value 566V) developed using this method, batch AQ0030 (typical value 561V), has a surface area of ​​2.7 mm². Compared to the market-leading YFS0584 product (typical value 561V), the AQ0030 product has a surface area of ​​2.7 mm². 2 The area of ​​YFS0584 is 3.6mm². 2 AQ0030 has a smaller area by 0.9mm. 2 (Same voltage, smaller area by 25%), refer to Figure 17 As shown.

[0104] An enhanced GaN-HEMT includes a silicon substrate 1 and an Al2O3 substrate 1 arranged sequentially from bottom to top. 0.8 Ga 0.2 N layer 2, Al 0.5 Ga 0.5 N layer 3, Al 0.2 Ga 0.8 N-layer 4 and GaN high-resistivity layer 5;

[0105] The top surface of the GaN high-resistivity layer 5 is provided with a number of spaced AlN protrusions 6 to form protrusions and increase the path of LGd.

[0106] The top surface of the GaN high-resistivity layer 5 is provided with a GaN channel layer 7 through a plurality of AlN protrusions 6.

[0107] An AlGaN barrier layer 8 is provided on the GaN channel layer 7; the AlGaN barrier layer 8 and the GaN channel layer 7 undergo a piezoelectric polarization effect to form a two-dimensional electron gas.

[0108] On the AlGaN barrier layer 8, polysilicon 9 for filling is provided between the connected AlN protrusions 6;

[0109] The AlGaN barrier layer 8 is provided with a SiN passivation layer 13 (in order to isolate it from external electrical contact, avoid arcing, and form a passivation effect). The SiN passivation layer 13 is provided with a metal field plate 12 extending in the horizontal direction, which smooths the electric field and avoids the existence of electric field spikes.

[0110] One end of the SiN passivation layer 13 is provided with a source metal 14 extending downward to the GaN high-resistivity layer 5. The source metal 14 is provided so that the source can lead out a metal line to form an electrical connection. The other end is provided with a drain metal 15 extending downward to the GaN high-resistivity layer 5. The drain metal 15 is provided so that the drain can lead out a metal line to form an electrical connection.

[0111] Near the end of the AlGaN barrier layer 8, a P-type GaN cap layer 10 is provided on top; a gate metal 11 extending into the SiN passivation layer 13 is provided on top of the P-type GaN cap layer 10. The Mg-doped GaN cap layer 10 is used to control the conduction and cutoff of the two-dimensional electron gas, making the product an enhancement-mode device.

[0112] Regarding the information disclosed in this case, the following points need to be clarified:

[0113] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.

[0114] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0115] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for preparing enhanced GaN-HEMT, characterized in that, Includes the following steps: S100, a silicon substrate is selected and P-type doped; S200, AlGaN transition layer is grown heteroepitaxially on a silicon substrate; S300, heteroepitaxial growth of GaN high-resistivity layer on AlGaN transition layer; S400, AlN protrusions are heteroepitaxially grown on a GaN high resistivity layer; S410 uses MOCVD to heteroepitaxially grow AlN bumps on a GaN high resistivity layer. The thickness of the AlN bumps is 1µm. After growth, photoresist is coated on the surface of the epitaxial wafer, and exposure and development are performed to form a pattern of 1µm:1µm periodically arranged exposed and unexposed areas. Then, through dry etching and photoresist removal processes, AlN bumps with a thickness of 1µm, a length of 1µm, and a spacing of 1µm between adjacent AlN bumps are finally obtained. S500, heteroepitaxial growth of GaN channel layer; S510, on the periodically arranged AlN protrusions after step S400, a GaN channel layer with a thickness of 0.6 μm is heteroepitaxially grown. S600, heteroepitaxial growth of AlGaN barrier layer; S610, an AlGaN barrier layer with a thickness of 0.1 μm is grown on the GaN channel layer using MOCVD heteroepitaxial growth. S700, deposited heavily doped polycrystalline silicon; S710, the step profiler was used to test the highest point Z0 of the AlGaN barrier layer after suppression epitaxy, and then 1.2um of heavily doped polysilicon was deposited using PEVCD. After deposition, a planarization process was performed to etch the surface of the epitaxial wafer to the height Z0. S800, deposited P-type GaN cap layer; S900, Schottky metal is fabricated in the gate region; S100, Grown gate field plate; S110, Ohmic metal is prepared in the drain source region.

2. The method for preparing an enhanced GaN-HEMT according to claim 1, characterized in that, Step S100 includes: S110, diffusing boron on a single-crystal silicon substrate to achieve a resistivity of 1Ω*cm, thereby transforming the single-crystal silicon into a P-type silicon substrate.

3. The method for preparing an enhanced GaN-HEMT according to claim 1, characterized in that, Step S200 includes: S210, using MOCVD to heteroepitaxially grow an AlGaN layer on a silicon substrate, and gradually changing the composition ratio of AlN and GaN, with Al being the first transition layer material in the order of growth. 0.8 Ga 0.2 N, thickness 0.8µm, second transition layer material Al 0.5 Ga 0.5 N, thickness 0.6µm, third transition layer material Al 0.2 Ga 0.8 N, thickness 0.6um.

4. The method for preparing an enhanced GaN-HEMT according to claim 3, characterized in that, In step S210, the first layer is 0.8 μm thick, with 80% AlN and 20% GaN; the second layer is 0.6 μm thick, with 50% AlN and 50% GaN; and the third layer is 0.6 μm thick, with 20% AlN and 80% GaN.

5. The method for preparing an enhanced GaN-HEMT according to claim 1, characterized in that, Step S300 includes: S310, using MOCVD on the transition layer material Al 0.2 Ga 0.8 A GaN high-resistivity layer is heteroepitaxially grown on N-type substrate. The GaN high-resistivity layer has a thickness of 4 μm, is doped with C, and has a resistivity of 10⁻⁶. 9 Ω*cm.

6. The method for preparing an enhanced GaN-HEMT according to claim 1, characterized in that, Step S800 includes: S810, growing a 0.1 μm thick P-type GaN cap layer using MOCVD heteroepitaxial growth, with Mg as the dopant and a concentration of 5e. 16 .

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