Voltage-mode transmitter

Abstract

A voltage mode transmitter includes a serializer, a front-end driver circuit, a driver circuit, and a resistance correction circuit. The serializer is configured to convert a data into a serial data. The front-end driver circuit is configured to drive the serial data. The driver circuit includes a slice, a replica slice, a reference voltage generation circuit, a first operational amplifier, and a second operational amplifier. The reference voltage generation circuit is coupled between a first operating voltage and a second operating voltage and includes a resistance. The resistance correction circuit is configured to generate a reference voltage using a first current source and a reference resistance, wherein the first current source is a current source corrected by a bandgap reference circuit, generate a target voltage using a second current source flowing through the resistance, and adjust the resistance according to the reference voltage and the target voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to a voltage mode transmitter, and in particular to a driving circuit of a voltage mode transmitter and a resistance correction circuit thereof. BACKGROUND

[0002] Fig. 1 is a schematic diagram of a prior art chip. The chip 10 comprises a main circuit 110, a serializer 120, a pre-driver circuit 130 and a driving circuit 140. The serializer 120 serializes parallel data DP generated by the main circuit 110 according to a clock signal CLK to generate serial data DS, which then passes through the pre-driver circuit 130 and the driving circuit 140 before being outputted by the pin PD1 and the pin PD2. RL is a load resistance. The pre-driver circuit 130 and the driving circuit 140 are used to drive the output of the serial data DS, the principle of which is well known to those skilled in the art and will not be described in detail.

[0003] The internal resistance of the driving circuit 140 needs to be matched with the load resistance RL. However, some factors (e.g. process, voltage, temperature changes) can cause the resistance value of the internal resistance of the driving circuit 140 to change, so the prior art uses an external resistance RE (located outside the chip 10) with a precise resistance value as a reference to correct the internal resistance of the driving circuit 140. The disadvantage of the prior art is that the chip 10 needs to provide additional pins PD3 and PD4, resulting in a larger area and increased cost of the chip 10. SUMMARY

[0004] The present application aims to provide a voltage mode transmitter to improve the deficiencies of the prior art.

[0005] Some embodiments of the present application provide a voltage-mode transmitter. The voltage-mode transmitter outputs signals through a first output pin and a second output pin, and includes a serializer, a front-end driver circuit, a driver circuit, and a resistance correction circuit. The serializer is configured to convert a data into a serial data. The front-end driver circuit is coupled to the serializer and configured to drive the serial data. The driver circuit includes a slice, a replica slice, a reference voltage generation circuit, a first operational amplifier, and a second operational amplifier. The slice includes a first transistor and a second transistor, and is configured to provide an output signal to the first output pin or the second output pin. The replica slice is coupled to the slice and includes a third transistor and a fourth transistor, wherein a first gate of the first transistor is coupled to a third gate of the third transistor, and a second gate of the second transistor is coupled to a fourth gate of the fourth transistor. The reference voltage generation circuit is coupled between a first operating voltage and a second operating voltage and includes a resistance, and is configured to generate a first reference voltage and a second reference voltage at two ends of the resistance, respectively. The first operational amplifier is coupled between the replica slice and the reference voltage generation circuit, and is configured to receive the first reference voltage and provide a first gate voltage to the first gate and the third gate. The second operational amplifier is coupled between the replica slice and the reference voltage generation circuit, and is configured to receive the second reference voltage and provide a second gate voltage to the second gate and the fourth gate. The resistance correction circuit is configured to generate a third reference voltage using a first current source and a reference resistance, wherein the first current source is a current source corrected by a band-gap reference circuit, generate a target voltage using a second current source flowing through the resistance, and adjust the resistance according to the third reference voltage and the target voltage.

[0006] The voltage-mode transmitter of the present application does not need an external resistance to compensate or correct the resistance value variation caused by process variation. Compared with the prior art, the chip using the voltage-mode transmitter of the present application can reduce pins.

[0007] The features, implementations, and effects of the present application will be described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1 is a schematic diagram of a prior art chip;

[0009] Figure 2 FIG. 2 is a functional block diagram of a chip according to some embodiments of the present application;

[0010] Figure 3 FIG. 3 is a circuit diagram of a driver circuit according to some embodiments of the present application;

[0011] Figure 4 a circuit diagram of a resistance correction circuit according to some embodiments of the present application; and

[0012] Figure 5 a schematic diagram of a current source using a bandgap reference circuit according to some embodiments of the present application.

[0013] BRIEF DESCRIPTION OF DRAWINGS

[0014]

[0015] DETAILED DESCRIPTION

[0016] The technical terms in the following description are used in reference to the usual terms in the art, and the explanations of the terms are based on the descriptions or definitions in the specification.

[0017] The disclosure of the present application includes a voltage-mode transmitter. Since some of the elements included in the voltage-mode transmitter of the present application can be known elements individually, the following description will omit the details of the known elements without affecting the sufficient disclosure and implementability of the device application.

[0018] Figure 2 a functional block diagram of a chip according to some embodiments of the present application. The chip 20 (e.g., a System on a Chip (SoC)) includes a main circuit 210 and a voltage-mode transmitter 215. The main circuit 210 operates according to a clock signal CLK to implement the main functions of the chip 20, and the voltage-mode transmitter 215 converts parallel data DP generated by the main circuit 210 into serial data DS and outputs the serial data DS through output pins PD1 and PD2 of the chip 20. The functions and operating principles of the serializer 220 and the front-end driver circuit 230 are the same as those of the serializer 120 and the front-end driver circuit 130, respectively, and thus will not be described again. A driver circuit 300 is used to drive the serial data DS. The present application corrects the resistance inside the driver circuit 300 using a resistance correction circuit 400 inside the chip 20, and thus the chip 20 of the present application does not need an additional pin to connect an external resistance.

[0019] Figure 3 a circuit diagram of the driver circuit 300 according to some embodiments of the present application. The driver circuit 300 includes a reference voltage generation circuit 310, an operational amplifier 320, an operational amplifier 330, a replica slice 340, and a slice 350.

[0020] The reference voltage generation circuit 310 includes resistors Rl, R7, and R2, the resistance value of resistor R7 being adjustable. Resistors Rl, R7, and R2 are connected in series between a working voltage VDD and a working voltage Vref (VDD > Vref, Vref can be a ground reference voltage). More specifically, one end of resistor Rl is coupled or electrically connected to the working voltage VDD, and the other end of resistor Rl is coupled or electrically connected to a node Nl; one end of resistor R7 is coupled or electrically connected to the node Nl, and the other end of resistor R7 is coupled or electrically connected to a node N2; one end of resistor R2 is coupled or electrically connected to the node N2, and the other end of resistor R2 is coupled or electrically connected to the working voltage Vref. Through resistive voltage division, the reference voltage generation circuit 310 generates a reference voltage Vrl and a reference voltage Vr2 on the node Nl and the node N2, respectively. If the resistance value of resistor R7 changes, the reference voltage Vrl and the reference voltage Vr2 change.

[0021] The operational amplifier 320 has two input terminals and one output terminal. One of the input terminals of the operational amplifier 320 is coupled or electrically connected to the node Nl, and the other input terminal of the operational amplifier 320 is coupled or electrically connected to a node N3, and the output terminal of the operational amplifier 320 outputs a gate voltage Vgp. The operational amplifier 330 has two input terminals and one output terminal. One of the input terminals of the operational amplifier 330 is coupled or electrically connected to the node N2, and the other input terminal of the operational amplifier 330 is coupled or electrically connected to a node N4, and the output terminal of the operational amplifier 330 outputs a gate voltage Vgn. Those skilled in the art can know that the operational amplifier 320 and the operational amplifier 330 generate a voltage Vl and a voltage V2 on the node N3 and the node N4, respectively, and the voltage Vl and the voltage V2 are substantially equal to the reference voltage Vrl and the reference voltage Vr2, respectively.

[0022] The replica slice 340 includes transistors Ml, M2, resistors R3, R4, and R8. The source of transistor Ml is coupled or electrically connected to the working voltage VDD, and the gate of transistor Ml is coupled or electrically connected to the output terminal of the operational amplifier 320. The source of transistor M2 is coupled or electrically connected to the working voltage Vref, and the gate of transistor M2 is coupled or electrically connected to the output terminal of the operational amplifier 330. Resistors R3, R8, and R4 are connected in series between the drain of transistor Ml and the drain of transistor M2. More specifically, one end of resistor R3 is coupled or electrically connected to the drain of transistor Ml, and the other end of resistor R3 is coupled or electrically connected to the node N3; one end of resistor R8 is coupled or electrically connected to the node N3, and the other end of resistor R8 is coupled or electrically connected to the node N4; one end of resistor R4 is coupled or electrically connected to the node N4, and the other end of resistor R4 is coupled or electrically connected to the drain of transistor M2.

[0023] The slice 350 includes a transistor M3, a transistor M4, a resistor R5, a resistor R6, and a switch circuit 352. The source of the transistor M3 is coupled or electrically connected to the working voltage VDD, and the gate of the transistor M3 is coupled or electrically connected to the output of the operational amplifier 320. The source of the transistor M4 is coupled or electrically connected to the working voltage Vref, and the gate of the transistor M4 is coupled or electrically connected to the output of the operational amplifier 330. The switch circuit 352 is coupled between the drain of the transistor M3 and the drain of the transistor M4. One end of the resistor R5 is coupled or electrically connected to the switch circuit 352, and the other end of the resistor R5 is coupled or electrically connected to the output pin PD1. One end of the resistor R6 is coupled or electrically connected to the switch circuit 352, and the other end of the resistor R6 is coupled or electrically connected to the output pin PD2. The switch circuit 352 outputs a current I1 from the output pin PD1 or a current I2 from the output pin PD2 according to the serial data DS. The path of the current I1 is: M3→R5→RL→R6→M4, and the path of the current I2 is: M3→R6→RL→R5→M4. Those skilled in the art know how to implement the switch circuit 352 in logic circuits and transistors, and thus the details are not described herein. The present application is not limited to the implementation of the switch circuit 352.

[0024] Referring to Figure 3 In one embodiment (not intended to limit the present application), the resistance value of the resistor R1 is substantially equal to the resistance value of the resistor R2, and the resistance values of the resistors R3, R4, R5, and R6 are substantially the same.

[0025] Figure 3 Only one slice 350 is shown, however, in other embodiments, the driving circuit 300 can include K slices 350 in parallel (K>2), and the resistance value of the resistor R8 is ideally equal to K times the resistance value of the load resistor RL. Those skilled in the art know how to parallel multiple slices 350, and thus the details are not described herein.

[0026] The gate voltage Vgp and the gate voltage Vgn control the impedance matching of the transistors M3 and M4, respectively, to resist or offset process, voltage, and temperature variations. The resistance value variation of the resistor R8 is compensated or corrected by adjusting the resistance value of the resistor R7, which is adjusted by the resistance correction circuit 400. In other words, the present application indirectly compensates or corrects the resistor R8 by adjusting the resistor R7.

[0027] Figure 4 A circuit diagram of the resistance correction circuit 400 according to some embodiments of the present application is shown. The resistance correction circuit 400 includes a reference resistor R9, a comparator 412, a logic circuit 414, a current source 416 (with a current value IBx), and a current source 418 (with a current value IBt). As shown in FIG. 4, the reference resistor R9 is coupled or electrically connected between the output pin PD1 and the output pin PD2. The output of the comparator 412 is coupled or electrically connected to the logic circuit 414. The current source 416 is coupled or electrically connected to the logic circuit 414, and the current source 418 is coupled or electrically connected to the logic circuit 414. The logic circuit 414 is coupled or electrically connected to the resistor R7. Figure 4As shown, the current of current source 416 flows through reference resistor R9, such that the reference voltage Vr3 at node N5 is equal to VDD-R9*IBx; the current of current source 418 flows through resistor R7, such that the target voltage Vx at node N6 is equal to VDD-R7*IBt. Comparator 412 and logic circuit 414 adjust the resistance value of resistor R7 according to the reference voltage Vr3 and the target voltage Vx. More specifically, comparator 412 compares the reference voltage Vr3 and the target voltage Vx to generate a comparison result CR. When the comparison result CR indicates that the reference voltage Vr3 is greater than the target voltage Vx, logic circuit 414 controls the resistance value of resistor R7 to become smaller, so as to make the target voltage Vx become greater. When the comparison result CR indicates that the reference voltage Vr3 is smaller than the target voltage Vx, logic circuit 414 controls the resistance value of resistor R7 to become greater, so as to make the target voltage Vx become smaller. Those skilled in the art can implement logic circuit 414 according to the above-mentioned operation logic, and thus the details thereof will not be described herein. The present application is not limited to the implementation of logic circuit 414.

[0028] As shown in FIG. 4, reference resistor R9, current source 416, and current source 418 are part of voltage-mode transmitter 215. In other words, reference resistor R9, current source 416, and current source 418 are located inside chip 20. Figure 2 Figure 4 As shown in FIG. 4, reference resistor R9, current source 416, and current source 418 are part of voltage-mode transmitter 215. In other words, reference resistor R9, current source 416, and current source 418 are located inside chip 20.

[0029] Please refer to FIG. 5 for further details. Figure 4 Resistor R7 and reference resistor R9 are both on-chip resistors, and thus are subject to process variation. Current source 416 is a current source that has been corrected by a Bandgap Reference (BGR), while current source 418 is a current source that has not been corrected. In other words, current source 418 is subject to process variation, while current source 416 is not. That is, resistance correction circuit 400 first learns the difference between current source 416 and current source 418 (i.e., the degree of influence of process variation) by comparing reference voltage Vr3 and target voltage Vx, and then compensates for process variation by adjusting resistor R7. Please refer to FIG. 6 for further details. Figure 3 Because the voltage across resistor R7 is substantially equal to the voltage across resistor R8, adjusting resistor R7 is equivalent to correcting resistor R8.

[0030] In one embodiment (not intended to limit the present application), the resistance value of reference resistor R9 is substantially equal to the resistance value (Rx) of resistor R1 and resistor R2, and the resistance value of resistor R7 is substantially equal to Rx±0.1Rx. Here, "±0.1Rx" is the adjustable range of resistor R7, i.e., the predicted range of process variation.

[0031] Figure 5 ​A schematic diagram of correcting the current source 416 using a bandgap reference circuit according to some embodiments of the present application is shown. The bandgap reference circuit 500 is coupled or electrically connected to the current source 416, and is coupled to the operating voltage Vref through a resistor R10. The resistor R10 is a tunable resistor. The current source 416 can be corrected by changing the voltage across the resistor R10, which is well known to those skilled in the art, and thus will not be described in detail.

[0032] In summary, the present application corrects the resistance of the driving circuit 300 of the voltage mode transmitter 215 to overcome the process variation without using an external resistor.

[0033] The shapes, sizes, and proportions of the elements shown in the above-described figures are for example only and are not intended to limit the present application, which is defined by the claims.

[0034] Although the embodiments of the present application have been described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, which changes can all fall within the scope of the patent protection sought for the present application. In other words, the scope of the patent protection of the present application should be defined according to the claims of the present application.

Claims

1. A voltage mode transmitter outputting a signal through a first output pin and a second output pin, comprising: a serializer configured to convert a data into a serial data; a front-end driver circuit coupled to the serializer and configured to drive the serial data; a driver circuit comprising: a slice comprising a first transistor and a second transistor configured to provide an output signal to the first output pin or the second output pin; a replica slice coupled to the slice and comprising a third transistor and a fourth transistor, wherein a first gate of the first transistor is coupled to a third gate of the third transistor and a second gate of the second transistor is coupled to a fourth gate of the fourth transistor; a reference voltage generation circuit coupled between a first operating voltage and a second operating voltage and comprising a resistor configured to generate a first reference voltage and a second reference voltage at two ends of the resistor, respectively; a first operational amplifier coupled between the replica slice and the reference voltage generation circuit and configured to receive the first reference voltage and provide a first gate voltage to the first gate and the third gate; and a second operational amplifier coupled between the replica slice and the reference voltage generation circuit and configured to receive the second reference voltage and provide a second gate voltage to the second gate and the fourth gate; and a resistance correction circuit configured to: generate a third reference voltage using a first current source and a reference resistor, wherein the first current source is a current source corrected by a bandgap reference circuit; generate a target voltage using a second current source flowing through the resistor; and adjust the resistor according to the third reference voltage and the target voltage.

2. The voltage-mode transmitter of claim 1, wherein, The resistor is a first resistor, and the replica slice further comprises: a second resistor having a first end and a second end, the first end coupled to an input of the first operational amplifier, and the second end coupled to an input of the second operational amplifier; a third resistor coupled between the third transistor and the second resistor; and a fourth resistor coupled between the second resistor and the fourth transistor.

3. The voltage-mode transmitter of claim 2, wherein, The slice further comprises: a switch circuit coupled to the first transistor and the second transistor and configured to receive the serial data; a fifth resistor coupled between the switch circuit and the first output pin; and a sixth resistor coupled between the switch circuit and the second output pin.

4. The voltage-mode transmitter of claim 3, wherein, The third resistor, the fourth resistor, the fifth resistor, and the sixth resistor have equal resistance values.

5. The voltage-mode transmitter of claim 1, wherein, The resistor is a first resistor, and the slice further comprises: a switch circuit coupled to the first transistor and the second transistor and configured to receive the serial data; a second resistor coupled between the switch circuit and the first output pin; and a third resistor coupled between the switch circuit and the second output pin.

6. The voltage-mode transmitter of claim 1, wherein, The resistor is a first resistor, and the reference voltage generation circuit further comprises: a second resistor coupled between the first resistor and the first operating voltage; and a third resistor coupled between the second resistor and the second operating voltage. a third resistor coupled between the first resistor and the second operating voltage; wherein the second resistor is electrically connected to an input of the first operational amplifier, and the third resistor is electrically connected to an input of the second operational amplifier.

7. The voltage-mode transmitter of claim 1, wherein, The resistance correction circuit further comprises: a comparator for comparing the third reference voltage and the target voltage to generate a comparison result; and a logic circuit coupled to the comparator and the resistance for adjusting the resistance value of the resistance according to the comparison result.

8. The voltage-mode transmitter of claim 1, the voltage-mode transmitter being part of a chip, and the reference resistance being located within the chip.

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