A method for reducing loss of large dynamic FFT operation by truncation and number system conversion

Abstract

The application discloses a method for reducing the loss of large dynamic FFT operation by truncation and number system conversion, and relates to the field of radar signal processing. Firstly, by selecting appropriate rotation factor quantization bits and complex multiplication truncation bits, the full frequency domain precision loss is ensured to be not more than a fixed value under the condition of small signal input; then, whether to retain the bit width increased by complex addition operation is judged according to the order corresponding to the number of FFT points required to be operated; finally, according to the operation bit width truncation rule, after completing the entire FFT operation, the FFT operation result represented by fixed-point numbers is converted into the FFT operation result represented by floating-point numbers. The application can effectively retain the spectrum information under the condition of small signal input, avoid the signal distortion caused by the truncation in the FFT processing process, greatly improve the dynamic range, and provide good data support for subsequent fine processing.

Description

Technical Field

[0001] This invention relates to the field of radar signal processing. Background Technology

[0002] In current practical applications of radar signal processing, FFT is widely used in various scenarios such as beamforming, spectrum representation, and fast computation. In radar front-ends, fixed-point FFT is generally used for beamforming. However, this method involves truncation operations involving successive multiplication and addition. For large signals, this can lead to partial signal distortion; for small signals, it may result in complete signal truncation, causing errors.

[0003] To address the aforementioned issues, floating-point FFT can be used to improve the system's dynamic range. However, this method is rarely used due to its high resource consumption and complex computational nature. To address the problems with floating-point FFT, some literature has proposed using block floating-point FFT. While this method can improve the dynamic range to some extent, it can only retain a portion of the signal precision due to limitations in mantissa length. In engineering practice, fixed-point FFT is typically used to form multiple digital beams. During the computation, multi-stage butterfly fixed-point operations cause the processing bit width to increase exponentially with each stage, increasing processing resource consumption and final-stage I / O bandwidth requirements. This problem is generally avoided by truncating bits at each stage, thus resulting in a loss of processing dynamics and system sensitivity. For radars employing low-gain wide-beam transmission, the target echo power is relatively weak. The loss of beamforming gain caused by computational processing reduces the integrity of target information and limits the ability to perform subsequent refined information processing. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a truncation and number system conversion method to reduce the computational loss of large dynamic FFT, which is achieved through the following technical solution:

[0005] Step 1: Select an appropriate rotation factor quantization bit depth N1 based on the full-frequency domain accuracy loss value specified in the indicator;

[0006] Step 2: Select an appropriate number of complex multiplication truncation bits N2 based on the full-frequency domain accuracy loss value specified in the index;

[0007] Step 3: After truncating the carry from the complex addition operation, obtain the fixed-point FFT operation result with a bit width of M;

[0008] Step 4: According to the I / O port transmission width N3 specified by the subsequent stage, if M>N3, then truncate the bit width added by the complex addition operation; otherwise, retain the bit width added by the complex addition operation.

[0009] Step 5: Based on the above operation bit width truncation rules, select an appropriate number of operation bits for operation. After completing all the predetermined FFT operations, obtain the FFT operation result with a bit width of N4.

[0010] Step 6: At this point, according to the specified I / O transmission bit width N3, the FFT operation result with a bit width of N4, which is represented by fixed-point numbers, is converted into the FFT operation result with a bit width of N3, which is represented by floating-point numbers, using floating-point numerical representation.

[0011] Compared with the prior art, the significant advantages of this invention are:

[0012] 1. By selecting an appropriate number of bits for operation based on the required computational precision, the dynamic range of the FFT operation results can be dynamically and effectively improved.

[0013] 2. By converting the fixed-point FFT operation result into a floating-point representation, the dynamic range can be improved while preserving the spectral accuracy of small signals and reducing the transmission bit width.

[0014] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the data processing flow of the present invention. Detailed Implementation

[0016] This invention proposes a truncation and number system conversion method to reduce computational losses in large dynamic range FFT. Through detailed research and analysis of the fixed-point FFT butterfly operation process, a fixed-point truncation scheme is developed. The optimal truncation bit depth can be selected according to actual needs, while also meeting the requirements of large dynamic range. Simultaneously, after completing the fixed-point FFT operation, a number system conversion is used to convert the fixed-point number to a floating-point representation. This reduces the bit width of the numerical representation and the bandwidth of subsequent transmission stages, while fully preserving the spectral information of small signals and effectively preserving the spectral information of large signals, thus better meeting the needs of various engineering applications. The invention will be further described below with reference to the accompanying drawings, but the scope of protection of this invention is not limited by the implementing regulations.

[0017] like Figure 1 As shown, a preferred embodiment of the present invention includes the following steps:

[0018] Step 1: Based on the full-frequency domain accuracy loss value specified in the indicator, generally set to -80dB to -60dB, select an appropriate rotation factor quantization bit depth N1. Here, N1 is the optimal result obtained through simulation. During simulation, a random single-bit small signal is used as the standard for the signal input.

[0019] Step 2: Based on the full-frequency domain accuracy loss value specified in the indicator, select an appropriate number of truncation bits N2. Here, N2 is the optimal result obtained through simulation. During simulation, the input signal is determined based on the actual input intermediate frequency I / Q signal bit width and the noise situation of the receiver front end. The selection of the number of truncation bits starts from the same as the input signal bit width and decreases bit by bit until the selected number of bits meets the specified full-frequency domain accuracy loss value.

[0020] Step 3: After truncating the carry from the complex addition operation, we obtain the fixed-point FFT operation result with a bit width of M. Here, the bit width M is a theoretical value derived by combining the truncation bits selected in Step 1 and Step 2.

[0021] Step 4: According to the I / O port transmission bit width N3 specified by the subsequent stage, if M>N3, the bit width added by the complex addition operation is truncated; otherwise, the bit width added by the complex addition operation is retained. Here, the I / O transmission bit width N3 represents the FFT operation result in floating-point numerical representation.

[0022] Step 5: Based on the above operation bit width truncation rules, select an appropriate number of operation bits for operation. After completing all the predetermined FFT operations, obtain the FFT operation result with a bit width of N4. The bit width N4 is a theoretical value derived from the complex addition operation carry processing method selected in Step 4.

[0023] Step 6: At this point, according to the specified I / O transmission bit width N3, the FFT operation result with a bit width of N4, represented using fixed-point numbers, is converted to an FFT operation result with a bit width of N3, represented using floating-point numbers. This includes a method for converting fixed-point numbers to floating-point numbers. If the actual bit width of the FFT operation result is less than the mantissa bits in N4, then during the conversion process, the entire actual bit width can be retained, and the exponent in the floating-point number is set to zero; if the actual bit width of the FFT operation result is greater than the mantissa bits in N4, then the number system conversion needs to be performed according to the following steps:

[0024] Step 6-1: Exponent extraction. This involves finding and recording the first position in the number where the sign bit is opposite to the exponent. This position is then marked with a flag bit (symbol). Thus, the exponent |E| can be obtained.

[0025] Step 6-2: Fixed-point shift, define the position format b of the input fixed-point number. n-1 ,b n-2 ,…,b0, where n=16. Based on this, assuming the exponent is |E|, if the mantissa is defined as 11 bits, if |E|<=11, then the significant bits of the fixed-point number are placed directly in the mantissa; if |E|>11, then the high 11 bits of the input fixed-point number are taken first, and then the extracted value is placed in the mantissa, which will result in a loss of some precision.

Claims

1. A truncation and number system conversion method to reduce computational loss in large dynamic FFT, characterized in that: Step 1: Select the quantization bit depth of the rotation factor as N1 according to the full-frequency domain accuracy loss value specified in the index; the full-frequency domain accuracy loss value in Step 1 is set to -80dB to -60dB according to the index specification. Step 2: Based on the full-frequency domain accuracy loss value specified in the index, select the number of truncation bits for complex multiplication as N2; Step 3: After truncating the carry from the complex addition operation, obtain the fixed-point FFT operation result with a bit width of M; Step 4: According to the I / O port transmission width N3 specified by the subsequent stage, if M>N3, then truncate the bit width added by the complex addition operation; otherwise, retain the bit width added by the complex addition operation. Step 5: Based on the above operation bit width truncation rules, select an appropriate number of operation bits for operation. After completing all the predetermined FFT operations, obtain the FFT operation result with a bit width of N4. Step 6: Based on the specified I / O transmission bit width N3, convert the FFT operation result with a bit width of N4, which is represented by fixed-point numbers, into the FFT operation result with a bit width of N3, which is represented by floating-point numbers, using floating-point numerical representation.

2. The truncation and number system conversion method for reducing the computational loss of large dynamic FFT as described in claim 1, characterized in that: In step 1, the quantization bit number N1 of the rotation factor is the optimal result obtained through simulation; during simulation, for the signal input, a random single-bit small signal is used as the standard.

3. The truncation and number system conversion method for reducing the computational loss of large dynamic FFT as described in claim 1, characterized in that: In step 2, the number of truncation bits N2 is obtained through simulation. During the simulation, the input signal is determined based on the actual input intermediate frequency I / Q signal width and the noise situation of the receiver front end. The selection value of the number of truncation bits starts from the same as the input signal width and decreases bit by bit until the selected number of bits meets the specified full-frequency domain accuracy loss value.

4. The truncation and number system conversion method for reducing the computational loss of large dynamic FFT as described in claim 1, characterized in that: In step 3, the bit width M is a theoretical value derived by combining the quantization bit width and truncation bit width selected in steps 1 and 2.

5. The truncation and number system conversion method for reducing the computational loss of large dynamic FFT as described in claim 1, characterized in that: The bit width N4 mentioned in step 5 is a theoretical value derived from the complex addition carry processing method selected in step 4.

6. The truncation and number system conversion method for reducing the computational loss of large dynamic FFT as described in claim 1, characterized in that: Step 6 further includes: if the actual bit width of the FFT result is less than the mantissa in N4, then during the conversion process, the entire actual bit width can be retained, and the exponent in the floating-point number can be set to zero; if the actual bit width of the FFT result is greater than the mantissa in N4, then the number system conversion needs to be performed according to the following steps: Step 6-1: Exponent Extraction: Find and record the first position in the number that is opposite to the sign bit; mark this position with the flag bit symbol to obtain the exponent |E|; Step 6-2: Fixed-point shift, define the position format b of the input fixed-point number. n-1 ,b n-2 b0, ..., b0, where n = 16; based on this, assuming the exponent is |E|, if the mantissa is defined as 11 bits, if |E| <= 11, then the significant bits of the fixed-point number are placed directly in the mantissa; if |E| > 11, then the high 11 bits of the input fixed-point number are taken first, and then the extracted value is placed in the mantissa, which will result in a loss of some precision.

Images