An automated FPGA prototype verification method

Abstract

The application discloses an automatic FPGA prototype verification method and relates to the field of chip FPGA prototype verification; the method comprises the following steps: S1, a verification platform is divided into an FPGA prototype test module and an auxiliary test module; S2, according to the module function of FPGA prototype verification, a test flow is divided into three types: an internal self-test flow, an external excitation and feedback test flow and a test flow related to reset; S3, according to the module function, a test instruction is issued to FPGA test code, and meanwhile, an auxiliary test chip judges corresponding output or test results fed back by the FPGA; the auxiliary test chip sequentially sends test instructions and records test results; S4, the auxiliary test module sequentially tests all function CASEs, and according to test results, error test items are preferentially tested during regression testing. The application provides a stable verification method, reduces the verification difficulty and the threshold of verification personnel, reduces the labor cost and improves the efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip FPGA prototype verification, and in particular to an automatic FPGA prototype verification method. BACKGROUND

[0002] FPGA is an integrated chip mainly based on digital circuits, and belongs to a programmable logic device, which is a kind of semi-custom circuit in the field of application specific integrated circuit, and solves the shortage of custom circuit and overcomes the defect of limited number of gate circuits of original programmable device.

[0003] With the further increase of the difficulty and challenge of integrated circuit design, in the chip development and verification stage, the iterative version of the design code is more and more, and each design version needs to be functionally verified, which will consume a lot of time and labor cost.

[0004] FPGA prototype verification is to simulate the actual software application conditions, whether the chip and system complete the actual scene application according to the design requirements, the FPGA internal circuit can be reconfigured, and the logic design of the chip can be mapped, from the cost, the cost performance of FPGA prototype verification is very high, and the FPGA prototype running speed is also very fast, compared with other verification methods, the FPGA prototype verification speed is several orders of magnitude higher, which is the current mainstream chip verification method.

[0005] At the beginning of chip design, many rounds of FPGA prototype verification are needed until the problem converges to zero, the repeated test will consume a lot of human resources, and because it is manual test, it will bring the risk of false verification, therefore, how to realize automatic verification is the key problem to be solved in the chip design and verification stage, and the present application provides an automatic FPGA prototype verification method to effectively solve the above problems. SUMMARY

[0006] The present application aims to provide an automatic FPGA prototype verification method, build an automatic FPGA prototype verification platform, write prototype test code and auxiliary test code according to the function, automatically execute the test instruction issued once, record the test result, judge whether the chip function is normal according to the running condition of the test code, save the result to FLASH, and compare the priority of different test cases according to the test result in the regression test stage, and maximize the test effect.

[0007] In order to solve the problems in the above background art, the present application provides the following technical scheme: an automatic FPGA prototype verification method, the verification method comprises the following steps:

[0008] S1, according to the FPGA prototype verification requirements, the verification platform is divided into two parts: FPGA prototype test module and auxiliary test module, wherein the auxiliary test module includes auxiliary test chip;

[0009] S2, according to the module function of FPGA prototype verification, the test flow is divided into three kinds: internal self-test flow, external excitation and feedback test flow and reset involved test flow;

[0010] S3, according to the module function of FPGA prototype verification, each function CASE test code is edited and merged to generate an executable program file, which is downloaded to the FPGA prototype verification module, each function test CASE is given to FPGA to execute corresponding test code by the way of auxiliary test chip issuing test instruction, at the same time, the auxiliary test chip will judge the corresponding output or the test result of FPGA feedback, the auxiliary test chip will send all the test instructions in turn, and record each test result;

[0011] S4, the auxiliary test module tests all function CASEs in turn, and according to all the test results, the erroneous test items are automatically tested preferentially in the regression test.

[0012] According to the above technical scheme, in step S1, according to the FPGA prototype verification automation requirement, the FPGA automation verification platform is built, the verification platform is divided into two parts: the FPGA prototype test module and the auxiliary test module; according to the function of each IP, the prototype test code and the auxiliary test code are written and downloaded into the FPGA prototype test module and the auxiliary test module at one time, the FPGA prototype test module needs to lead out all the digital pins equivalent to the netlist, and the internal digital signals of the analog module are led out, the analog module includes ADC, DAC, COMP and OPA analog IP modules; the I2C and SPI function modules belong to the prototype test module, the I2C and SPI function modules reserve the downloader interface, the reset button interface and the running indicator light in the FPGA prototype test module; some function modules increase the pull-up and pull-down resistors on the prototype test module to ensure the initial level state of the pin and the function implementation; after the digital part signals of the analog module are led out, the function circuit of the analog module is built outside through hardware to realize the full function of the analog module and test; the auxiliary test module tests all functions of the FPGA netlist, has the same number of pins as the prototype test module, and is connected with all the pins one by one; each pin of the auxiliary test module realizes the function corresponding to the corresponding prototype test module, the IO output is detected through the IO input, and the IO is an input and output interface; the PWM output is detected through the PWM capture, the PMW is a method for digitally encoding the analog signal level; the I2C is detected through the I2C interface, the I2C is a bidirectional two-wire synchronous serial bus; the SPI is detected through the SPI port, the SPI is a serial peripheral interface, which is a high-speed, full-duplex and synchronous communication bus; the UART is detected through the UART, the UART is a universal asynchronous receiver-transmitter which adopts asynchronous serial communication mode; the TIM is detected through the TIM, and the TIM is a capacitor key detection.

[0013] According to the above technical scheme, in step S2, the internal self-test flow executes the function configuration of the function module without output and input pins through the register, such as in the HDIV hardware divider module, which is represented as configuring the corresponding divisor, dividend, sign bit and enable bit configuration parameters through the register, and then reading out the calculated quotient and remainder through the register; the system is configured and the function is used, and then the corresponding result is read out through the corresponding register, whether the function is tested through is judged through the result, and the flow is as follows:

[0014] S2101, the auxiliary test module issues a test instruction;

[0015] S2102, the FPGA prototype verification module receives the instruction and executes the corresponding code, and jumps back to step S2101 if the execution result is correct; if the execution result is incorrect, jump to step S2103;

[0016] S2103, exit the test;

[0017] The external excitation and feedback test procedure is that a functional module needing external excitation or outputting external signals is excited or detects output by an auxiliary test chip, and whether the function is tested through is judged through output results or external excitation feedback. The test procedure is as follows:

[0018] S2201, the auxiliary test module issues a test instruction;

[0019] S2202, the FPGA prototype verification module receives the instruction and executes corresponding code;

[0020] S2203, the auxiliary test module gives excitation;

[0021] S2204, the FPGA prototype verification module gives feedback signals according to the excitation;

[0022] S2205, the auxiliary test module judges whether the feedback signals meet the conditions, and if the conditions are met, returns to step S2201;

[0023] S2206, exit the test;

[0024] The test procedure involving reset needs to save the current CASE number to the FLASH fixed area before the reset operation, and read the value of the FLASH address after the reset, and execute the corresponding code after the reset, so as to ensure that the test procedure continues to execute. The test procedure is as follows:

[0025] S2301, the auxiliary test module issues a test instruction;

[0026] S2302, the FPGA prototype verification module receives the instruction and executes corresponding code;

[0027] S2303, the FPGA prototype verification module saves the current test instruction number to FLASH and resets;

[0028] S2304, the FPGA prototype verification module reads the FLASH data after the reset and executes the CASE number corresponding to the current data;

[0029] S2305, the FPGA prototype verification module feeds back the test result, if correct, returns to step S2301; if incorrect, jumps to step S2306;

[0030] S2306, exit the test.

[0031] According to the above technical solution, in step S3, according to the module function of FPGA prototype verification, each function test CASE is given to FPGA to execute corresponding test code through the mode of auxiliary test chip issuing test instructions, and the auxiliary test module judges the corresponding output or FPGA feedback test result. The auxiliary test chip will send all the test instructions in turn, and record each test result. In order to facilitate the update and maintenance of automatic test CASE in the later period, the following rules are used to name the CASE number instruction: string "XX-YY-ZZ"; wherein XX is the module number to which the current CASE belongs, and each IP module corresponds to different numbers; YY is the function number of a certain group under the current module number; for example, the baud rate of serial port is a group function, and the baud rate parameter test supported by the current serial port is placed under this group function test number; ZZ is the CASE serial number under this group function; when adding CASE in the later period, it can be added under the corresponding multi-level serial number, without affecting other module serial numbers; similarly, the CASE number naming rule only needs to follow the arrangement order of module number, group function number and corresponding group function number under CASE serial number, and does not limit the string size of corresponding CASE instruction. In the FPGA verification process, a large number of CASEs usually need to be verified. According to the number of CASEs in the plan, set a reasonable string size; the instruction and feedback result string are transmitted through any two IO ports, using a self-defined protocol. One IO port is used as clock SWC, and one IO port is used as data SWD. When transmitting data, first pull down the SWD by one clock as the starting bit, then transmit 16-bit integer data from high bit to low bit, and finally pull down the clock SWD as the end bit to control the transmission state. When SWD is pulled down, the transmission state is idle. The above instruction string is converted into corresponding ASIC code for transmission. The auxiliary test module sends test instructions to the FPGA prototype verification module from CASE number "00-00-00" in the first test. Each instruction waits for feedback results. If the feedback result is passed, the next CASE number is executed. If the feedback result is not passed, the current CASE number is recorded, and the error result is recorded; when writing the test CASE, the execution of each step is recorded, and the execution result of all steps of the current CASE is recorded. If all steps are correct, the feedback verification is passed, otherwise, the result of each step is fed back to the auxiliary test module, which is convenient for error checking.

[0032] According to the above technical scheme, in step S4, according to the test result of the auxiliary test module, the erroneous test item is automatically tested preferentially in the regression test, firstly, all CASE test priorities are divided into three levels: priority 1, priority 2 and priority 3, in the initial state, all CASE priorities are priority 2 by default, if the i-th CASE continuously passes three rounds of regression tests, the priority of the i-th CASE is reduced to 3, if the j-th CASE continuously passes part of three rounds of regression tests, the priority of the j-th CASE remains unchanged, if the k-th CASE continuously fails three rounds of regression tests, the priority of the k-th CASE is adjusted to 1, and each round of test is tested in order from 1 to 3 according to the priority. Improve the error detection efficiency; after multiple rounds of regression tests, the probability of some CASEs having problems is getting lower and lower or never having problems, the auxiliary test module will adjust the test priority of the CASEs to be low; the probability of some CASEs having problems is very high, the auxiliary test module will adjust the test priority of the CASEs to be high, and the test efficiency is improved.

[0033] Compared with the prior art, the beneficial effects achieved by the present application are:

[0034] 1、The present application uses an automatic verification method, builds an automatic verification platform, unifies the prototype verification module code and the auxiliary test module code, ensures the repeatability of the steps in multiple rounds of FPGA prototype verification, accurately records the experimental results, facilitates error problem checking, preferentially tests the erroneous test item, optimizes the test process, and improves the verification accuracy.

[0035] 2、The present application uses automatic code for a large number of repeated tests, uses FPGA instead of manual verification, saves human resources, reduces human cost, improves verification efficiency, and conforms to the mainstream direction of future FPGA prototype verification.

[0036] 3、The present application uses an automatic method, simplifies the verification steps, thereby reducing the verification difficulty and lowering the access threshold of the verification personnel. DETAILED DESCRIPTION

[0037] The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the specification, together with the embodiments of the present application, to explain the present application, and do not constitute a limitation of the present application. In the drawings:

[0038] Figure 1 FIG. 1 is a FPGA automatic verification platform diagram of the automatic FPGA prototype verification method of the present application;

[0039] Figure 2An internal self-test flow chart of the automatic FPGA prototype verification method of the application;

[0040] Figure 3 An external excitation and feedback test flow chart of the automatic FPGA prototype verification method of the application;

[0041] Figure 4 A test flow chart related to reset of the automatic FPGA prototype verification method of the application;

[0042] Figure 5 A self-defined protocol transmission chart of the automatic FPGA prototype verification method of the application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0044] The application provides the following technical solution: an automatic FPGA prototype verification method, which comprises the following steps:

[0045] S1, according to FPGA prototype verification requirements, the verification platform is divided into two parts: an FPGA prototype test module and an auxiliary test module, and the verification platform is as shown in Figure 1As shown; in step S1, according to the FPGA prototype verification automation requirements, the verification platform is divided into two parts: the FPGA prototype test module and the auxiliary test module, the auxiliary test module includes an auxiliary test chip; the FPGA prototype test module needs to lead out all the digital pins equivalent to the netlist, the analog module includes ADC, DAC, COMP and OPA analog IP modules; At the same time, the internal digital signal of the analog module is led out; The FPGA prototype test module reserves the downloader interface, the reset button interface and the running indicator; The prototype test module includes I2C and SPI function modules, the I2C and SPI function modules increase the pull-up and pull-down resistors on the prototype test module to ensure the initial level state of the pin and the function implementation; After the digital part signal of the analog module is led out, the function circuit of the analog module simulation part is built externally by hardware to realize the full function of the analog module and test; The auxiliary test module has the same number of pins as the prototype test module and is connected one by one with all the pins; Each pin of the auxiliary test module can realize the function corresponding to the corresponding prototype test module, the IO output is detected by the IO input, the PWM output is detected by the PWM capture, the I2C is detected by the I2C interface, the SPI is detected by the SPI port, the UART is detected by the UART, and the TIM is detected by the TIM.

[0046] S2, according to the module function of the FPGA prototype verification, the test flow is divided into three kinds: internal self-test flow, external excitation and feedback test flow and reset-related test flow; In step S2, the internal self-test flow will not have output and input pin function modules through register execution function configuration, such as in the HDIV hardware divider module, it is manifested as configuring the corresponding divisor, dividend, sign bit and enable bit parameters through the register, and then reading out the calculated quotient and remainder through the register; The corresponding result is read out through the corresponding register, and the result is used to judge whether the function is tested through, and the flow is as shown in Figure 2

[0047] S2101, the auxiliary test module issues a test instruction;

[0048] S2102, the FPGA prototype verification module receives the instruction and executes the corresponding code, and the execution result is correct to jump back to step S2101; The execution result is incorrect to jump to step S2103;

[0049] S2103, exit the test;

[0050] The external excitation and feedback test flow is to excite or detect the output of the function module which needs external excitation or output external signal through the auxiliary test chip, and judge whether the function is tested through by the output result or external excitation feedback, as shown in Figure 3 The test flow is as follows:

[0051] ​S2201, the auxiliary test module issues a test instruction;

[0052] S2202, the FPGA prototype verification module receives the instruction and executes the corresponding code;

[0053] S2203, the auxiliary test module gives an excitation;

[0054] S2204, the FPGA prototype verification module gives a feedback signal according to the excitation;

[0055] S2205, the auxiliary test module judges whether the feedback signal meets the condition, and if the condition is met, jumps back to step S2201;

[0056] S2206, exit the test;

[0057] The test flow related to the reset needs to save the current CASE number to the FLASH fixed area before the reset operation, and read the value of the FLASH address after the reset, and execute the corresponding code after the reset, so as to ensure the test flow to continue to execute, as shown in Figure 4 The test flow is as follows:

[0058] S2301, the auxiliary test module issues a test instruction;

[0059] S2302, the FPGA prototype verification module receives the instruction and executes the corresponding code;

[0060] S2303, the FPGA prototype verification module saves the current test instruction number to the FLASH and resets;

[0061] S2304, the FPGA prototype verification module reads the FLASH data after the reset, and executes the CASE number corresponding to the current data;

[0062] S2305, the FPGA prototype verification module feeds back the test result, if correct, jumps back to step S2301; if incorrect, jumps to step S2306;

[0063] S2306, exit the test.

[0064] S3, according to the module function of FPGA prototype verification, the CASE test code of each function is edited and merged to generate an executable program file, which is downloaded to the FPGA prototype verification module, each item of function test CASE is given to FPGA to execute corresponding test code in the form of test instruction issued by the auxiliary test chip, and the auxiliary test chip judges the corresponding output or the test result fed back by FPGA, the auxiliary test chip sends all test instructions in turn, and records each test result; in step S3, according to the module function of FPGA prototype verification, each item of function test CASE is given to FPGA to execute corresponding test code in the form of test instruction issued by the auxiliary test chip, and the auxiliary test module judges the corresponding output or the test result fed back by FPGA, the auxiliary test chip sends all test instructions in turn, and records each test result; in order to facilitate the update and maintenance of automatic test CASE in the later period, the following rules are used to name the CASE number instruction: string "XX-YY-ZZ"; wherein XX is the module number to which the current CASE belongs, each IP module corresponds to a different number; YY is the number of a group function under the current module number; ZZ is the CASE serial number under the group function; when adding CASE in the later period, it can be added under the corresponding multi-level serial number, without affecting other module serial numbers; similarly, the CASE number naming rule only needs to follow the arrangement order of module number, group function number and CASE serial number under the corresponding group function number, and does not limit the size of the corresponding CASE instruction string, in the FPGA verification process, a large number of CASEs usually need to be verified, according to the number of CASEs in the plan, a reasonable string size is set; the instruction and feedback result string are transmitted through any two IO ports, using a self-defined protocol, one IO port as clock SWC and one IO port as data SWD, when transmitting data, first pull down the SWD clock as the starting bit, then transmit 16-bit integer data from high bit to low bit, and finally pull down the clock SWD as the end bit, the SWD clock controls the transmission state, and the SWD is pulled down when the transmission state is idle, as shown in Figure 5 the above instruction string is converted into corresponding ASIC code for transmission, the auxiliary test module sends test instructions to the FPGA prototype verification module from CASE number "00-00-00" in the first test. Each instruction waits for feedback result, if the feedback result is passed, the next CASE number is executed, and if the feedback result is not passed, the current CASE number is recorded; when the test CASE is written, the execution of each step is recorded, and the execution result of all steps of the current CASE is recorded, if the execution result of all steps of the current CASE is correct, the feedback verification is passed, otherwise, the result of each step is fed back to the auxiliary test module, which is convenient for error checking.

[0065] S4, the auxiliary test module tests all functions CASE in turn, and according to all test results, automatically tests the erroneous test items first in the regression test. In step S4, according to the test results of the auxiliary test module, the erroneous test items are automatically tested first in the regression test, and first, the priority of all CASE tests is divided into three levels: priority 1, priority 2 and priority 3, and in the initial state, the priority of all CASEs is priority 2 by default, and if after three rounds of regression tests, the ith CASE passes the three rounds of regression tests, the priority of the ith CASE is reduced to 3, if after three rounds of regression tests, the jth CASE passes the three rounds of regression tests, the priority of the jth CASE remains unchanged, and if after three rounds of regression tests, the kth CASE fails the three rounds of regression tests, the priority of the kth CASE is adjusted to 1, and each round of test is tested in the order of priority from 1 to 3. After several rounds of regression tests, the probability of some CASEs appearing problems is lower and lower or never appears problems, and the auxiliary test module will lower the test priority of such CASEs; the probability of some CASEs appearing problems is very high, and the auxiliary test module will increase the test priority of such CASEs, and test them first to improve the error detection efficiency.

[0066] Embodiment one:

[0067] In step S1, the auxiliary test module issues a test instruction, the FPGA prototype verification module receives the instruction, executes the code, and the CASE "23-32-12" performs an internal self-test process, the execution result is correct, the auxiliary test module saves the CASE number and the execution result, and lowers the priority of the CASE "23-32-12" in the regression test; the next test instruction is issued, the FPGA prototype verification module receives the instruction, the CASE "42-23-51" performs an external excitation and feedback test process, the test module gives an excitation, the FPGA prototype verification module gives a feedback signal according to the excitation, the auxiliary test module judges that the feedback signal meets the condition, saves the CASE number and the test result, and lowers the priority of the CASE "42-23-51" in the regression test; the auxiliary test module issues the next test instruction, the FPGA prototype verification module receives the instruction, the CASE "01-23-98" performs a test involving reset, the FPGA prototype verification module saves the instruction number to FLASH and resets, the reset reads the FLASH data, executes the corresponding CASE number, and the feedback test result is incorrect, which is recorded and the priority of the CASE "01-23-98" in the regression test is increased.

[0068] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that the technical solutions described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalent ones. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An automated FPGA prototype verification method, characterized in that... It includes four steps: S1. Based on the FPGA prototype verification requirements, the verification platform is divided into two parts: the FPGA prototype test module and the auxiliary test module, wherein the auxiliary test module includes the auxiliary test chip. S2. Based on the module functions of the FPGA prototype verification, the test process is divided into three types: internal self-test process, external stimulus and feedback test process, and test process involving reset. S3. Based on the module functions of the FPGA prototype verification, edit the test code for each function CASE, merge them to generate an executable program file, and download it to the FPGA prototype verification module. Each function CASE is given to the FPGA to execute the corresponding test code by issuing test instructions through the auxiliary test chip. At the same time, the auxiliary test chip judges the corresponding output or the test result fed back by the FPGA. The auxiliary test chip sends all test instructions in sequence and records each test result. S4, the auxiliary testing module tests all functional cases in sequence, and automatically prioritizes testing erroneous test items during regression testing based on all test results; In step S1, based on the automation requirements of FPGA prototype verification, the verification platform is divided into two parts: an FPGA prototype test module and an auxiliary test module. The FPGA prototype test module brings out all the digital pins equivalent to the netlist, and also brings out the internal digital signals of the analog module. A downloader interface, a reset button interface, and a run indicator light are reserved in the FPGA prototype test module. The I2C and SPI functional modules belong to the prototype test module, and pull-up and pull-down resistors are added to the I2C and SPI functional modules on the prototype test module. After the digital signals of the analog module are brought out, the functional circuit of the analog part of the analog module is built externally through hardware to realize the full function of the analog module and test it. The auxiliary test module has the same number of pins as the prototype test module. The system has pins for measuring quantity and connects them one by one; each pin of the auxiliary test module performs a function corresponding to the corresponding prototype test module; IO output is detected through IO input, IO is an input / output interface; PWM output is detected through PWM capture, PWM is a method of digitally encoding analog signal levels; I2C is detected through the I2C interface, I2C is a bidirectional two-wire synchronous serial bus; SPI is detected through the SPI port, SPI is a serial peripheral interface, a high-speed, full-duplex, synchronous communication bus; UART is detected through UART, UART is a universal asynchronous transceiver that uses asynchronous serial communication; TIM is detected through TIM, TIM is a capacitive key detection. In step S2, the internal self-test process configures functional modules without output or input pins through registers, then reads the corresponding results from the registers to determine whether the function has passed the test. The process is as follows: S2101, The auxiliary testing module issues test commands; S2102: The FPGA prototype verification module receives the instruction and executes the corresponding code. If the execution result is correct, it jumps back to step S2101; if the execution result is incorrect, it jumps to step S2103. S2103, Exit test; The external stimulus and feedback test process involves providing external stimulus or output signals to functional modules that require external input through an auxiliary test chip. The test result or external stimulus feedback is then used to determine whether the function has passed the test. The test process is as follows: S2201, The auxiliary test module issues test commands; S2202, the FPGA prototype verification module receives the instruction and executes the corresponding code; S2203, The auxiliary test module provides the stimulus; S2204, the FPGA prototype verification module provides feedback signals based on the stimulus; S2205. The auxiliary test module determines whether the feedback signal meets the conditions. If the conditions are met, it jumps back to step S2201. S2206, Exit test; For test procedures involving reset, the current CASE number needs to be saved to a fixed area of ​​FLASH before the reset operation, and the value of that FLASH address needs to be read after the reset to execute the corresponding reset code, thereby ensuring that the test procedure continues to execute. The test procedure is as follows: S2301, The auxiliary testing module issues test commands; S2302, the FPGA prototype verification module receives the instruction and executes the corresponding code; S2303, the FPGA prototype verification module saves the current test instruction number to FLASH and resets it; S2304, the FPGA prototype verification module resets and reads the FLASH data, and executes the CASE number corresponding to the current data; S2305. The FPGA prototype verification module provides the test results. If correct, jump back to step S2301; if incorrect, jump to step S2306. S2306, Exit test; In step S3, based on the module functions of the FPGA prototype verification, each functional test case is given to the FPGA to execute the corresponding test code by issuing test instructions through the auxiliary test chip. Simultaneously, the auxiliary test module judges the corresponding output or the test results fed back by the FPGA. The auxiliary test chip sends all test instructions sequentially and records each test result. The case number instruction is named using the following rule: string "XX-YY-ZZ"; where XX is the module number to which the current case belongs, with each IP module corresponding to a different number; YY is the function number of the group under the current module number; and ZZ is the case number under this function group. The instruction and feedback result strings are separated by any two I... The IO port uses a custom protocol for transmission. One IO port is used as the clock SWC, and the other is used as the data SWD. When transmitting data, SWD is first pulled low by one clock cycle as the start bit. Then, 16-bit integer data is transmitted sequentially from the high bit to the low bit. Finally, SWD is pulled low by one clock cycle as the end bit. The above instruction string is converted into the corresponding ASIC code for transmission. During the first test, the auxiliary test module sends test instructions sequentially from CASE number "00-00-00" to the FPGA prototype verification module. Each instruction waits for feedback. If the feedback result is successful, the next CASE number is executed. If the feedback result is unsuccessful, the current CASE number is recorded, and the error result is also recorded. During test case writing, the execution status of each step is recorded. If all steps of the test case are correct, the verification is passed; otherwise, the results of each step are fed back to the auxiliary testing module. In step S4, based on the test results of the auxiliary testing module, the erroneous test items are automatically prioritized for testing during regression testing. First, all test case priorities are divided into three levels: priority 1, priority 2, and priority 3. Initially, all test cases are assigned priority 2 by default. If, after three consecutive rounds of regression testing, the i-th test case passes all three rounds, its priority is reduced to 3. If, after three consecutive rounds of regression testing, the j-th test case partially passes all three rounds, its priority remains unchanged. If the k-th test case fails all three rounds, its priority is adjusted to 1. Each round of testing proceeds sequentially from priority 1 to 3.

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