Display panel and display device

Abstract

This invention provides a display panel and a display device. The display panel includes a data line and a pixel circuit under test. The pixel circuit under test is coupled to the data line and is used to receive a first detection signal from a self-detection signal source and a second detection signal from a pixel data signal source. The pixel circuit under test generates a drive current to read the first and second detection signals, thereby generating a detection result signal. The pixel circuit under test includes a light-emitting element and a bypass circuit. The light-emitting element emits light according to the drive current. The bypass circuit is coupled to the light-emitting element and the data line and is used to transmit the detection result signal to the detection signal source via the data line according to a test control signal, so that the detection signal source can determine whether the pixel circuit under test is abnormal.

Description

Technical Field

[0001] This application relates to an electronic testing device. More specifically, this application relates to a display panel and a display device. Background Technology

[0002] In existing display devices, the pixel circuit testing design of the display panel is coupled to a low system voltage. However, since all pixel circuits in a column are coupled to the low system voltage signal line, if any pixel circuit in a column malfunctions, the test results for all pixel circuits in that column will also be abnormal. Therefore, it is impossible to determine the specific abnormal pixel circuit in a column.

[0003] Therefore, the above-mentioned technologies still have many shortcomings, and it is up to practitioners in the field to develop other suitable display panels and display devices. Summary of the Invention

[0004] One aspect of this application relates to a display panel. The display panel includes a data line and a pixel circuit under test. The pixel circuit under test is coupled to the data line and is used to receive a first detection signal from a self-detection signal source and a second detection signal from a pixel data signal source. The pixel circuit under test is also used to generate a drive current to read the first and second detection signals, thereby generating a detection result signal. The pixel circuit under test includes a light-emitting element and a bypass circuit. The light-emitting element emits light according to the drive current. The bypass circuit is coupled to the light-emitting element and the data line and is used to transmit the detection result signal to the detection signal source via the data line according to a test control signal, so that the detection signal source can determine whether the pixel circuit under test is abnormal.

[0005] Another aspect of this application relates to a display device. The display device includes a display panel and a detection signal source. The display panel includes a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits under test (DUTs). The plurality of DUTs are respectively coupled to the plurality of data lines and the plurality of gate lines. The detection signal source is coupled to each of the plurality of DUTs and the plurality of data lines of the display panel, and is used to generate a first detection signal to each of the plurality of DUTs, thereby causing each of the plurality of DUTs to generate a detection result signal to the plurality of data lines based on the first detection signal and a second detection signal. The detection signal source determines whether each of the plurality of DUTs is abnormal based on the detection result signal. If each of the plurality of DUTs is abnormal, the detection signal source is used to lock the abnormal plurality of DUTs based on a plurality of positioning points of the plurality of data lines and the plurality of gate lines. Attached Figure Description

[0006] The content of this application can be better understood by referring to the embodiments in the following paragraphs and the accompanying drawings:

[0007] Figure 1This is a circuit block diagram of a display device illustrated according to some embodiments of this application;

[0008] Figure 2 This is a circuit block diagram illustrating the test pixel circuit of a display panel according to some embodiments of this application;

[0009] Figure 3 This is a schematic diagram of the driving signal timing of the pixel circuit under test of a display panel, illustrated according to some embodiments of this application;

[0010] Figure 4 This is a schematic diagram of the circuit state of the pixel circuit under test of a display panel, illustrated according to some embodiments of this application.

[0011] Figure 5 A schematic diagram of the circuit state of the pixel circuit under test of a display panel, illustrated according to some embodiments of this application; and

[0012] Figure 6 This is a schematic diagram of the circuit state of the pixel circuit under test of a display panel according to some embodiments of this application.

[0013] [Symbol Explanation]

[0014] 100: Display device

[0015] 110: Display panel

[0016] 120: Detect signal source

[0017] DL1~DL[N]: Data cable

[0018] G1~G[N]: Gate lines

[0019] P1~P[N], P[N+1]~P[2N], P[M]: Pixel circuit under test

[0020] X, Y: Coordinate axis directions

[0021] L: Light-emitting element

[0022] BP: Bypass circuit

[0023] T13: Detection transistor

[0024] PWM: Pulse Width Modulation Circuit

[0025] PAM: Pulse Amplitude Modulation Circuit

[0026] RESET: Reset circuit

[0027] EPWM(n): First control signal source

[0028] EPAM(n): Second control signal source

[0029] VST(n): Initial signal source

[0030] SP(n): Write signal source

[0031] TEST(n): Test control signal source

[0032] T1~T12, T14~T19: Transistors

[0033] C1~C3: Capacitors

[0034] SET(n): Reset the signal source

[0035] Vset: Reset voltage

[0036] Sweep(n): Sweep signal source

[0037] Sweep_VGH: High potential

[0038] VDD_PWM, VDD_PAM: System high voltage source

[0039] VSS: System Low Voltage Source

[0040] VPAM_R / G / B: Pixel data signal source

[0041] Vsig(m)_R / G / B: First detection signal

[0042] I1~I2: Stages

[0043] I11~I12, I21: Sub-stages

[0044] R1~R2: Current path Detailed Implementation

[0045] The spirit of this application will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of this application, those skilled in the art can make changes and modifications based on the technology taught in this application without departing from the spirit and scope of this application.

[0046] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application. Singular forms such as “a,” “this,” “this,” “the,” and “the”, as used herein, also include plural forms.

[0047] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0048] Unless otherwise specified, the terms used herein generally have their ordinary meaning in the context of the art, the application, and the specific content thereof. Some terms used to describe this application will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing this application.

[0049] Figure 1 This is a circuit block diagram illustrating a display device 100 according to some embodiments of this application. In some embodiments, such as Figure 1 As shown, the display device 100 includes a display panel 110 and a detection signal source 120.

[0050] In some embodiments, the display panel 110 includes a plurality of data lines (e.g., data lines DL1 to DL[N]), a plurality of gate lines (e.g., gate lines G1 to G[N]), and a plurality of pixel circuits under test (e.g., pixel circuits under test P1 to pixel circuits under test P[N], pixel circuits under test P[N+1] to pixel circuits under test P[2N], and pixel circuits under test P[M]).

[0051] Next, multiple pixel circuits under test (e.g., pixel circuits under test P1 to pixel circuits under test P[N], pixel circuits under test P[N+1] to pixel circuits under test P[2N] and pixel circuits under test P[M]) are respectively coupled to multiple data lines (e.g., data lines DL1 to DL[N]) and multiple gate lines (e.g., gate lines G1 to G[N]). The detection signal source 120 is coupled to each of the plurality of pixel circuits under test (e.g., pixel circuits under test P1 to P[N], pixel circuits under test P[N+1] to P[2N], and pixel circuits under test P[M]) and the plurality of data lines (e.g., data lines DL1 to DL[N]) of the display panel 110, and is used to generate detection signals to each of the plurality of pixel circuits under test (e.g., pixel circuits under test P1 to P[N], pixel circuits under test P[N+1] to P[2N], and pixel circuits under test P[M]) and the plurality of data lines (e.g., data lines DL1 to DL[N]), so that each of the plurality of pixel circuits under test generates a detection result signal to the plurality of data lines (e.g., data lines DL1 to DL[N]) according to the first detection signal and the second detection signal.

[0052] Furthermore, the detection signal source 120 determines whether each of the multiple pixel circuits under test is abnormal based on the detection result signal. If each of the multiple pixel circuits under test is abnormal, the detection signal source 120 uses multiple positioning points of multiple data lines and multiple gate lines (e.g., the positions of pixel circuits under test P1 to P[N], the positions of pixel circuits under test P[N+1] to P[2N], and the position of pixel circuits under test P[M]) to lock the abnormal pixel circuits under test.

[0053] In some embodiments, please refer to Figure 1 Multiple data lines (e.g., data lines DL1 to DL[N]) are arranged along a first direction (e.g., the Y-axis). Multiple gate lines (e.g., gate lines G1 to G[N]) are arranged along a second direction (e.g., the X-axis). The multiple data lines (e.g., data lines DL1 to DL[N]) and the multiple gate lines (e.g., gate lines G1 to G[N]) are not parallel. The multiple data lines (e.g., data lines DL1 to DL[N]) and the multiple gate lines (e.g., gate lines G1 to G[N]) intersect to form multiple positioning points. It should be noted that the multiple data lines (e.g., data lines DL1 to DL[N]) are used to position multiple pixel circuits under test in the X-axis direction. The multiple gate lines (e.g., gate lines G1 to G[N]) are used to position multiple pixel circuits under test in the Y-axis direction.

[0054] Next, multiple pixel circuits to be tested (e.g., pixel circuits P1 to P[N], P[N+1] to P[2N], and P[M]) are located at multiple positioning points.

[0055] Figure 2 To illustrate corresponding embodiments of this application Figure 1 A circuit block diagram of the pixel circuit P1 under test in the display panel 110 of the display device 100. In some embodiments, please refer to... Figure 1 and Figure 2 The circuit structures of the pixel circuits under test P2 to P[N], P[N+1] to P[2N], and P[M] are all the same as those of the pixel circuit under test P1. Subsequent explanations will use the circuit structure of the pixel circuit under test P1 as an example.

[0056] In some embodiments, to facilitate understanding of the structure of all pixel circuits under test in this application, please refer to the following: Figure 1 and Figure 2 In some embodiments, see Figure 1 The display panel 110 includes a data line DL1 and a pixel circuit P1 to be tested.

[0057] Next, please refer to Figure 1 and Figure 2 The pixel circuit P1 under test is coupled to the data line DL1 and is used to receive the first detection signal Vsig(m)_R / G / B (illustrated from the self-detection signal source 120) Figure 2 The circuit receives the signal at the top left corner, and the pixel circuit P1 under test is used to generate a drive current to read the first detection signal Vsig(m)_R / G / B (shown from...). Figure 2 The output is located at the lower right corner of the circuit. The pixel circuit P1 under test is used to receive the second detection signal from the pixel data signal source VPAM_R / G / B. The pixel circuit P1 under test generates a detection result signal based on the first detection signal Vsig(m)_R / G / B and the second detection signal.

[0058] Furthermore, please refer to Figure 1 and Figure 2 The pixel circuit under test, P1, includes a light-emitting element L and a bypass circuit BP. The light-emitting element L emits light according to the driving current. The bypass circuit BP is coupled to the light-emitting element L and the data line DL1, and is used to transmit the detection result signal to the detection signal source 120 via the data line DL1 according to the test control signal, so that the detection signal source 120 can determine whether the pixel circuit under test, P1, is abnormal. It should be noted that the bypass circuit BP bypasses the detection result signal to the data line DL1; in this case, the light-emitting element L does not emit light.

[0059] In some embodiments, the bypass circuit BP includes a detection transistor T13. The detection transistor T13 is coupled to the light-emitting element L and the data line DL1, and is used to transmit the detection result signal to the data line DL1 according to the test control signal.

[0060] In some embodiments, the pixel circuit P1 under test further includes a pulse width modulation circuit (PWM), a pulse amplitude modulation circuit (PAM), and a reset circuit (RESET).

[0061] In some embodiments, the pulse width modulation (PWM) circuit is coupled to... Figure 1 The detection signal source 120 and the first control signal source EPWM(n) are used to drive according to the first control signal of the first control signal source EPWM(n).

[0062] In some embodiments, the pulse amplitude modulation circuit PAM is coupled to the light-emitting element L, the detection transistor T13, the pulse width modulation circuit PWM, the pixel data signal source VPAM_R / G / B and the second control signal source EPAM(n), and is used to drive according to the second control signal of the second control signal source EPAM(n).

[0063] In some embodiments, both the pulse width modulation (PWM) circuit and the pulse amplitude modulation (PAM) circuit are coupled to the initial signal source VST(n). Both the PWM circuit and the PAM circuit are coupled to the write signal source SP(n).

[0064] In some embodiments, taking the top and right sides of the components in the figure as the first terminals, the detection transistor T13 includes a first terminal, a second terminal, and a control terminal. The first terminal of the detection transistor T13 is coupled to the pulse amplitude modulation circuit PAM. The second terminal of the detection transistor T13 is coupled to the data line DL1. The control terminal of the detection transistor T13 is coupled to the test control signal source TEST(n) and is used to receive the test control signal from the test control signal source TEST(n), thereby responding to the test control signal being turned on to output the detection result signal to the data line DL1.

[0065] In some embodiments, the pulse width modulation (PWM) circuit includes a first capacitor C1, transistors T1 to T6, transistor T12, and transistors T16 to T19. The first capacitor C1 is indirectly coupled to the detection signal source 120. The first capacitor C1 is used to store the first detection signal Vsig(m)_R / G / B.

[0066] In some embodiments, the pulse amplitude modulation circuit (PAM) includes a second capacitor C2, transistors T7 to T11, and transistor T15. The second capacitor C2 is coupled to the pixel data signal source VPAM_R / G / B. The second capacitor C2 is used to store the second detection signal input from the pixel data signal source VPAM_R / G / B.

[0067] In some embodiments, the RESET circuit includes a capacitor C3 and a transistor T14.

[0068] In some embodiments, to enable Figure 2 The operation of the pixel circuit P1 under test is easy to understand; please refer to [the documentation / reference]. Figure 3 , Figure 3 Illustrations based on some embodiments of this application Figure 1 The timing diagram of the driving signal of the pixel circuit P1 under test of the display panel 110 is shown. The pulse width modulation circuit PWM and the pulse amplitude modulation circuit PAM are reset in the first sub-stage I11 of the first stage I1 according to the initial signal of the initial signal source VST(n).

[0069] Next, in the second sub-stage I12 of the first stage I1, the pulse width modulation circuit (PWM) stores the first detection signal Vsig(m)_R / G / B to the first capacitor C1 of the PWM circuit based on the write signal from the write signal source SP(n). In the second sub-stage I12 of the first stage I1, the pulse amplitude modulation circuit (PAM) stores the second detection signal of the pixel data signal source VPAM_R / G / B to the second capacitor C2 of the PAM circuit based on the write signal from the write signal source SP(n).

[0070] Furthermore, in the second stage I2, the pulse width modulation (PWM) circuit is turned on according to the first control signal to read the first detection signal Vsig(m)_R / G / B from the first capacitor C1 of the PWM circuit, and then outputs it to the pulse amplitude modulation (PAM) circuit. In the second stage I2, the pulse amplitude modulation (PAM) circuit is turned on according to the second control signal to read the second detection signal from the second capacitor C2 of the PAM circuit, and then outputs the first detection signal Vsig(m)_R / G / B and the second detection signal to the data line DL1 through the detection transistor T13. It should be noted that the first stage I1 is... Figure 1 The programming stage of the display device 100. The second stage I2 is... Figure 1 The testing phase of the display device 100.

[0071] Figure 4 Corresponding figures illustrated according to some embodiments of this application Figure 1 A schematic diagram of the circuit state of the pixel-to-be-tested circuit P1 of the display panel 110 of the display device 100. In some embodiments, please refer to... Figure 3 and Figure 4 In the first sub-stage I11 of the first stage I1, the initial signal of the initial signal source VST(n) and the reset signal of the reset signal source SET(n) are at low level, while the write signal of the write signal source SP(n) is at high level. The pulse width modulation circuit PWM and the pulse amplitude modulation circuit PAM are reset according to the initial signal of the initial signal source VST(n) in the first sub-stage I11 of the first stage I1.

[0072] In some embodiments, the initial signal of the initial signal source VST(n) in the first sub-stage I11 of the first stage I1 resets the pulse width modulation circuit PWM through transistors T12 and T18. The initial signal of the initial signal source VST(n) in the first sub-stage I11 of the first stage I1 resets the pulse amplitude modulation circuit PAM through transistor T18 and transistor T11 of the pulse amplitude modulation circuit PAM.

[0073] In some embodiments, the reset signal of the reset signal source SET(n) stores the reset voltage Vset to the capacitor C3 of the reset circuit RESET through the transistor T14 of the reset circuit RESET in the first sub-stage I11 of the first stage I1.

[0074] Figure 5 Corresponding figures illustrated according to some embodiments of this application Figure 1 A schematic diagram of the circuit state of the pixel-to-be-tested circuit P1 of the display panel 110 of the display device 100. In some embodiments, please refer to... Figure 3 and Figure 5 In the second sub-stage I12 of the first stage I1, the write signal of the write signal source SP(n) and the sweep signal of the sweep signal source Sweep(n) are both at a low level, while the initial signal of the initial signal source VST(n) is at a high level. The pulse width modulation circuit (PWM) stores the first detection signal Vsig(m)_R / G / B based on the write signal of the write signal source SP(n) in the second sub-stage I12 of the first stage I1. The pulse amplitude modulation circuit (PAM) stores the second detection signal of the pixel data signal source VPAM_R / G / B based on the write signal of the write signal source SP(n) in the second sub-stage I12 of the first stage I1.

[0075] In some embodiments, please refer to Figure 3 and Figure 5 The write signal from the signal source SP(n) is written to the first detection signal Vsig(m)_R / G / B through transistors T2-T4 of the pulse width modulation circuit (PWM) in the second sub-stage I1 of the first stage I1, and stored in the first capacitor C1 of the PWM circuit. The write signal from the signal source SP(n) is written to the second detection signal through transistors T7-T9 of the pulse amplitude modulation circuit (PAM) in the second sub-stage I1 of the first stage I1, and stored in the second capacitor C2 of the PAM circuit.

[0076] In some embodiments, please refer to Figure 3 , Figure 4 and Figure 5 Since the capacitor C3 of the reset circuit RESET has stored the reset voltage Vset in the first sub-stage I11 of the first stage I1, in the second sub-stage I12 of the first stage I1, the transistor T10 of the pulse amplitude modulation circuit PAM turns on in response to the reset voltage Vset of the capacitor C3 of the reset circuit RESET.

[0077] Figure 6 Corresponding figures illustrated according to some embodiments of this application Figure 1 A schematic diagram of the circuit state of the pixel-to-be-tested circuit P1 of the display panel 110 of the display device 100. In some embodiments, please refer to... Figure 3 and Figure 6 In the third sub-stage I21 of the second stage I2, the first control signal of the first control signal source EPWM(n), the second control signal of the second control signal source EPAM(n), the test control signal of the test control signal source TEST(n), and the sweep signal of the sweep signal source Sweep(n) are all at low level, while the write signal of the write signal source SP(n) and the initial signal of the initial signal source VST(n) are at high level.

[0078] In some embodiments, the first control signal of the first control signal source EPWM(n) forms a first current path R1 in the pulse width modulation circuit PWM through transistors T1, T3 and T5 of the pulse width modulation circuit PWM.

[0079] In some embodiments, the second control signal from the second control signal source EPAM(n) passes through transistor T6 of the pulse width modulation (PWM) circuit and forms a second current path R2 between the system high voltage source VDD_PAM and the data line DL1. The second current path R2 originates from the system high voltage source VDD_PAM, flows through transistor T6 of the PWM circuit, transistors T8, T10, and T15 of the pulse amplitude modulation (PAM) circuit, and the detection transistor T13 of the bypass circuit BP, and finally flows to the data line DL1.

[0080] In some embodiments, the first detection signal Vsig(m)_R / G / B stored in the first capacitor C1 of the pulse width modulation circuit (PWM) is read out by the driving current along the first current path R1 and collected into the second current path R2. Then, the second detection signal stored in the second capacitor C2 of the pulse amplitude modulation circuit (PAM) is read out by the driving current along the second current path R2. The pixel circuit P1 under test generates a detection result signal based on the first detection signal Vsig(m)_R / G / B and the second detection signal.

[0081] Furthermore, the second control signal of the second control signal source EPAM(n) is transmitted to the data line DL1 via the transistor T15 of the pulse width modulation circuit PWM and the test signal of the test control signal source TEST(n) via the detection transistor T13 of the bypass circuit BP.

[0082] In some embodiments, please refer to Figure 1The detection signal source 120 uses multiple positioning points of multiple data lines (e.g., data lines DL1 to DL[N]), multiple gate lines (e.g., gate lines G1 to G[N]), and detection result signals to lock at least one abnormality in multiple pixel circuits under test (e.g., pixel circuits under test P1 to P[N], P[N+1] to P[2N], and P[M]).

[0083] According to the foregoing embodiments, this application provides a display panel and a display device, which stores the detection signal in the capacitor of the pixel circuit under test, and sets a bypass circuit in the light-emitting element of the pixel circuit under test, and couples the bypass circuit to the data line to generate a driving current to read out the detection signal, so that the detection signal source locks the abnormal specific pixel circuit in the display panel.

[0084] While this application has disclosed detailed embodiments as described above, it does not exclude other possible implementations. Therefore, the scope of protection of this application should be determined by the appended claims, and not by the limitations of the foregoing embodiments.

[0085] For those skilled in the art, various modifications and refinements can be made to this application without departing from the spirit and scope of this application. Based on the foregoing embodiments, all modifications and refinements made to this application are also covered within the protection scope of this application.

Claims

1. A display panel, comprising: Data cable; as well as A pixel circuit under test, coupled to the data line, is used to receive a first detection signal from a self-detection signal source and a second detection signal from a pixel data signal source. The pixel circuit under test generates a drive current to read the first and second detection signals, thereby generating a detection result signal. The pixel circuit under test includes: A light-emitting element, used to emit light according to the driving current; as well as A bypass circuit, coupled to the light-emitting element and the data line, is used to transmit the detection result signal to the detection signal source via the data line according to the test control signal, so that the detection signal source can determine whether the pixel circuit under test is abnormal. The circuit for the pixel under test also includes: A pulse width modulation circuit is coupled to the detection signal source and the first control signal source, and is used to drive the circuit according to the first control signal from the first control signal source.

2. The display panel of claim 1, wherein the bypass circuit comprises: A detection transistor is coupled to the light-emitting element and the data line, and is used to transmit the detection result signal to the data line according to the test control signal.

3. The display panel as claimed in claim 2, wherein the pixel circuit under test further comprises: A pulse amplitude modulation circuit is coupled to the light-emitting element, the detection transistor, the pulse width modulation circuit, the pixel data signal source, and the second control signal source, and is used to drive the device according to the second control signal from the second control signal source.

4. The display panel of claim 3, wherein the detection transistor comprises: The first terminal is coupled to the pulse amplitude modulation circuit; The second end is coupled to the data line; as well as The control terminal is coupled to the test control signal source and is used to receive the test control signal from the test control signal source, thereby responding to the test control signal to conduct and output the test result signal to the data line.

5. The display panel of claim 4, wherein the pulse width modulation circuit and the pulse amplitude modulation circuit are both coupled to an initial signal source, and the pulse width modulation circuit and the pulse amplitude modulation circuit are reset according to an initial signal from one of the initial signal sources in a first sub-stage of the first stage.

6. The display panel of claim 5, wherein the pulse width modulation circuit and the pulse amplitude modulation circuit are both coupled to a write signal source, the pulse width modulation circuit stores the first detection signal of the detection signal source according to the write signal of the write signal source in the second sub-stage of the first stage, and the pulse amplitude modulation circuit stores the second detection signal of the pixel data signal source according to the write signal of the write signal source in the second sub-stage of the first stage.

7. The display panel of claim 6, wherein the pulse width modulation circuit includes a first capacitor, wherein the first capacitor is coupled to the detection signal source and is used to store the first detection signal in the second sub-stage of the first stage, wherein the pulse amplitude modulation circuit includes a second capacitor, wherein the second capacitor is coupled to the pixel data signal source and is used to store the second detection signal in the second sub-stage of the first stage.

8. The display panel of claim 7, wherein the pulse width modulation circuit is turned on in the second stage according to the first control signal to read the first detection signal in the first capacitor of the pulse width modulation circuit and output it to the pulse amplitude modulation circuit, wherein the pulse amplitude modulation circuit is turned on in the second stage according to the second control signal to read the second detection signal in the second capacitor of the pulse amplitude modulation circuit and output the first detection signal and the second detection signal to the data line through the detection transistor.

9. The display panel as claimed in claim 1, further comprising: A gate line is coupled to the pixel circuit under test, wherein the data line is not parallel to the gate line.

10. A display device comprising: Display panel, including: Multiple data cables; Multiple gate lines; as well as Multiple pixel circuits to be tested are respectively coupled to the data line and the gate line; as well as A detection signal source is coupled to each of the pixel circuits under test (DUT) and the data line of the display panel, and is used to generate a first detection signal to each of the DUTs, thereby causing each of the DUTs to generate a detection result signal to the data line based on the first and second detection signals. The detection signal source determines whether each of the DUTs is abnormal based on the detection result signal. If each of the DUTs is abnormal, the detection signal source uses multiple positioning points on the data line and the gate line to pinpoint the abnormal DUT. Each of the pixel circuits under test includes: A pulse width modulation circuit is coupled to the detection signal source and the first control signal source, and is used to drive the circuit according to the first control signal from the first control signal source.

11. The display device of claim 10, wherein the data lines are arranged along a first direction, wherein the gate lines are arranged along a second direction, wherein the data lines and the gate lines are not parallel, and wherein the data lines and the gate lines intersect to form the positioning point.

12. The display device of claim 11, wherein the pixel circuits under test are respectively located at the positioning points.

13. The display device of claim 10, wherein each of the pixel circuits under test further comprises: Light-emitting elements, used to emit light; and A detection transistor is coupled to at least one of the light-emitting element and the data lines, and is used to output the detection result signal to at least one of the data lines according to a test control signal.

14. The display device of claim 13, wherein each of the pixel circuit under test further comprises: A pulse amplitude modulation circuit is coupled to the light-emitting element, the detection transistor, the pulse width modulation circuit, the pixel data signal source, and the second control signal source, and is used to drive the device according to the second control signal from the second control signal source.

15. The display device of claim 14, wherein the detection transistor comprises: The first terminal is coupled to the pulse amplitude modulation circuit; The second end is coupled to at least one of the data lines; as well as The control terminal is coupled to the test control signal source and is used to receive the test control signal from the test control signal source, thereby responding to the test control signal being turned on to output the detection result signal to at least one of the data lines.

16. The display device of claim 15, wherein the pulse width modulation circuit and the pulse amplitude modulation circuit are both coupled to an initial signal source, and the pulse width modulation circuit and the pulse amplitude modulation circuit are reset according to the initial signal of the initial signal source in a first sub-stage of the first stage.

17. The display device of claim 16, wherein the pulse width modulation circuit and the pulse amplitude modulation circuit are both coupled to a write signal source, the pulse width modulation circuit stores the first detection signal of the detection signal source to a first capacitor of the pulse width modulation circuit according to a write signal from one of the write signal sources in the second sub-stage of the first stage, and the pulse amplitude modulation circuit stores the second detection signal of the pixel data signal source to a second capacitor of the pulse amplitude modulation circuit according to the write signal from the write signal source in the second sub-stage of the first stage.

18. The display device of claim 17, wherein the pulse width modulation circuit is turned on in a second stage according to the first control signal to read the first detection signal in the first capacitor of the pulse width modulation circuit and output it to the pulse amplitude modulation circuit, wherein the pulse amplitude modulation circuit is turned on in a second stage according to the second control signal to read the second detection signal in the second capacitor of the pulse amplitude modulation circuit and output the first detection signal and the second detection signal to at least one of the data lines through the detection transistor.

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