Display substrate, display driving method, and display device

Abstract

This disclosure provides a display substrate, a display driving method, and a display device. The display substrate includes: a gate driving circuit including a plurality of cascaded shift register units; a plurality of first gate lines, each connected to the output terminal of a shift register unit; a plurality of second gate lines, each connected to the output terminal of a shift register unit; a gating circuit for time-division control of the gate driving circuit to drive the plurality of first gate lines or to drive a continuous segment of the plurality of second gate lines; a first type of pixel circuit connected to the first gate lines; and a second type of pixel circuit connected to the second gate lines. The bezel size of this display substrate is relatively small.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display substrate, a display driving method, and a display device. Background Technology

[0002] This section is intended to provide background or context for the embodiments set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] In related technologies, the display panel also functions as a fingerprint recognition device. This requires two sets of gate driving circuits on both sides of the display substrate: one set for display and the other for fingerprint recognition. The display panel has a relatively large bezel. Summary of the Invention

[0004] This disclosure provides a display substrate, a display driving method, and a display device.

[0005] This disclosure adopts the following technical solution: a display substrate, comprising:

[0006] The gate drive circuit includes multiple cascaded shift register units;

[0007] Multiple first gate lines are each connected to the output of a shift register unit;

[0008] Multiple second gate lines are each connected to the output of a shift register unit;

[0009] A gating circuit is used to control the gate driving circuit to drive the plurality of first gate lines or drive a continuous segment of the plurality of second gate lines in a time-division manner.

[0010] A first type of pixel circuit connected to the first gate line;

[0011] A second type of pixel circuit connected to the second gate line.

[0012] In some embodiments, the gating circuit includes:

[0013] A first gate line and a plurality of first switching elements, wherein the plurality of first switching elements are connected one-to-one with the plurality of first gate lines, the first gate line is connected to the control electrode of each first switching element, the first electrode of each first switching element is connected to the output terminal of one of the shift register units, and the second electrode of each first switching element is connected to the corresponding first gate line.

[0014] The second gate line and a plurality of second switching elements are connected one-to-one with continuous segments of the plurality of second gate lines. The second gate line is connected to the control electrode of each second switching element. The first electrode of each second switching element is connected to the output terminal of one of the shift register units. The second electrode of each second switching element is connected to the corresponding second gate line.

[0015] In some embodiments, the output terminal of the shift register unit is short-circuited to the second pole of the corresponding first switching element and the second pole of the corresponding second switching element.

[0016] In some embodiments, the output terminal of the shift register unit is short-circuited to the second pole of the corresponding first switching element, and the output terminal of the shift register unit is also connected to the second pole of the corresponding second switching element through an inverter circuit.

[0017] In some embodiments, the first gating control line and the second gating control line are controlled independently; or...

[0018] The first gating control line and the second gating control line are electrically connected, and the polarities of the first switching element and the second switching element are opposite.

[0019] In some embodiments, the second terminals of the plurality of first switching elements are respectively connected to the first terminal of a first capacitor, and the second terminal of the first capacitor is connected to a fixed voltage terminal; and / or, the second terminals of the plurality of second switching elements are respectively connected to the first terminal of a second capacitor, and the second terminal of the second capacitor is connected to a fixed voltage terminal.

[0020] In some embodiments, the plurality of second gate lines divide at least one continuous segment. When the beginning of any continuous segment corresponds to a shift register unit at the middle position, the shift register unit corresponding to the beginning of the segment has two input terminals with different priorities. The input terminal with lower priority is connected to the output terminal of the other shift register unit, and the input terminal with higher priority is independently controlled.

[0021] In the case where the shift register unit at the middle position corresponds to the end of any continuous segment, the shift register unit corresponding to the end of the segment has two input terminals with different priorities. The input terminal with lower priority is connected to the output terminal of the other shift register unit, and the input terminal with higher priority is independently controlled.

[0022] In some embodiments, the first type of pixel circuit includes a display pixel circuit, and the second type of pixel circuit includes a fingerprint recognition pixel circuit.

[0023] This disclosure adopts the following technical solution: a display driving method for driving the aforementioned display substrate, the display driving method comprising:

[0024] During the first type of data read / write cycle, the gating circuit controls the first gate line to be connected to the output terminal of the corresponding shift register unit, and controls the second gate line to be disconnected from the output terminal of the corresponding shift register unit;

[0025] During the second type of data read / write cycle between two adjacent first type of data read / write cycles, the gating circuit controls the second gate line to be connected to the output terminal of the corresponding shift register unit, and controls the first gate line to be disconnected from the output terminal of the corresponding shift register unit.

[0026] The present disclosure adopts the following technical solution: a display device, including the aforementioned display substrate.

[0027] Some embodiments disclosed herein help to reduce the bezel size of display devices. Attached Figure Description

[0028] Figure 1 This is a circuit diagram of a display substrate according to an embodiment of the present disclosure.

[0029] Figure 2 yes Figure 1 The diagram shown is a driving timing diagram of the display substrate.

[0030] Figure 3 This is a circuit diagram of a display substrate according to another embodiment of the present disclosure.

[0031] Figure 4 yes Figure 3 The diagram shown is a driving timing diagram of the display substrate.

[0032] Figure 5 This is an example of the first pixel circuit of an embodiment of this disclosure.

[0033] Figure 6 This is an example of the second pixel circuit in an embodiment of this disclosure. Detailed Implementation

[0034] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0035] Figure 1 This is a circuit diagram of a display substrate according to an embodiment of the present disclosure. Figure 2 yes Figure 1 The diagram shown is a driving timing diagram of the display substrate. Figure 3 This is a circuit diagram of a display substrate according to another embodiment of the present disclosure. Figure 4 yes Figure 3 The diagram shown is a driving timing diagram of the display substrate. Figure 5This is an example of the first pixel circuit of an embodiment of this disclosure. Figure 6 This is an example of the second pixel circuit in an embodiment of this disclosure.

[0036] Combination Figures 1 to 6 The embodiments of this disclosure provide a display substrate, comprising:

[0037] The gate drive circuit includes multiple cascaded shift register units 1;

[0038] Multiple first gate lines L1 are each connected to the output of a shift register unit 1;

[0039] Multiple second gate lines L2 are each connected to the output of a shift register unit 1;

[0040] The gating circuit 2 is used to control the gate driving circuit to drive a continuous segment of the plurality of first gate lines L1 or the plurality of second gate lines L2 in a time-division manner.

[0041] A first type of pixel circuit connected to the first gate line L1;

[0042] A second type of pixel circuit connected to the second gate line L2.

[0043] The same gate driving circuit can drive the first gate line or the second gate line at different times. This allows the first type of pixel circuit and the second type of pixel circuit in the display substrate to operate in time slots.

[0044] refer to Figure 5 In one exemplary embodiment, the first type of pixel circuit includes a transistor T0 and a capacitor C. The gate of transistor T0 is connected to a first type of gate line L1, the first terminal of transistor T0 is connected to a data line (not shown in the figures), and the second terminal of transistor T0 is connected to the first terminal of capacitor C. The second terminal of capacitor C is connected to a fixed voltage terminal (e.g., grounded or connected to a common voltage terminal). The first type of pixel circuit is used, for example, in a display.

[0045] refer to Figure 6 In one exemplary embodiment, the second type of pixel circuit includes a transistor T0a and a photodiode D. The gate of transistor T0a is connected to a second type of gate line L2, the first terminal of transistor T0a is connected to a sensing line (not shown), and the second terminal of transistor T0a is connected to the cathode of photodiode D. The anode of photodiode D receives a negative voltage, causing photodiode D to be in a reverse-biased state. When the gate of transistor T0a receives an effective voltage and is turned on, the photocurrent of photodiode D can be detected on the sensing line. Because the light intensity is different at the ridges of the finger, the photocurrent of photodiode D at the corresponding locations is different. This achieves fingerprint recognition. In this embodiment, the second type of pixel circuit is used for fingerprint recognition.

[0046] In some embodiments, reference Figure 1 and Figure 3 The gating circuit 2 includes:

[0047] A first gate line MUX_display and a plurality of first switching elements T1 are connected one-to-one with the plurality of first gate lines MUX_display. The first gate line MUX_display is connected to the control terminal of each first switching element T1. The first terminal of each first switching element T1 is connected to the output terminal G(1)……G(n), G(n+1), G(n+2), G(n+100)…… of a shift register unit 1. The second terminal of each first switching element T1 is connected to the corresponding first gate line L1.

[0048] The second gate line MUX_sensor and a plurality of second switching elements T2 are connected one-to-one with consecutive segments of the plurality of second gate lines L2. The second gate line MUX_sensor is connected to the control pole of each second switching element T2. The first pole of each second switching element T2 is connected to the output terminal G(1)……G(n), G(n+1), G(n+2), G(n+100)…… of the shift register unit 1, respectively. The second pole of each second switching element T2 is connected to the corresponding second gate line L2.

[0049] Combination Figure 1 and Figure 3 When the first gate line MUX_display provides a low-level voltage, the shift register unit 1 is connected to the first gate line L1 and disconnected from the second gate line L2. The display substrate simultaneously enters the first type of data read / write cycle (e.g., display time). The data line (not shown) of the display substrate for display receives the data voltage provided by the external driving circuit (not shown).

[0050] Continue to combine Figure 1 and Figure 3 When the second gate line MUX_sensor provides a low-level voltage, the shift register unit 1 is connected to the second gate line L2 and disconnected from the first gate line L1. At the same time, the display substrate enters the second type of data read / write cycle (e.g., recognition time), and the sensing line (not shown) of the display substrate for fingerprint recognition receives photosensitive current.

[0051] In some embodiments, the output terminal of the shift register T1 is short-circuited to the second pole of the corresponding first switching element T1 and the second pole of the corresponding second switching element T2.

[0052] refer to Figure 1 and combined Figure 5 and Figure 6 The gate voltage of the switching element T0 in the first pixel circuit connected by the first gate line L1 is active high, and the gate voltage of the switching element T0a in the second pixel circuit connected by the second gate line L2 is active high. When the shift register unit 1 transmits a high-level pulse, the high-level pulse output by each shift register unit 1 can directly drive either the first gate line L1 or the second gate line L2.

[0053] In some embodiments, the output terminal of the shift register unit 1 is short-circuited to the second pole of the corresponding first switching element T1, and the output terminal of the shift register unit 1 is also connected to the second pole of the corresponding second switching element T2 through the inverter circuit 3.

[0054] refer to Figure 3 and combined Figure 5 and Figure 6 Assuming that Figure 6 In the second pixel circuit, the switching element T0a is replaced with a P-type field-effect transistor (PMOSFET), whose gate voltage is active low. The gate voltage of the switching element T0 in the first pixel circuit connected to the first gate line L1 is active high. When the shift register unit 1 transmits a high-level pulse, each high-level pulse output by the shift register unit 1 can directly drive the first gate line L1. It needs to be inverted to a low-level voltage by the inverter circuit 3 before driving the second gate line L2.

[0055] The function of inverter current 3 is to convert high-level voltage to low-level voltage and low-level voltage to high-level voltage.

[0056] In some embodiments, the first gating control line MUX_display and the second gating control line MUX_sensor are independently controlled, for example, they are connected to two independent ports of the driver chip (not shown).

[0057] Alternatively, in other embodiments, the first gating control line MUX_display and the second gating control line MUX_sensor are electrically connected, and the polarities of the first switching element T1 and the second switching element T2 are opposite.

[0058] For example, the first switching element T1 is a PMOSFET, and the second switching element T2 is an N-type field-effect transistor (NMOSFET). When both the first gating control line MUX_display and the second gating control line MUX_sensor receive a high-level voltage, the second switching element T2 is turned on, and the first switching element T1 is turned off. When both the first gating control line MUX_display and the second gating control line MUX_sensor receive a low-level voltage, the second switching element T2 is turned off, and the first switching element T1 is turned on.

[0059] In some embodiments, reference Figure 1 and Figure 3 The second terminals of the plurality of first switching elements T1 are respectively connected to the first terminal of a first capacitor C11, and the second terminal of the first capacitor C11 is connected to a fixed voltage terminal Vbias; and / or, the second terminals of the plurality of second switching elements T2 are respectively connected to the first terminal of a second capacitor C21, and the second terminal of the second capacitor C21 is connected to a fixed voltage terminal Vbias.

[0060] In some embodiments, the fixed voltage terminal Vbias is ground, a common voltage terminal, a constant high-level voltage, or a constant low-level voltage. The voltage on the fixed voltage terminal Vbias can be provided by a specific signal line on the display substrate, or it can be provided separately by a driver chip (not shown).

[0061] The functions of the first capacitor C11 and the second capacitor C21 are to maintain the stability of the output voltage of the second terminal of the first switching element T1 and the second switching element T2, respectively.

[0062] In some embodiments, the plurality of second gate lines L2 divide at least one continuous segment. When the beginning of any continuous segment corresponds to the shift register unit 1 at the middle position, the shift register unit 1 corresponding to the beginning of the segment has two input terminals with different priorities. The input terminal with lower priority is connected to the output terminal of the other shift register unit 1, and the input terminal with higher priority is independently controlled.

[0063] In the case where the shift register unit 1 at the middle position corresponding to the end of any continuous segment, the shift register unit 1 corresponding to the end of the segment has two input terminals with different priorities. The input terminal with lower priority is connected to the output terminal of the other shift register unit 1, and the input terminal with higher priority is independently controlled.

[0064] refer to Figure 1The second gate line L2 connected to the first shift register unit 1 (whose output is labeled G(1)) to the nth shift register unit 1 (whose output is labeled G(n)) is a continuous segment. The (n+1)th shift register unit 1 has two inputs with different priorities. The input with lower priority is connected to the output G(n) of the other shift register unit, and the input with higher priority receives the start signal Sensor_STV1. When both signals CK and CK2 are low, signal G(n) is low, signal Sensor_STV1 is high, and the on-resistance of transistor M9 is sufficiently small compared to the on-resistance of transistor M1 (for example, the ratio of the width-to-length ratio of transistor M9 to the width-to-length ratio of transistor M1 is greater than or equal to 3), the gate of transistor M2 receives a high-level voltage (invalid voltage). During the blank period between two adjacent first-type data read / write cycles, the first shift register unit 1 to the nth shift register unit 1 sequentially transmit valid pulse signals, and the valid pulse signals are cut off at the (n+1)th shift register unit and will not continue to be transmitted to the (n+2)th shift register unit 1.

[0065] In this way, only the first to the nth second gate lines L2 can be refreshed during the blank periods of two adjacent first-type data read / write cycles.

[0066] refer to Figure 1 and combined Figure 2 The second gate line L2 connected to the (n+1)th shift register unit 1 (its output is labeled G(n+1)) to the (n+100)th shift register unit 1 (its output is labeled G(n+100)) forms a continuous segment. The (n+1)th shift register unit 1 has two inputs with different priorities. The input with lower priority is connected to the output G(n) of the other shift register units, and the input with higher priority receives the start signal Sensor_STV1. When both signals CK and CK2 are low, regardless of whether signal G(n) is low or high, signal Sensor_STV1 is low, and the on-resistance of transistor M9 is sufficiently smaller than that of transistor M1, the gate of transistor M2 receives a low-level voltage (effective voltage). Since the (n+100th)th shift register unit 1 is the end of this continuous segment, the (n+101st)th shift register unit has two input terminals. The input terminal with lower priority receives the output signal G(n+100) of the (n+100th)th shift register unit 1, and the input terminal with higher priority receives the signal Sensor_STV2.

[0067] During the blank periods of the other two adjacent first type of data read / write cycles, the (n+1)th shift register unit 1 to the (n+100)th shift register unit 1 sequentially transmit valid pulse signals, and the valid pulse signals are cut off at the (n+101)th shift register unit and will not continue to be transmitted to the (n+102)th shift register unit 1.

[0068] In this way, only the (n+1)th to (n+100)th second gate lines L2 can be refreshed during the blank periods of two adjacent first-type data read / write cycles.

[0069] Specifically, the shift register unit 1 with one input terminal includes transistors M1 to M8 and capacitors C1 and C2, and receives external signals CB, CK, VL, and VH. One end of transistor M1 serves as the cascade signal input terminal, and the connection node of transistors M4 and M5 serves as the cascade signal output terminal.

[0070] The shift register unit 1, with two input terminals, includes transistors M1 to M9 and capacitors C1 and C2, and receives external signals CB, CK, VL, and VH. One end of transistor M1 serves as the cascade signal input terminal, the connection node of transistors M4 and M5 serves as the cascade signal output terminal, and one end of transistor M9 serves as the higher priority input terminal.

[0071] Figure 1 and Figure 3 This is merely an example illustrating the circuit structure of one shift register unit; other known shift register unit circuit structures can also be applied to embodiments of this disclosure.

[0072] exist Figure 1 and Figure 2 In the embodiment shown, the multiple second gate lines L2 are divided into multiple continuous segments, which are connected end to end in sequence.

[0073] In some other embodiments, the second gate line L2 may also have only one continuous segment used for fingerprint recognition (i.e., connected to the second type of pixel circuit). Taking a number of 1024 second gate lines L2 as an example: In one exemplary embodiment, the 612th to 1024th second gate lines L2 form a continuous segment and are respectively connected to the second type of pixel circuit. The remaining second gate lines are either floating or grounded. In another exemplary embodiment, the 1st to 300th second gate lines L2 form a continuous segment and are respectively connected to the second pixel circuit. The remaining second gate lines are either floating or grounded. In this embodiment, the 301st shift register unit has two inputs with different priorities to truncate the transmission of valid pulses during the fingerprint recognition phase. In another exemplary embodiment, the first to 1024th second gate lines L2 form a continuous segment, i.e., the entire screen is used for fingerprint recognition, and all second gate lines L2 sequentially receive valid level pulses in one second type of data read / write cycle.

[0074] exist Figure 1 and Figure 2 In the illustrated embodiment, the number of first gate lines L1 and second gate lines L2 are equal and correspond one-to-one. In other embodiments, the number of second gate lines L2 is less than the number of first gate lines L1. For example, the second gate lines L2 correspond one-to-one with the even-numbered first gate lines L1, or the second gate lines L2 correspond one-to-one with only a portion of a series of consecutive first gate lines L1.

[0075] Further Figure 2 and Figure 4 The remaining signals are explained below. Signal D-Gout1 is the voltage signal received by the first gate line L1, where a low-level pulse is a valid signal. Signal D-Gout2 is the voltage signal received by the second gate line L1, where a low-level pulse is a valid signal.

[0076] Signal S-Gout1 is the voltage signal received by the first second gate line L2. Signal S-Gout2 is the voltage signal received by the second second gate line L2. Signal S-Gout100 is the voltage signal received by the 100th second gate line L2. Signal S-Gout101 is the voltage signal received by the 101st second gate line L2.

[0077] exist Figure 2 In the illustrated embodiment, the second gate line L2 sequentially receives low-level pulses. Figure 4 In the embodiment shown, the second gate line L2 sequentially receives high-level pulses.

[0078] Figure 3An inverter circuit 3 is illustrated by way of example. The inverter circuit 3 includes transistors M10, M11, M12 and M13 and capacitor C3, receives signals VL and CB and inverts the output signal of shift register unit 1 to provide it to the second switching element T2.

[0079] Based on the same inventive concept, embodiments of this disclosure further provide a display driving method for driving the aforementioned display substrate, the display driving method comprising:

[0080] During the first type of data read / write cycle, the gating circuit controls the first gate line to be connected to the output terminal of the corresponding shift register unit, and controls the second gate line to be disconnected from the output terminal of the corresponding shift register unit;

[0081] During the blank period between two adjacent first type data read / write cycles, the gating circuit controls the second gate line to conduct between the output terminal of the corresponding shift register unit and controls the first gate line to turn off between the output terminal of the corresponding shift register unit.

[0082] Based on the same inventive concept, embodiments of this disclosure also provide a display device, including the aforementioned display substrate.

[0083] Display devices include, for example, any product or component with display functionality such as display panels, display modules, tablet computers, mobile phones, vehicle display terminals, and navigation devices.

[0084] In some embodiments, the display device is a liquid crystal display, an organic light-emitting diode (OLED) display, a micro-light-emitting diode (Micro-LED) display, or electronic paper.

[0085] The various embodiments in this disclosure are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0086] The scope of protection of this disclosure is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its scope and spirit. If such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, then the intent of this disclosure also includes such modifications and variations.

Claims

1. A display substrate, characterized in that, include: The gate drive circuit includes multiple cascaded shift register units; Multiple first gate lines are each connected to the output of a shift register unit; Multiple second gate lines are each connected to the output of a shift register unit; A gating circuit is used to control the gate driving circuit to drive the plurality of first gate lines or drive a continuous segment of the plurality of second gate lines in a time-division manner. A first type of pixel circuit connected to the first gate line; A second type of pixel circuit connected to the second gate line; The multiple second gate lines divide at least one continuous segment. When the beginning of any continuous segment corresponds to a shift register unit at the middle position, the shift register unit corresponding to the beginning of the segment has two input terminals with different priorities. The input terminal with lower priority is connected to the output terminal of the other shift register unit, and the input terminal with higher priority is independently controlled. In the case where the shift register unit at the middle position corresponds to the end of any continuous segment, the shift register unit corresponding to the end of the segment has two input terminals with different priorities. The input terminal with lower priority is connected to the output terminal of the other shift register unit, and the input terminal with higher priority is independently controlled.

2. The display substrate according to claim 1, characterized in that, The gating circuit includes: A first gate line and a plurality of first switching elements, wherein the plurality of first switching elements are connected one-to-one with the plurality of first gate lines, the first gate line is connected to the control electrode of each first switching element, the first electrode of each first switching element is connected to the output terminal of one of the shift register units, and the second electrode of each first switching element is connected to the corresponding first gate line. The second gate line and a plurality of second switching elements are connected one-to-one with continuous segments of the plurality of second gate lines. The second gate line is connected to the control electrode of each second switching element. The first electrode of each second switching element is connected to the output terminal of one of the shift register units. The second electrode of each second switching element is connected to the corresponding second gate line.

3. The display substrate according to claim 2, characterized in that, The output terminal of the shift register unit is short-circuited to the second pole of the corresponding first switching element and the second pole of the corresponding second switching element.

4. The display substrate according to claim 2, characterized in that, The output terminal of the shift register unit is short-circuited to the second pole of the corresponding first switching element, and the output terminal of the shift register unit is also connected to the second pole of the corresponding second switching element through an inverter circuit.

5. The display substrate according to claim 2, characterized in that, The first gate line and the second gate line are independently controlled; or, The first gate line and the second gate line are electrically connected, and the polarities of the first switching element and the second switching element are opposite.

6. The display substrate according to claim 2, characterized in that, The second terminals of the plurality of first switching elements are respectively connected to the first terminal of a first capacitor, and the second terminal of the first capacitor is connected to a fixed voltage terminal; and / or, the second terminals of the plurality of second switching elements are respectively connected to the first terminal of a second capacitor, and the second terminal of the second capacitor is connected to a fixed voltage terminal.

7. The display substrate according to claim 1, characterized in that, The first type of pixel circuit includes a display pixel circuit, and the second type of pixel circuit includes a fingerprint recognition pixel circuit.

8. A display driving method, characterized in that, The display driving method for driving a display substrate according to any one of claims 1 to 7 includes: During the first type of data read / write cycle, the gating circuit controls the first gate line to be connected to the output terminal of the corresponding shift register unit, and controls the second gate line to be disconnected from the output terminal of the corresponding shift register unit; During the second type of data read / write cycle between two adjacent first type of data read / write cycles, the gating circuit controls the second gate line to be connected to the output terminal of the corresponding shift register unit, and controls the first gate line to be disconnected from the output terminal of the corresponding shift register unit.

9. A display device, characterized in that, Includes a display substrate according to any one of claims 1 to 7.

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