Gate drive circuit

Abstract

This invention provides a gate driving circuit. The gate driving circuit includes multiple driving circuits. These driving circuits are respectively disposed on multiple sides of a display area. The nth driving circuit is located on the first side of the display area and includes multi-level gate drivers, multiple gate lines, and a signal bus. The multi-level gate drivers are arranged along the first side. The multiple gate lines are respectively coupled to these gate drivers. In the display area, these gate lines extend in a first direction and have different lengths. The signal bus is coupled to these gate drivers. In the layout area outside the display area, the extension direction of the signal bus lines is parallel to the extension direction of the first side and overlaps with multiple data lines.

Description

Technical Field

[0001] This invention relates to a gate driving circuit, and more particularly to a gate driving circuit suitable for non-rectangular displays. Background Technology

[0002] In various applications, displays can have different shapes, such as rectangular, circular, or polygonal. For circular displays, multi-stage gate drivers can be arranged along the periphery of the display area. Multi-stage gate drivers can output multiple gate signals based on control signals from multiple follow-through lines (e.g., buses) to drive corresponding pixel columns in the display area. However, the follow-through lines between each stage of gate drivers are often winding and complex, increasing the difficulty of circuit layout and the layout area. Summary of the Invention

[0003] This invention provides a gate driving circuit suitable for displays (especially non-rectangular displays), and can reduce the complexity of circuit layout and layout area.

[0004] The gate driving circuit of this invention includes multiple driving circuits. These multiple driving circuits are respectively disposed on multiple sides of the display area. The nth driving circuit is located on the first side of the display area and includes a multi-level gate driver, multiple gate lines, and a signal bus. The multi-level gate drivers are arranged along the first side. The multiple gate lines are respectively coupled to these gate drivers. In the display area, these gate lines extend in a first direction and have different lengths. The signal bus is coupled to these gate drivers. In the layout area outside the display area, the extension direction of the signal bus lines is parallel to the extension direction of the first side and overlaps with multiple data lines. n is a positive integer.

[0005] Based on the above, the gate driving circuit of this embodiment simplifies the arrangement of multiple driving circuits and multiple gate drivers by setting multiple gate drivers on each side. The signal bus lines extend in a direction parallel to one side of the display area, which avoids bending the traces, thereby reducing the complexity of the circuit layout and the layout area.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.

[0008] Figure 2 Based on the present invention Figure 1 A schematic diagram of the nth driving circuit shown in the embodiment.

[0009] Figure 3 This is a schematic diagram of a gate drive circuit according to another embodiment of the present invention.

[0010] [Symbol Explanation]

[0011] 100, 300: Gate drive circuit

[0012] 101, 301: The nth driving circuit

[0013] 102, 302: The m-th driving circuit

[0014] 103: The kth driving circuit

[0015] 104: The j-th driving circuit

[0016] A1: Display Area

[0017] A2: Layout Area

[0018] A21~A23: Sector area

[0019] BL1~BL3: Signal bus

[0020] BL1': Reserved portion

[0021] D1, D2, D3, D_SB1: Direction

[0022] DL1~DL4, DL12: Data cables

[0023] GD11~GD14, GD112, GD21~GD24, GD31~GD34: Gate drivers

[0024] GL11~GL14, GL112, GL21~GL24, GL31~GL34: Gate lines

[0025] L1, L2: Centerline

[0026] SB1~SB4: Side Detailed Implementation

[0027] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0028] Figure 1 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. (See reference) Figure 1The gate drive circuit 100 is applicable to displays, and particularly to non-rectangular displays. Non-rectangular displays can be, for example, circular or polygonal displays. In this embodiment, the display can be, for example, a liquid crystal display (LCD), a light-emitting diode (LED), an organic light-emitting diode (OLED), or other displays that provide display functions.

[0029] In this embodiment, the display area A1 of the display may be, for example, a near-circular polygon with multiple sides. Multiple pixel circuits (not shown) of the display may be disposed in the display area A1. A gate driving circuit 100 may be coupled to these pixel circuits to control their light emission. In this embodiment, these pixel circuits may be, for example, a pixel array arranged with multiple pixel columns and multiple pixel rows. These pixel columns may extend in a first direction D1 and may be arranged in a second direction D2. These pixel rows may extend in the second direction D2 and may be arranged in the first direction D1. The number of these pixel columns (or pixel rows) is not identical to form a polygonal array.

[0030] In this embodiment, the gate driving circuit 100 includes multiple driving circuits. For ease of explanation, in... Figure 1 Multiple driving circuits are shown, including the nth driving circuit 101, the mth driving circuit 102, the kth driving circuit 103, and the jth driving circuit 104, and... Figure 1 Several other driving circuits are omitted, where n, m, k, and j are distinct positive integers. Multiple driving circuits 101 to 104 are respectively disposed on multiple edges SB1 to SB4 of the display area A1.

[0031] In this embodiment, the nth driving circuit 101 is located on the first side SB1 of the display area A1. The nth driving circuit 101 includes multi-level gate drivers GD11 to GD14, multiple gate lines GL11 to GL14, and a signal bus BL1. Figure 1 The number and configuration of the gate drivers GD11~GD14, gate lines GL11~GL14, and signal bus BL1 in the embodiment are merely examples and are not intended to limit the scope of the embodiments.

[0032] In this embodiment, gate drivers GD11 to GD14 are arranged along the first side SB1. That is, the arrangement direction of gate drivers GD11 to GD14 is parallel to the extension direction D_SB1 of the first side SB1, and they are arranged sequentially adjacent to each other. In this embodiment, each level of gate driver GD11 to GD14 is coupled to a signal bus BL1. The signal bus BL1 includes multiple control lines (not shown) to transmit multiple control signals respectively. Each level of gate driver GD11 to GD14 can generate corresponding gate signals according to these control signals. Gate drivers GD11 to GD14 are respectively coupled to gate lines GL11 to GL14 to transmit multiple gate signals to multiple pixel circuits in the display area A1 through gate lines GL11 to GL14 respectively.

[0033] In the display area A1, gate lines GL11 to GL14 can extend in the first direction D1. It should be noted that since the gate drive circuit 100 is suitable for circular or polygonal displays, the display area A1 is non-quadrilateral. Therefore, in the display area A1, gate lines GL11 to GL14 have different lengths.

[0034] In layout area A2 outside display area A1, the extension direction of signal bus line BL1 is parallel to the extension direction D_SB1 of the first side SB1. In layout area A2, signal bus line BL1 overlaps with multiple data lines DL1 to DL4. In this embodiment, data lines DL1 to DL4 are coupled to the source driver of the display (not shown) to transmit multiple data signals to multiple pixel circuits in display area A1, respectively. Each data line DL1 to DL4 includes multiple sub-data lines (not shown) to transmit these data signals respectively. Figure 1 The number and configuration of data lines DL1 to DL4 in this embodiment are merely examples and are not intended to limit the scope. In layout area A2, the extension direction of data lines DL1 to DL4 is perpendicular to the extension direction D_SB1 of the first side SB1. In display area A1, data lines DL1 to DL4 can extend in the second direction D2.

[0035] In this embodiment, the m-th driving circuit 102, the k-th driving circuit 103, and the j-th driving circuit can be deduced by referring to the relevant description of the n-th driving circuit 101, and will not be repeated here.

[0036] It is worth mentioning that each driving circuit (e.g., the nth driving circuit 101) is located on a single side SB1 corresponding to the display area A1, and the multi-level gate drivers GD11 to GD14 in each driving circuit are arranged along the single side SB1, which simplifies the arrangement between multiple driving circuits and between the multi-level gate drivers GD11 to GD14. Therefore, the signal bus BL1 can extend in the extension direction D_SB1 parallel to the first side SB1, which avoids the signal bus BL1 having bent traces or extra extended traces, thereby reducing the complexity and layout area of ​​the circuit layout in the display.

[0037] Refer again Figure 1 The display can be, for example, a dual-drive display. That is, the number of drive sources for the display is two. For example, taking the center line L2 extending in the second direction D2 of the display area A1 as the line of symmetry, the drive circuits on the left half (e.g., the nth drive circuit 101) and the drive circuits on the right half (e.g., the mth drive circuit 102) can be symmetrically designed, and can drive multiple pixel circuits on the same pixel column respectively. In this embodiment, taking the center line L1 extending in the first direction D1 of the display area A1 as the line of symmetry, the drive circuits on the upper half (e.g., the nth drive circuit 101) and the drive circuits on the lower half (e.g., the kth drive circuit 103) can be symmetrically designed.

[0038] In detail, in this embodiment, the nth driving circuit 101 and the mth driving circuit 102 are respectively coupled to gate lines GL11 to GL14. The nth driving circuit 101 and the mth driving circuit 102 can share the same gate lines GL11 to GL14 to transmit multiple gate signals to multiple pixel circuits through the gate lines GL11 to GL14 respectively. In this embodiment, the nth driving circuit 101 and the kth driving circuit 103 are respectively coupled to data lines DL1 to DL4. The nth driving circuit 101 and the kth driving circuit 103 can share the same data lines DL1 to DL4 to transmit multiple data signals to multiple pixel circuits through the data lines DL1 to DL4.

[0039] In this embodiment, the layout area A2 includes a first fan-shaped area A21 between the gate drivers GD11 to GD14 and the display area A1, a second fan-shaped area A22 between the gate drivers GD21 to GD24 of the m-th driving circuit 102 and the display area A1, and a third fan-shaped area A23 between the gate drivers GD31 to GD34 of the k-th driving circuit 103 and the display area A1.

[0040] In the first sector A21, the gate line GL11 extends perpendicularly to the extension direction D_SB1 of the first side SB1, and the gate line GL11 has an extension distance. In the display area A1, the gate line GL11 can extend to the second side SB2 in the first direction D1. In the second sector A22, the gate line GL11 extends perpendicularly to the extension direction of the second side SB2, and has the same or different extension distances. The gate lines GL12 to GL14 can be deduced by referring to the relevant description of the gate line GL11, and will not be repeated here.

[0041] It should be noted that because each pixel column includes a different number of pixel circuits, each gate line GL11–GL14 has a different gate loading. For example, Figure 1 The top or bottom pixel column shown has the fewest pixel circuits, and the corresponding gate lines GL11 to GL14 (in display area A1) have the shortest trace distance and the smallest gate load. Figure 1 The pixel column located at the center line L1 has the most pixel circuits, and its corresponding gate line (in display area A1) has the longest trace distance and the largest gate load. In this embodiment, the differences between these gate loads can be compensated, for example, by the length (i.e., extension distance) of gate lines GL11 to GL14 in the first sector A21. That is, for multiple driving circuits located on different sides, the gate lines may have different extension distances in the corresponding sector. In this embodiment, the extension distance is related to the length of each gate line.

[0042] In this embodiment, in the same stage of the driving circuit 101, gate lines GL11 to GL14 may have the same extension distance. This extension distance may differ from the extension distance of other stages of the driving circuit (e.g., a stage of the driving circuit located on the center line L1). In another embodiment, in the same stage of the driving circuit 101, gate lines GL11 to GL14 may have different extension distances. These extension distances may differ from the extension distances of other stages of the driving circuit.

[0043] In the first sector A21, the data lines DL1 to DL4 extend perpendicularly to the extension direction D_SB1 of the first side SB1 and parallel to the extension directions of the gate lines GL11 to GL14. In the display area A1, the data lines DL1 to DL4 can extend to the third side SB3 in the second direction D2. In the third sector A23, the data lines DL1 to DL4 extend perpendicularly to the extension direction of the third side SB3 and parallel to the extension directions of the gate lines GL31 to GL34.

[0044] It should be noted that since display area A1 is not quadrilateral, data lines DL1 to DL4 have different lengths within display area A1. To achieve load matching of data lines between different pixel rows, the traces of data lines DL1 to DL4 pass through (or overlap with) signal bus line BL1 and gate drivers GD11 to GD14 in the first sector A21, cross the center line L1 from the upper semicircle to the lower semicircle in display area A1, and pass through (or overlap with) signal bus line BL3 and the corresponding multi-stage gate driver in the third sector A23.

[0045] In this embodiment, Figure 1 As shown, at both ends of the center line L2 (i.e., the upper and lower areas of layout area A2), the display leaves a portion of the layout area empty to allow the reserved portion BL1' of the signal bus line BL1 to be externally connected to other circuits of the display. In various embodiments, the other signal bus lines BL2 to BL4 can be deduced by referring to the relevant description of the signal bus line BL1, and will not be repeated here.

[0046] Figure 2 Based on the present invention Figure 1 A schematic diagram of the nth driving circuit shown in the embodiment. (Refer to...) Figure 1 as well as Figure 2 The nth driving circuit 101 may include 12 levels of gate drivers GD11 to GD111 and GD112. For ease of explanation, in... Figure 2 The diagram shows several gate drivers GD11, GD111, GD112 and their corresponding gate lines GL11, GL111, GL112 and their corresponding data lines DL11, DL11, DL12, and... Figure 2 Several other gate drivers and their corresponding gate lines and data lines are omitted.

[0047] In this embodiment, the phase of the nth driving circuit 101 represents the number of periodic control signals it is based on, and therefore the phase is related to the number of control lines in the signal bus BL1. That is, the phase can be the number of multi-stage gate drivers GD11 to GD112. In this embodiment, the phase can be designed, for example, based on the refresh rate and load of the multiple pixel circuits.

[0048] It should be noted that the 12-stage gate drivers GD11 to GD112 can function as first-stage gate drivers and occupy a single edge (e.g., SB1). The 12-stage gate drivers GD11 to GD112 can each output multiple gate signals through their corresponding gate lines GL11 to GL112. These gate signals can be directly transmitted to multiple pixel transistors in the corresponding pixel column via their respective gate lines GL11 to GL112 without the need for additional vias or through holes.

[0049] In this embodiment, the number of sides of the display area A1 is related to the resolution of the display, the parameters of the driving circuits 101-104, and the number of driving sources of the display. Specifically, the number of sides of the display area A1 can be determined, for example, by the following formula (1). In formula (1), NSB is the number of sides of the display area A1, RES is the resolution of the display (e.g., 1440), NPH is the number of phases of the driving circuit 101 (e.g., 12 levels), n is the order of the driving circuit 101 on a single side (e.g., 1st order), and ND is the number of driving sources (e.g., 2). Therefore, the number of sides of the display area A1 can be, for example, 240. In this embodiment, since n is a positive integer, n-order (more than one) gate drivers can occupy a single side, thereby reducing the number of sides of the display area A1.

[0050]

[0051] Figure 3 This is a schematic diagram of a gate drive circuit according to another embodiment of the present invention. (See reference) Figure 3 The gate drive circuit 300 is applicable to non-rectangular displays. The gate drive circuit 300 includes multiple drive circuits. The gate drive circuit 300 can be referenced... Figure 1 The relevant descriptions of the gate drive circuit 100 shown are extended by analogy, and some components and their labels are omitted and will not be repeated here.

[0052] exist Figure 3 In the illustrated embodiment, the display may be, for example, a single-drive display. That is, the number of drive sources for the display is one. For example, taking the center line L2 extending in the second direction D2 of the display area A1 as the line of symmetry, each drive circuit on the left half (e.g., the nth drive circuit 301) can drive multiple pixel circuits on odd-numbered columns. Each drive circuit on the right half (e.g., the mth drive circuit 302) can drive multiple pixel circuits on even-numbered columns.

[0053] In detail, in this embodiment, the nth driving circuit 301 transmits multiple gate signals to multiple pixel circuits in columns 1, 3, 5, and 7 respectively via gate lines GL11 to GL14. The mth driving circuit 302 transmits multiple gate signals to multiple pixel circuits in columns 2, 4, 6, and 8 respectively via gate lines GL21 to GL24.

[0054] In the first sector A21, the gate line GL11 extends perpendicularly to the extension direction D_SB1 of the first side SB1, and the gate line GL11 has an extension distance. In the display area A1, the gate line GL11 can extend to the second side SB2 in the first direction D1. The gate lines GL12 to GL14 can be deduced by referring to the relevant description of the gate line GL11 and will not be repeated here.

[0055] In the first sector A22, the extension direction of gate line GL21 is perpendicular to the extension direction of the second side SB2, and gate line GL21 has an extension distance. In the display area A1, gate line GL21 can extend to the first side SB1 in the first direction D1. Gate lines GL22 to GL24 can be deduced by referring to the relevant description of gate line GL11, and will not be repeated here.

[0056] In summary, the gate driving circuit of this invention, by providing multi-stage gate drivers on each side, simplifies the layout between different driving circuits and between multi-stage gate drivers. In this way, the signal bus can extend in a single direction and overlap with the data signal, avoiding bends in the signal bus traces, thereby reducing the complexity and area of ​​the circuit layout in the display.

[0057] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A gate driving circuit, suitable for a display, the display including a polygonal display area and a layout area without a display area, the gate driving circuit comprising: Multiple driving circuits are respectively disposed on multiple sides of the display area, wherein the nth driving circuit is located on the first side of the display area and includes: A multi-stage gate driver is arranged along the first side; A plurality of gate lines, each coupled to the multi-stage gate driver, wherein in the display area, the plurality of gate lines extend in a first direction and have different lengths; and A signal bus, coupled to the multi-level gate driver, extends parallel to the extension direction of the first side and overlaps with multiple data lines in the layout area. The layout area includes a first sector between the multi-level gate driver and the display area. In the first sector, the extension directions of the multiple gate lines are perpendicular to the extension direction of the first side, and the multiple gate lines each have the same extension distance, where n is a positive integer. In the multiple driving circuits respectively disposed on multiple sides of the display area, the extension distance of the gate line corresponding to each driving circuit is related to the length of the gate line corresponding to each driving circuit in the display area. In the first sector, the extension direction of the plurality of data lines is perpendicular to the extension direction of the first side and parallel to the extension direction of the gate lines.

2. The gate driving circuit of claim 1, wherein in the display area, the gate line extends to a second side of the display area in the first direction, wherein in the second sector of the layout area, the extension direction of the gate line is perpendicular to the extension direction of the second side, and the gate line is coupled to the m-th driving circuit located on the second side.

3. The gate driving circuit as claimed in claim 2, wherein the nth driving circuit and the mth driving circuit respectively transmit multiple gate signals to multiple pixel circuits in the display area through the gate line.

4. The gate driving circuit of claim 1, wherein in the display area, the gate line extends to a second side of the display area in the first direction, wherein the m-th driving circuit located on the second side includes a plurality of second gate lines, wherein in the display area, the second gate lines extend to the first side in the first direction.

5. The gate driving circuit of claim 4, wherein the nth driving circuit transmits a plurality of gate signals to a plurality of pixel circuits on odd-numbered columns in the display area through the gate line, and the mth driving circuit transmits a plurality of second gate signals to a plurality of pixel circuits on even-numbered columns in the display area through the second gate line.

6. The gate driving circuit of claim 1, wherein in the display area, the data lines extend in a second direction and have different lengths.

7. The gate driving circuit of claim 6, wherein in the display area, the data line extends to the third side of the display area in the second direction, wherein in the third sector of the layout area, the extension direction of the data line is perpendicular to the extension direction of the third side, and the data line is coupled to the k-th driving circuit located on the third side.

8. The gate driving circuit of claim 1, wherein the number of edges is related to the resolution of the display, the parameters of the driving circuit, and the number of driving sources of the display.

Images