Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor device having a buried word line and a method of fabricating the same. The semiconductor device has a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also has a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate, and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 541,817 and 17 / 544,410 (i.e., priority dates of December 3, 2021 and December 7, 2021), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and its fabrication method. In particular, it relates to a semiconductor device having embedded word lines and its fabrication method. Background Technology

[0003] In a dynamic random access memory (DRAM) device, addresses of multiple memory cells are accessed via multiple word lines. Interference between multiple word lines in different memory cells should be avoided to reduce storage node leakage (e.g., junction leakage and sub-threshold leakage) and to preserve the charge written to the cell capacitor.

[0004] As DRAM devices become highly integrated, it becomes more difficult to insulate a word line (which can be represented as an active word line) in a memory cell from another word line (which can be represented as a passing word line) in an adjacent memory cell. When a passing word line is conducting, the junction leakage current can be accelerated by trap-assisted tunneling, which is generated by an internal electric field.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface; and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

[0007] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface; a first dielectric layer extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer. The semiconductor device also includes a second dielectric layer extending from the surface of the substrate into the substrate; and a second conductive layer disposed in the substrate and separated from the substrate by the second dielectric layer. The first dielectric layer and the second dielectric layer have different thicknesses.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first recess in a first dielectric layer within a substrate; and forming a second recess spaced apart from the first recess and within the substrate. The fabrication method also includes disposing a protective layer on the substrate to cover the second recess; and disposing a second dielectric layer on the first dielectric layer.

[0009] By forming two dielectric layers between the conductive layer and the substrate, the effective electric field can be reduced, thereby reducing the junction leakage current. Therefore, interference between multiple word lines in different memory cells can be avoided, and the charge written to the cell capacitor can be retained.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0012] Figure 1 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0013] Figure 2A This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0014] Figure 2B This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0015] Figure 2C This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0016] Figure 2D This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0017] Figure 2E This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0018] Figure 2F This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0019] Figure 2G This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0020] Figure 2H This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0021] Figure 2I This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0022] Figure 2J This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0023] Figure 2K This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0024] Figure 2L This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0025] Figure 2M This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0026] Figure 2N This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0027] Figure 2O This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0028] Figure 2P This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0029] Figure 2Q This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0030] Figure 2R This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0031] Figure 2S This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0032] Figure 2T This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0033] Figure 3 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 1: Semiconductor components

[0036] 10: Base

[0037] 101: Surface

[0038] 102: Surface

[0039] 10a: Diffusion region

[0040] 10b: Diffusion region

[0041] 11: Dielectric layer

[0042] 11a: Sub-layer

[0043] 11a1: Surface

[0044] 11b: Sublayer

[0045] 11b1: Surface

[0046] 11r: Depression

[0047] 12: Conductive layer

[0048] 121: Surface

[0049] 12m: Conductive material

[0050] 13: Dielectric layer

[0051] 131: Surface

[0052] 13r: Depression

[0053] 14: Conductive layer

[0054] 141: Surface

[0055] 15: Isolation layer

[0056] 16: Bitline

[0057] 16a: Polycrystalline silicon

[0058] 16b: Laminates

[0059] 17: Isolation layer

[0060] 18: Isolation layer

[0061] 18r: Opening

[0062] 19: Capacitor contact plugging

[0063] 20: Isolation layer

[0064] 21: Capacitor contact pad

[0065] 22: Isolation layer

[0066] 23: Capacitor

[0067] 23a: Lower electrode

[0068] 23b: Isolation layer

[0069] 23c: Upper electrode

[0070] 24: Protective layer

[0071] 25: Optical Obscuration

[0072] 30: Preparation method

[0073] S31: Steps

[0074] S32: Steps

[0075] S33: Steps

[0076] S34: Steps

[0077] S35: Steps

[0078] S36: Steps Detailed Implementation

[0079] The various embodiments (or examples) of this disclosure described in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, are considered to be common practice for those skilled in the art to which this disclosure pertains. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0080] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0082] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor element 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 1 may include a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory (DRAM) cell. Figure 1 As shown, in some embodiments, the semiconductor element 1 may include a substrate 10, diffusion regions 10a and 10b, dielectric layers 11 and 13, conductive layers 12 and 14, and an isolation layer 15.

[0083] In some embodiments, conductive layers 12 and 14 can serve as character lines. For example, conductive layers 12 and 14 can interact with multiple character lines (e.g., ...). Figure 1The bit line 16 shown is used together to locate the address of multiple memory cells. For example, conductive layer 14 can be used as a gate electrode of a transistor in a memory cell. Diffusion regions 10a and 10b can be used as a drain region and a source region of the transistor, respectively. Diffusion region 10a can be coupled to a capacitor (e.g., Figure 1 A capacitor 23 is shown, and the diffusion region 10b can be coupled to a bit line (e.g., a capacitor 23). Figure 1 (See bit line 16 shown). This transistor can retain charge in the capacitor. Similarly, conductive layer 12 can serve as a gate electrode of a transistor in another memory cell, and this transistor can retain charge in another capacitor (not shown in the figure).

[0084] In some embodiments, conductive layers 12 and 14 may be configured to locate addresses of different memory cells. In some embodiments, conductive layer 12 may include a passing word line, and conductive layer 14 may include an active word line. As used herein, the term "active word line" refers to a word line configured to receive a voltage to locate the address of a memory cell; and the term "passing word line" refers to a word line configured to receive a voltage to locate the address of an adjacent memory cell.

[0085] In some embodiments, conductive layer 12 may be a through word line in one memory cell, but becomes an active word line in another memory cell. In some embodiments, conductive layer 14 may be an active word line in one memory cell, but becomes a through word line in yet another memory cell.

[0086] In some embodiments, conductive layer 12 and conductive layer 14 may be configured to receive different voltages. For example, conductive layer 12 may be configured to receive a negative voltage and conductive layer 14 may be configured to receive a positive voltage, or vice versa.

[0087] In some embodiments, the semiconductor element 1 may further include a bit line 16, isolation layers 17, 18, 20, 22, a capacitor contact plug 19, a capacitor contact pad 21, and a capacitor 23.

[0088] In some embodiments, the substrate 10 may include a surface 101 and a surface 102, with the surface 102 disposed opposite to the surface 101. In some embodiments, the surface 101 may be an active surface of the substrate 10, while the surface 102 may be a rear surface of the substrate 10.

[0089] In some embodiments, for example, the substrate 10 may include Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, In, InAs, InP, or other group IV-IV, III-V, or II-VI semiconductor materials. In some other embodiments, the substrate 10 may include a single-layer semiconductor, such as silicon / silicon-germanium, silicon-on-insulator, or silicon-on-insulator.

[0090] In some embodiments, diffusion regions 10a and 10b may be disposed on or within the substrate 10. In some embodiments, diffusion regions 10a and 10b may be disposed on or near the surface 101 of the substrate 10. In some embodiments, diffusion regions 10a and 10b may be disposed on opposite sides of the conductive layer 14.

[0091] In some embodiments, diffusion regions 10a and 10b may be doped with an N-type dopant, such as P, As, or Sb. In some other embodiments, diffusion regions 10a and 10b may be doped with a P-type dopant, such as B or In.

[0092] In some embodiments, diffusion regions 10a and 10b may be doped with multiple dopants having the same conductivity type or multiple impurity ions. In some embodiments, diffusion regions 10a and 10b may be doped with dopants having different conductivity types or multiple impurity ions.

[0093] In some embodiments, the dielectric layer 11 may be disposed in the substrate 10. In some embodiments, the dielectric layer 11 may be part of an insulating structure, such as a shallow trench isolation (STI) structure. In some embodiments, the dielectric layer 11 may be disposed in an STI trench of the substrate 10.

[0094] In some embodiments, dielectric layer 11 may include a two-layer structure. For example, dielectric layer 11 may include a sublayer 11a and a sublayer 11b. For example, an interface or boundary may be seen between sublayer 11a and sublayer 11b.

[0095] In some embodiments, sublayer 11a may include a dielectric layer, such as an oxide film. Sublayer 11a may extend from surface 101 of substrate 10 into substrate 10. Sublayer 11a may partially penetrate substrate 10. In some embodiments, sublayer 11a may have a surface (e.g., an upper surface) 11a1 that is substantially coplanar with surface 101 of substrate 10.

[0096] In some embodiments, sublayer 11b includes a dielectric layer, such as an oxide film. Sublayer 11b may extend from surface 101 of substrate 10 into substrate 10. Sublayer 11b may partially penetrate substrate 10. In some embodiments, sublayer 11b may have a surface (e.g., an upper surface) 11b1 that is substantially coplanar with surface 101 of substrate 10. In some embodiments, surface 11b1 of sublayer 11b may be substantially coplanar with surface 11a1 of sublayer 11a.

[0097] In some embodiments, sublayer 11a is disposed between sublayer 11a and substrate 10. In some embodiments, sublayer 11b is disposed between sublayer 11a and conductive layer 12. In some embodiments, sublayer 11a may define a recess, and sublayer 11b may be disposed in the recess.

[0098] In some embodiments, each of sublayers 11a and 11b may include a low dielectric constant material, such as fluorine-doped silica (FSG), organosilicon glass (OSG), carbon-doped oxide (CDO), porous silica, etc. In some embodiments, each of sublayers 11a and 11b may be a dielectric material having a dielectric constant lower than that of silica, or a dielectric material having a dielectric constant lower than approximately 4.0.

[0099] In some embodiments, sublayer 11a and sublayer 11b may be made of different materials. In some embodiments, sublayer 11a and sublayer 11b may be made of the same material, but their fabrication techniques include different steps. For example, the fabrication technique of sublayer 11a may include a chemical vapor deposition (CVD) process, and the fabrication technique of sublayer 11b may include an atomic layer deposition (ALD) process. For example, sublayer 11a and sublayer 11b may include different steps.

[0100] In some embodiments, sublayers 11a and 11b may have different densities, such as different particle densities. For example, a density of sublayer 11a may be lower than a density of sublayer 11b. A density of sublayer 11b may be higher than a density of sublayer 11a. For example, sublayer 11b may be denser than sublayer 11a. For example, the surface 11b1 of sublayer 11b may be denser than the surface 11a1 of sublayer 11a.

[0101] In some embodiments, the conductive layer 12 may be disposed in the substrate 10. In some embodiments, the conductive layer 12 may be disposed in the dielectric layer 11. In some embodiments, the dielectric layer 11 (including sublayers 11a and 11b) may define a recess, and the conductive layer 12 may be disposed in the recess. In some embodiments, the conductive layer 12 may be surrounded by sublayers 11b and further surrounded by sublayers 11a. In some embodiments, the conductive layer 12 may be separated from the substrate 10 by sublayers 10a and 10b.

[0102] In some embodiments, the conductive layer 12 may have a surface (e.g., an upper surface) 121 that is separated from the surface 101 of the substrate 10. For example, the surface 121 of the conductive layer 12 may not be coplanar with the surface 101 of the substrate 10. In some embodiments, the surface 121 of the conductive layer 12 may be separated from the surfaces 11b1 of the sublayer 11b and 11a1 of the sublayer 11a. For example, the surface 121 of the conductive layer 12 may not be coplanar with the surfaces 11b1 of the sublayer 11b and 11a1 of the sublayer 11a.

[0103] In some embodiments, the conductive layer 12 may include a single layer of metal, a metal composite, or a multilayer conductive material. In some embodiments, the conductive layer 12 may include polysilicon (poly-Si), TiN, WN, or the like.

[0104] In some embodiments, the dielectric layer 13 may be disposed in the substrate 10. In some embodiments, the dielectric layer 13 may include an oxide film. The dielectric layer 13 may extend from the surface 101 of the substrate 10 into the substrate 10. The dielectric layer 13 may penetrate the substrate 10. In some embodiments, the dielectric layer 13 may have a surface 131 (e.g., an upper surface) that is substantially coplanar with the surface 101 of the substrate 10.

[0105] In some embodiments, the dielectric layer 13 may include a low dielectric constant material, such as fluorine-doped silica (FSG), organosilicon glass (OSG), carbon-doped oxide (CDO), porous silica, etc. In some embodiments, the dielectric layer 13 may include a dielectric material having a dielectric constant lower than that of silica, or a dielectric material having a dielectric constant lower than about 4.0.

[0106] In some embodiments, dielectric layer 13 may have a material different from the materials of sublayers 11a and 11b. In some embodiments, dielectric layer 13, sublayers 11a, and sublayers 11b may have the same material, and their fabrication techniques may include different steps. For example, the fabrication technique of dielectric layer 13 may include a thermal oxidation step. In some embodiments, dielectric layer 13 is formed after sublayers 11a and 11b are formed.

[0107] In some embodiments, dielectric layer 13, sublayer 11a, and sublayer 11b may have different densities, such as different particle densities. For example, a density of dielectric layer 13 may be higher than a density of sublayer 11a and lower than a density of sublayer 11b. For example, dielectric layer 13 (or surface 131) may be denser than sublayer 11a (or surface 11a1). For example, sublayer 11b (or surface 11b1) may be denser than dielectric layer (or surface 131).

[0108] In some embodiments, the conductive layer 14 may be disposed in the substrate 10. In some embodiments, the conductive layer 14 may be disposed in the dielectric layer 13. In some embodiments, the dielectric layer 13 may define a recess, and the conductive layer 14 may be disposed in the recess. In some embodiments, the conductive layer 14 may be surrounded by the dielectric layer 13. In some embodiments, the conductive layer 14 may be separated from the substrate 10 by the dielectric layer 13. In some embodiments, the dielectric layer 13 may be disposed between the conductive layer 14 and the substrate 10.

[0109] In some embodiments, the conductive layer 14 may have a surface (e.g., an upper surface) 141 that is separated from the surface 101 of the substrate 10. For example, the surface 141 of the conductive layer 14 may not be coplanar with the surface 101 of the substrate 10. In some embodiments, the surface 141 of the conductive layer 14 may be separated from the surface 131 of the dielectric layer 13. For example, the surface 141 of the conductive layer 14 may not be coplanar with the surface 131 of the dielectric layer 13.

[0110] In some embodiments, the conductive layer 14 may include a single layer of metal, a metal composite, or a multilayer conductive material. In some embodiments, the conductive layer 14 may include polycrystalline silicon, TiN, WN, or the like.

[0111] In some embodiments, dielectric layer 11 (including sublayers 11a and 11b) and dielectric layer 13 may have different thicknesses. For example, the thickness of dielectric layer 11 (e.g., maximum thickness or average thickness) may be greater than the thickness of dielectric layer 13 (e.g., maximum thickness or average thickness). For example, the distance between conductive layer 12 and substrate 10 may be greater than the distance between conductive layer 14 and substrate 10.

[0112] In some embodiments, the dielectric constant of dielectric layer 11 (including sublayers 11a and 11b) may be lower than the dielectric constant of substrate 10. In some embodiments, the dielectric constant of dielectric layer 13 may be lower than the dielectric constant of substrate 10.

[0113] In some embodiments, the low dielectric constant characteristics of dielectric layers 11 and 13 can help with insulation between conductive layers 12 and 14. For example, the first dielectric constant characteristics of dielectric layers 11 and 13 can help reduce the effective electric field generated when conductive layer 12 is turned on or activated (e.g., via word lines) and prevent interference between them.

[0114] In some embodiments, the isolation layer 15 may be disposed on the surface 121 of the conductive layer 12 and on the surface 141 of the conductive layer 14. In some embodiments, a portion of the isolation layer 15 on the conductive layer 12 may be separated from the substrate 10 by a dielectric layer 11 (including sublayers 11a and 11b). In some embodiments, a portion of the isolation layer 15 on the conductive layer 12 may cover the surface 11a1 of the sublayer 11a and the surface 11b1 of the sublayer 11b. In some embodiments, a portion of the isolation layer 15 on the conductive layer 12 may contact the surface 11a1 of the sublayer 11a and the surface 11b1 of the sublayer 11b.

[0115] In some embodiments, a portion of the insulating layer 15 on the conductive layer 14 may be separated from the substrate 10 by the dielectric layer 13. In some embodiments, a portion of the insulating layer 15 on the conductive layer 14 may cover the surface 131 of the dielectric layer 13. In some embodiments, a portion of the insulating layer 15 on the conductive layer 14 may contact the surface 131 of the dielectric layer 13.

[0116] In some embodiments, at least a portion of the insulating layer 15 may be embedded in the substrate 10. For example, at least a portion of the insulating layer 15 may be embedded in a recess defined by the surface 121 of the sublayer 11b and the conductive layer 12. For example, at least a portion of the insulating layer 15 may be embedded in a recess defined by the surface 141 of the dielectric layer 13 and the conductive layer 14.

[0117] In some embodiments, the isolation layer 15 may include SiO2, Si3N4, N2OSi2, N2OSi2, etc., but is not limited thereto. In some embodiments, the isolation layer 15 may cover and protect the surface 121 of the conductive layer 12 and the surface 141 of the conductive layer 14.

[0118] In some embodiments, bit line 16 may be disposed on diffusion region 10b. In some embodiments, bit line 16 may be electrically connected to diffusion region 10b. In some embodiments, bit line 16 may include a polysilicon 16a and a lamination 16b, but is not limited thereto, wherein lamination 16b includes a WN x Membrane, W membrane, etc.

[0119] In some embodiments, isolation layer 17 may be disposed on isolation layer 15 and bit line 16. In some embodiments, isolation layer 17 may include SiO2, Si3N4, N2OSi2, N2OSi2, etc., but is not limited thereto.

[0120] In some embodiments, the isolation layer 18 may be disposed on the isolation layer 17. In some embodiments, an upper surface of the isolation layer 18 may be substantially coplanar with an upper surface of the capacitor contact pad plug 19. In some embodiments, the isolation layer 18 may include SiO2, Si3N4, N2OSi2, N2OSi2, etc., but is not limited thereto.

[0121] In some embodiments, the capacitor contact plug 19 may extend through or through the insulating layer 17 and the insulating layer 18. In some embodiments, the capacitor contact plug 19 may be disposed on the diffusion region 10a. In some embodiments, the capacitor contact plug 19 may be electrically connected to the diffusion region 10a.

[0122] In some embodiments, the capacitor contact plug 19 may include a suitable conductive material. For example, the capacitor contact plug 19 may include W, Cu, Al, Ag, alloys thereof, or combinations thereof.

[0123] In some embodiments, isolation layer 20 may be disposed on isolation layer 18 and capacitor contact plug 19. In some embodiments, isolation layer 22 may be disposed on isolation layer 20. In some embodiments, isolation layer 20 may surround capacitor contact pad 21. In some embodiments, isolation layer 22 and isolation layer 20 may surround capacitor 23. In some embodiments, each of isolation layer 20 and isolation layer 22 may include SiO2, Si3N4, N2OSi2, N2OSi2, etc., but is not limited thereto.

[0124] In some embodiments, capacitor 23 may be electrically connected to diffusion region 10a (e.g., a source junction or a drain junction of a corresponding transistor) via capacitor contact plug 19. In some embodiments, capacitor 23 may include a lower electrode 23a, an isolation layer 23b, and an upper electrode 23c.

[0125] In some embodiments, the lower electrode 23a and the upper electrode 23c may comprise doped polycrystalline silicon or metal. In some embodiments, the insulating layer 23b comprises Ta2O5, Al2O3, SrBi2Ta2O9 (SBT), BaSrTiO3 (BST), a dielectric material having a dielectric constant higher than that of SiO2, or a dielectric material having a dielectric constant of about 4.0 or greater.

[0126] In a comparative embodiment, sublayer 11b may be omitted, and conductive layer 12 may be separated from substrate 10 only by sublayer 11a.

[0127] As DRAM devices become more highly integrated, isolating an active word line (e.g., conductive layer 14) in a memory cell from a through word line (e.g., conductive layer 12) in an adjacent memory cell becomes more difficult. For example, when a through word line (e.g., conductive layer 12) is conducting, an inversion layer can be created, extending the source / drain junction and generating an internal electric field. Junction leakage current can be accelerated by trap-assisted tunneling, which is generated by the internal electric field.

[0128] By forming two dielectric layers (e.g., sublayer 11a and sublayer 11b) between conductive layer 12 and substrate 10, with a thicker layer of low-dielectric-constant dielectric material between conductive layer 12 and substrate 10, the internal electric field can be reduced, thereby reducing junction leakage current. Therefore, interference between multiple word lines (e.g., conductive layer 12 and conductive layer 14) in different memory cells of this disclosure can be avoided, and the charge written to the cell capacitor can be retained. In some embodiments, sublayer 11b, having a higher density than sublayer 11a, can further enhance the insulation between multiple word lines (e.g., conductive layer 12 and conductive layer 14) in different memory cells of this disclosure.

[0129] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K , Figure 2L , Figure 2M , Figure 2N , Figure 2O , Figure 2P , Figure 2Q , Figure 2R , Figure 2S , Figure 2T This is a cross-sectional schematic diagram illustrating multiple stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. To better understand various aspects of the present disclosure, at least some figures have been simplified. In some embodiments, in Figure 1 Semiconductor element 1 can be obtained by means of the steps described below and corresponding Figure 2A , Figure 2B , Figure 2C , Figure 2D, Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K , Figure 2L , Figure 2M , Figure 2N , Figure 2O , Figure 2P , Figure 2Q , Figure 2R , Figure 2S , Figure 2T To manufacture.

[0130] Please refer to Figure 2A A substrate 10 may be provided. A sublayer 11a may be disposed in the substrate 10. In some embodiments, the fabrication technique of the sublayer 11a may include trench etching, followed by filling the trench with a dielectric material. In some embodiments, the fabrication technique of the sublayer 11a may include a chemical vapor deposition (CVD) process.

[0131] In some embodiments, sublayer 11a may include a dielectric material with a low dielectric constant, such as FSG, OSG, CDO, porous silica, etc. In some embodiments, sublayer 11a may be a dielectric material having a dielectric constant lower than that of SiO2 or a dielectric material having a dielectric constant lower than about 4.0.

[0132] Please refer to Figure 2B A recess 11r may be formed in a sublayer 11a, and a recess 13r may be formed in a substrate 10. In some embodiments, the recess 11r and the recess 13r may be separated from each other. In some embodiments, the recess 11r and the recess 13r may be formed sequentially or simultaneously.

[0133] In some embodiments, the fabrication techniques for recesses 11r and 13r may include photolithography and etching techniques. In some embodiments, sublayer 11a and substrate 10 have different etching rates relative to an etchant. For example, the etching rate of sublayer 11a relative to an etchant may be greater than the etching rate of substrate 10. In some embodiments, a depth of recess 11r may be greater than a depth of recess 13r.

[0134] Please refer to Figure 2CA protective layer 24 may be disposed on the surface 101 of the substrate 10. The protective layer 24 may be disposed in recesses 11r and 13r. The protective layer 24 may fill recesses 11r and 13r. In some embodiments, the protective layer 24 and the substrate 10 have different etch rates relative to an etchant. In some embodiments, the protective layer 24 may exhibit etch characteristics different from those of the substrate 10. For example, the protective layer 24 may include a nitride or a photoresist.

[0135] Please refer to Figure 2D A photoresist 25 and a hard mask (not shown in the figures) may be provided on the protective layer 24. In some embodiments, the photoresist 25 may be patterned. In some embodiments, the photoresist 25 may be disposed on the recess 13r. In some embodiments, the photoresist 25 may not cover the recess 11r. In some embodiments, the photoresist 25 may not overlap with the recess 11r.

[0136] Please refer to Figure 2E A patternable protective layer 24 is provided. In some embodiments, the substrate 10 can remain unchanged when the protective layer 24 is patterned because the protective layer 24 corresponds to an etchant and has a different etch rate or exhibits different etch characteristics. After a portion of the protective layer 24 is removed, the sublayer 11a and the surface 11a1 can be exposed.

[0137] Please refer to Figure 2F Sublayer 11b may be disposed in the recess 11r and on sublayer 11a. In some embodiments, the fabrication technique of sublayer 11b may include a process different from that of sublayer 11a. In some embodiments, the fabrication technique of sublayer 11b may include an atomic layer deposition (ALD) process. In some embodiments, a density of sublayer 11b may be higher than a density of sublayer 11a. In some embodiments, sublayer 11b may include a dielectric material with a low dielectric constant, such as FSG, OSG, CDO, porous silica, etc. In some embodiments, sublayer 11b may be a dielectric material having a dielectric constant lower than that of SiO2, or a dielectric material having a dielectric constant lower than about 4.0. In some embodiments, sublayer 11b and sublayer 11a may have the same material.

[0138] Please refer to Figure 2G The photoresist 25 can be removed from the protective layer 24.

[0139] Please refer to Figure 2H For example, the protective layer 24 can be removed from the substrate 10 by a wet etching process or other suitable process. After removing the protective layer 24, the recess 13r can be exposed. In other words, the recess 13r can be removed after the sublayer 11b is disposed in the recess 11r and on the sublayer 11a.

[0140] Please refer to Figure 2I A dielectric layer 13 may be disposed in the recess 13r. In some embodiments, the fabrication technique of the dielectric layer 13 may include a process different from that of sublayer 11a or sublayer 11b. In some embodiments, the fabrication technique of the dielectric layer 13 may include a thermal oxidation step. In some embodiments, the density of the dielectric layer 13 may be higher than that of sublayer 13a and lower than that of sublayer 11b. In some embodiments, the dielectric layer 13 may include a dielectric material with a low dielectric constant, such as FSG, OSG, CDO, porous silica, etc. In some embodiments, the dielectric layer 13 may be a dielectric material having a dielectric constant lower than that of SiO2, or a dielectric material having a dielectric constant lower than about 4.0. In some embodiments, the dielectric layer 13, sublayer 11b, and sublayer 11a may have the same material.

[0141] In some embodiments, after a chemical mechanical polishing (CMP) process, the surfaces 11a1 of sublayer 11a, 11b1 of sublayer 11b, and / or 131 of dielectric layer 13 may be formed. In some embodiments, the surfaces 101 of substrate 10, 11a1 of sublayer 11a, 11b1 of sublayer 11b, and / or 131 of dielectric layer 13 may be substantially coplanar.

[0142] Please refer to Figure 2J The fabrication techniques for diffusion regions 10a and 10b may include doping with multiple impurities via ion implantation or thermal diffusion. In some embodiments, diffusion regions 10a and 10b may be formed on or near the surface 101 of the substrate 10. In some embodiments, diffusion regions 10a and 10b may be formed after other steps described herein. For example, diffusion regions 10a and 10b may be formed at... Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H It was formed after one of them.

[0143] Please refer to Figure 2K A conductive material 12m may be disposed on the substrate 10 to fill the recesses 11r and 13r. In some embodiments, for example, the fabrication technique of the conductive material 12m may include plating, electroless plating, printing, CVD or other suitable steps.

[0144] Please refer to Figure 2LA portion of the conductive material 12m can be removed by an etch-back process, such as a dry etching process using a silicon nitride film (not shown) as a mask. In some embodiments, after the etch-back process, the conductive layer 12 may be formed in the recess 11r, and the conductive layer 14 may be formed in the recess 13r. In some embodiments, after the etch-back process, the surface 121 of the conductive layer 12 may be separated from the surface 101 of the substrate 10. In some embodiments, after the etch-back process, the surface 141 of the conductive layer 14 may be separated from the surface 101 of the substrate 10.

[0145] Please refer to Figure 2M The isolation layer 15 may be disposed on the surface 121 of the conductive layer 12 and on the surface 141 of the conductive layer 14. In some embodiments, for example, the fabrication techniques of the isolation layer 15 may include ALD, CVD, physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), coating, etc.

[0146] Please refer to Figure 2N The patternable isolation layer 15 can define the location of the bit lines formed in the following steps.

[0147] Please refer to Figure 2O Bit lines 16 may be disposed on diffusion regions 10b. For example, a laminate 16b of a patternable W / WN film and polysilicon 16a may be used to form bit lines 16. In some embodiments, bit lines 16 may contact diffusion regions 10b. In some embodiments, bit lines 16 may be electrically connected to diffusion regions 10b.

[0148] Please refer to Figure 2P The isolation layer 17 can be disposed on the isolation layer 15 and the bit line 16. In some embodiments, for example, the fabrication technology of the isolation layer 17 may include ALD, CVD, PVD, RPCVD, PECVD, coating, etc.

[0149] Please refer to Figure 2Q An isolation layer 18 may be disposed on an isolation layer 17. In some embodiments, for example, the fabrication techniques of the isolation layer 18 may include ALD, CVD, PVD, RPCVD, PECVD, coating, etc.

[0150] Please refer to Figure 2R An opening 18r can be formed in the isolation layer 17 and the isolation layer 18 by means of photolithography and etching techniques. The diffusion region 10a can be exposed through the opening 18r.

[0151] Please refer to Figure 2SA conductive material may be formed in the opening 18r of the capacitor contact plug 19. The capacitor contact plug 19 may pass through the insulating layer 17 and the insulating layer 18. The manufacturing technology of the conductive material may include suitable techniques such as electroplating or an electroless coating process, CVD, PVD, etc.

[0152] Please refer to Figure 2T Similar steps can be repeated to form capacitor contact pad 21 and other conductive elements (if any) on capacitor contact plug 19. Isolation layers 20 and 22 may be disposed on isolation layer 18. An opening may be formed in isolation layers 20 and 22.

[0153] Capacitor 23 can be disposed in the opening defined by isolation layer 20 and isolation layer 22. For example, the electrode material of the lower electrode 23a can be disposed in the opening by means of, for example, plating, electroless plating, printing, CVD or other suitable steps. The isolation material of isolation layer 23b can be disposed on the inner side of the lower electrode 23a by, for example, CVD. The electrode material of the upper electrode 23c can be disposed in the opening by means of, for example, plating, electroless plating, printing, CVD or other suitable steps.

[0154] In some embodiments, after the capacitor 23 is formed, a wiring layer (not shown) may be formed on the capacitor 23. For example, the wiring layer may have a multilayer wiring structure, which includes multiple wiring layers and interlayer isolation films.

[0155] Figure 3 This is a flowchart illustrating a method 30 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0156] In some embodiments, the fabrication method 30 may include a step S31, forming a first recess in a first dielectric layer in a substrate. For example, such as Figure 2B As shown, the recess 11r can be formed in the sublayer 11a in the substrate 10.

[0157] In some embodiments, the preparation method 30 may include a step S32, forming a second recessed portion to be spaced apart from the first recessed portion and in the substrate. For example, such as Figure 2B As shown, the recess 13r may be formed in the substrate 10. The recess 13r is separated from the recess 11r.

[0158] In some embodiments, the preparation method 30 may include a step S33, which involves depositing a protective layer on the substrate to cover the second recess. For example, such as Figure 2C As shown, the protective layer 24 can be disposed on the substrate 10 to cover the recess 13r.

[0159] In some embodiments, the fabrication method 30 may include a step S34, which involves depositing a second dielectric layer on the first dielectric layer. For example, such as Figure 2F As shown, sublayer 11b can be set on sublayer 11a.

[0160] In some embodiments, the preparation method 30 may include a step S35, removing the protective layer to expose the second recess. For example, such as Figure 2H As shown, the protective layer 24 can be removed from the substrate 10, and the recess 13r can be exposed.

[0161] In some embodiments, the fabrication method 30 may include a step S36, which involves depositing a third dielectric layer in the second recess. For example, such as Figure 2I As shown, the dielectric layer 13 can be disposed in the recess 13r.

[0162] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface; and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

[0163] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface; a first dielectric layer extending from the surface of the substrate into the substrate; and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer. The semiconductor device also includes a second dielectric layer extending from the surface of the substrate into the substrate; and a second conductive layer disposed in the substrate and separated from the substrate by the second dielectric layer. The first dielectric layer and the second dielectric layer have different thicknesses.

[0164] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first recess in a first dielectric layer within a substrate; and forming a second recess spaced apart from the first recess and within the substrate. The fabrication method also includes disposing a protective layer on the substrate to cover the second recess; and disposing a second dielectric layer on the first dielectric layer.

[0165] By forming two dielectric layers between the conductive layer and the substrate, the effective electric field can be reduced, thereby reducing the junction leakage current. Therefore, interference between multiple word lines in different memory cells can be avoided, and the charge written to the cell capacitor can be retained.

[0166] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0167] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A substrate having a surface; A first dielectric layer extends from the surface of the substrate into the substrate; A second dielectric layer is disposed on the first dielectric layer and extends from the surface of the substrate into the substrate; A first conductive layer is disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer; as well as A second conductive layer is disposed in the substrate and separated from the substrate by a third dielectric layer; The density of the third dielectric layer is lower than that of the second dielectric layer, but higher than that of the first dielectric layer.

2. The semiconductor device of claim 1, wherein the second dielectric layer is disposed between the first dielectric layer and the first conductive layer.

3. The semiconductor device of claim 1, wherein the first conductive layer includes a through word line and the second conductive layer includes an active word line, the first conductive layer and the second conductive layer being configured to locate the addresses of different memory cells.

4. The semiconductor device of claim 1, wherein the first conductive layer and the second conductive layer are configured to receive different voltages.

5. The semiconductor device of claim 1, wherein the first dielectric layer includes a first upper surface that is substantially coplanar with the surface of the substrate.

6. The semiconductor device of claim 1, wherein the second dielectric layer includes a second upper surface that is substantially coplanar with the surface of the substrate.

7. The semiconductor device of claim 1, wherein the first conductive layer includes a surface that is separated from the surface of the substrate.

8. The semiconductor device of claim 7, further comprising an isolation layer disposed on the surface of the first conductive layer, wherein the isolation layer is separated from the substrate by the first dielectric layer and the second dielectric layer, and the isolation layer contacts the first dielectric layer and the second dielectric layer.

9. A semiconductor element, comprising: A substrate having a surface; A first dielectric layer extends from the surface of the substrate into the substrate; A first conductive layer is disposed in the substrate and separated from the substrate by the first dielectric layer; A second dielectric layer extends from the surface of the substrate into the substrate; as well as A second conductive layer is disposed in the substrate and separated from the substrate by the second dielectric layer; The first dielectric layer and the second dielectric layer have different thicknesses; The first dielectric layer includes a first sub-layer and a second sub-layer, wherein the second sub-layer is disposed between the first sub-layer and the first conductive layer; The density of the second dielectric layer is lower than that of the second sublayer but higher than that of the first sublayer, and the upper surfaces of the first sublayer and the second sublayer are approximately coplanar.

10. The semiconductor device of claim 9, wherein the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

11. The semiconductor device of claim 9, wherein the first conductive layer includes a through word line and the second conductive layer includes an active word line, and the first conductive layer and the second conductive layer are configured to locate the addresses of different memory cells.

12. The semiconductor element of claim 9, wherein the first conductive layer and the second conductive layer are configured to receive different voltages.

13. A method for fabricating a semiconductor device, comprising: A first recess is formed in a first dielectric layer in a substrate; A second recess is formed to separate it from the first recess and within the substrate; A protective layer is provided on the substrate to cover the second recess; A second dielectric layer is disposed on the first dielectric layer; Remove the protective layer to expose the second recess; and A third dielectric layer is disposed in the second recess.

14. The preparation method of claim 13, wherein the first recess is deeper than the second recess.

15. The preparation method of claim 13, wherein the first dielectric layer is formed by a chemical vapor deposition process.

16. The preparation method of claim 13, wherein the second dielectric layer is formed by an atomic layer deposition process.

17. The preparation method of claim 13, wherein the third dielectric layer is formed by a thermal oxidation process.

18. The preparation method of claim 13, further comprising forming a first conductive layer on the second dielectric layer, wherein the first conductive layer is separated from the substrate by the first dielectric layer and the second dielectric layer.

19. The preparation method of claim 18, further comprising forming a second conductive layer on the third dielectric layer, wherein the second conductive layer is separated from the substrate by the third dielectric layer.

20. The fabrication method of claim 19, wherein the first conductive layer and the second conductive layer comprise a plurality of word lines and are configured to locate the addresses of different memory cells.

21. The preparation method of claim 13, wherein the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

22. The preparation method of claim 19, wherein the first dielectric layer comprises a first sublayer and a second sublayer, the second sublayer being disposed between the first sublayer and the first conductive layer.

23. The preparation method of claim 22, wherein a density of the second sublayer is different from a density of the first sublayer.

24. The preparation method according to claim 22, wherein the density of the second sublayer is greater than the density of the first sublayer.

25. The preparation method of claim 22, wherein the density of the second dielectric layer is lower than the density of the second sublayer and higher than the density of the first sublayer.

26. The preparation method of claim 22, wherein an upper surface of the first sublayer and an upper surface of the second sublayer are substantially coplanar.

27. The preparation method of claim 22, wherein the first conductive layer includes a through character line, and the second conductive layer includes an active character line.

28. The preparation method of claim 22, wherein the first conductive layer and the second conductive layer are configured to receive different voltages.

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