A high-symmetry ultra-wideband gallium nitride power amplifier power combining network

Abstract

The application discloses a high-symmetry ultra-wideband gallium nitride power amplifier power combination network, which is applied to the field of monolithic microwave integrated circuits and aims at the problem that, in the Ku wave band, the long secondary power combination transmission line seriously deteriorates the high-frequency characteristics of the existing tree-shaped power combination network and cannot meet the high-frequency and ultra-wideband requirements; the power combination network transistor of the application adopts X-shaped layout, so that the power combination network structure is axially symmetrical in the horizontal direction and the vertical direction and is centrally symmetrical relative to the secondary power combination point, the symmetry and the large-signal even-mode stability of the power combination network are improved, and the heat dissipation of the chip is facilitated, and the thermal stability is improved; the application also utilizes a two-order L-C low-pass matching network to make impedance transformation in the ultra-wideband be located in the low-Q value area of a Smith chart, and the high-frequency bandwidth and the insertion loss are further improved.

Description

Technical Field

[0001] This invention belongs to the field of monolithic microwave integrated circuits, and specifically relates to a novel power combining output network. Background Technology

[0002] Gallium nitride (GaN) is a third-generation semiconductor material, belonging to the wide-bandgap semiconductor category. It features a large bandgap, high breakdown field strength, and high carrier concentration, making it a crucial material for developing power semiconductor devices. The core active device in monolithic microwave integrated circuits is the GaN high-electron-mobility transistor (HEMT). HEMTs are based on the conduction band discontinuity and polarization effect of AlGaN and GaN, forming a heterojunction at their interface. This creates a potential well in the conduction band that restricts electron distribution, thereby constructing a two-dimensional electron gas channel on the undoped GaN side. This channel exhibits high electron mobility and fast electron saturation velocity, along with high breakdown voltage and high thermal conductivity, meeting the requirements for high-frequency, high-voltage, high-current, and high-temperature operation. It is currently the main process technology for high-power amplifier chips.

[0003] Power amplifier chips are the core components of RF front-end transmitting systems and have a decisive impact on the overall system performance. The core indicators of RF power amplifier chips are operating bandwidth, output power (Pout), and power added efficiency (PAE). Power added efficiency characterizes the amplifier's actual amplification capability for small signals, as shown in Equation (1).

[0004]

[0005] Where Pout is the output power (in watts), Pin is the input power (in watts), VDD is the transistor drain feed voltage (in volts), and IDD is the transistor drain dynamic current (in amperes).

[0006] Due to the relatively high cost of silicon carbide substrates and gallium nitride epitaxy, gallium nitride monolithic microwave integrated circuit power amplifiers (MMIC PAs) are mainly used in military fields, such as electronic warfare and radar systems. In such applications, in addition to the requirements of high power and high efficiency mentioned above, a large bandwidth is also required. Only with a sufficiently large bandwidth can spectrum resources be used efficiently, ensuring the security of our electromagnetic space while effectively tracking and locating enemy targets to achieve precision strikes. The bandwidth characteristic is generally described by the relative bandwidth ΔBW, which is the ratio of the effective bandwidth of the signal to the center frequency, as shown in equation (2). In practical applications, ultra-wideband generally refers to a relative bandwidth greater than 100%.

[0007]

[0008] Among them, f H For the highest effective operating frequency, f L For the lowest effective operating frequency, f C The center frequency of the effective bandwidth.

[0009] The widest possible operating bandwidth, the highest possible output power, and the highest possible power-added efficiency are the relentless pursuits in GaN microwave power amplifier chip design. The core work of MMIC chip design is impedance matching circuit design; transistors cannot function properly without impedance matching. A block diagram of transistor impedance matching is shown below. Figure 1 As shown. The input matching network loss is ILiN (dB), and the effective input power of the transistor gate after the input power Pin (dBm) passes through the input matching network is Pa_in (dBm); the output matching network loss is ILiout (dB), and the effective output power of the transistor drain output power Pa_out (dBm) after passing through the output matching network is Pout (dBm). Figures 2 to 4 The effects of output matching network loss on output power, power-added efficiency, and link gain Gp are presented respectively. Figures 5 to 7 The effects of input matched network loss on output power, power-added efficiency, and link gain Gp are presented separately. Figure 2 and Figure 3As can be seen, under the conditions of stable transistor output power and the same link gain, as the output matching network loss increases, the link output power and power-added efficiency decrease significantly, and the higher the transistor output power, the greater the output power loss due to the same loss. However, the degree of power-added efficiency degradation caused by input matching network loss is far less than the impact of output matching network loss under the same loss value. The above analysis shows that the final-stage output matching network of GaN MMIC PA has the most significant impact on the overall circuit performance. Improving the matching characteristics of the final-stage output matching network and reducing its insertion loss are the design focus of GaN power amplifier chips. Figure 1 In this context, Ga_p represents the transistor gain; Figure 3 In this context, PAE represents Power Added Efficiency.

[0010] In the design of the final stage output matching network of GaN MMIC PA, a tree-shaped power combining network is mainly used to synchronously realize the power combining and output impedance matching of multiple parallel transistors. A typical circuit schematic is shown below. Figure 8 As shown, the corresponding map diagram is as follows: Figure 9 As shown.

[0011] In this circuit, the gates of all transistors are parallel to the chip's input-output direction, and the dies are arranged vertically. The sources of all transistors are connected to ground, and the gates of all transistors are connected to the input signal. The first-stage power combining transmission line TL0_1 is connected between the drain d1 of transistor M1 and the first-stage power combining point a1; TL0_2 is connected between the drain d2 of transistor M2 and the first-stage power combining point a1; TL0_3 is connected between the drain d3 of transistor M3 and the first-stage power combining point a2; and TL0_4 is connected between the drain d4 of transistor M4 and the first-stage power combining point a2. The second-stage power combining transmission line consists of TL1_1 and TL2_1. TL1_1 is connected between the first-stage power combining point a1 and the common feed terminal b1, and TL2_1 is connected between the common feed terminal b1 and the second-stage power combining point c. The CHOKE_1 inductor is connected to the drain power pad, and the grounding capacitor Cbp_1 is connected between the drain power pad and the ground via to filter the power signal. The drain voltages of M1 and M2 are input from the common feed terminal b1 through CHOKE_1. The secondary power combining transmission line consists of TL1_2 and TL2_2. TL1_2 is connected between the primary power combining point a2 and the common feed terminal b2, and TL2_2 is connected between the common feed terminal b2 and the secondary power combining point c. The CHOKE_2 inductor is connected to the drain power pad, and the grounding capacitor Cbp_2 is connected between the drain power pad and the ground via to filter the power signal. The drain voltages of M3 and M4 are input from the common feed terminal b2 through CHOKE_2. The secondary power combining transmission line TL2_1 is connected between the common feed terminal b1 and the secondary power combining point c, and the secondary power combining transmission line TL2_2 is connected between the common feed terminal b2 and the secondary power combining point c. Transmission line TL3 connects points c and d, and capacitor C1 connects point d to the ground hole. Transmission line TL4 connects points d and e, and capacitor C2 connects point e to the ground hole. Capacitor C3 connects point e to the output port. To extend bandwidth, a shorting line TL5 is introduced at the output, therefore the output does not have DC blocking capability. An additional high-power capacitor needs to be connected in series, increasing the complexity and component area.

[0012] Transistors M1, M2, M3, and M4 are identical in specifications; inductors CHOKE_1 and CHOKE_2 are identical in specifications; capacitors Cbp_1 and Cbp_2 are identical in specifications; transmission lines TL0_1, TL0_2, TL0_3, and TL0_4 are identical in specifications; transmission lines TL1_1 and TL1_2 are identical in specifications; and transmission lines TL2_1 and TL2_2 are identical in specifications. This structure makes the circuit horizontally axially symmetrical. This symmetry is the main method to eliminate even-mode oscillations in power amplifier circuits, thus improving their large-signal stability. Because transistors dissipate a lot of heat when outputting high power, the transistors are spaced apart to avoid concentrated heat and burnout.

[0013] The biggest drawback of this circuit is the relatively long length of the secondary power combining transmission lines TL2_1 and TL2_2, resulting from the transistor tree arrangement; otherwise, it would be impossible to connect the two symmetrical circuit sections. In designs below the X-band, the length of TL2_1 and TL2_2 has little impact on performance. However, in the Ku-band, the excessively long TL2_1 and TL2_2 severely degrade the high-frequency characteristics of this power combining network, failing to meet the requirements of high frequency and ultra-wideband. Summary of the Invention

[0014] To address the aforementioned technical problems, this invention proposes a high-symmetry ultrawideband gallium nitride power amplifier power combining network. It employs an X-shaped power combining network structure, which is axially symmetric in both the horizontal and vertical directions and centrally symmetric with respect to the second-level power combining point. This improves the symmetry of the power combining network and the stability of large-signal even modes, and also facilitates chip heat dissipation, thus enhancing thermal stability.

[0015] The technical solution adopted in this invention is as follows: a power combining network for a high-symmetry ultrawideband gallium nitride power amplifier, comprising four transistors, four inductors, four grounding capacitors, four first-stage power combining transmission lines, and two second-stage power combining transmission lines; the gate direction of the four transistors is perpendicular to the chip input-output direction, and the transistor dies are arranged laterally;

[0016] The drain of the first transistor is connected to the first terminal of the first grounding capacitor via the first inductor. The second terminal of the first grounding capacitor is grounded. The first terminal of the first grounding capacitor is also connected to the power supply. The source of the first transistor is grounded. The gate of the first transistor is connected to the input signal.

[0017] The drain of the second transistor is connected to the first terminal of the second grounding capacitor via the second inductor. The second terminal of the second grounding capacitor is grounded, and the first terminal of the second grounding capacitor is also connected to the power supply. The source of the second transistor is grounded, and the gate of the second transistor is connected to the input signal.

[0018] The drain of the third transistor is connected to the first terminal of the third grounding capacitor via the third inductor. The second terminal of the third grounding capacitor is grounded. The first terminal of the third grounding capacitor is also connected to the power supply. The source of the third transistor is grounded. The gate of the third transistor is connected to the input signal.

[0019] The drain of the fourth transistor is connected to the first terminal of the fourth grounding capacitor via the fourth inductor. The second terminal of the fourth grounding capacitor is grounded. The first terminal of the fourth grounding capacitor is also connected to the power supply. The source of the fourth transistor is grounded. The gate of the fourth transistor is connected to the input signal.

[0020] The first stage power combining transmission line is connected between the drain of the first transistor and the first stage power combining point; the second stage power combining transmission line is connected between the drain of the second transistor and the first stage power combining point; the third stage power combining transmission line is connected between the drain of the third transistor and the second stage power combining point; the fourth stage power combining transmission line is connected between the drain of the fourth transistor and the second stage power combining point.

[0021] The first secondary power combining transmission line is connected between the first primary power combining point and the secondary power combining point, and the second secondary power combining transmission line is connected between the second primary power combining point and the secondary power combining point; the secondary power combining point is connected to the output terminal.

[0022] The secondary power combining point is connected to the output terminal through a first-order LC low-pass matching network and a second-order LC low-pass matching network.

[0023] The power supplies connected to the four grounding capacitors are independent of each other.

[0024] Transistors M1, M2, M3, and M4 have the same specifications; inductors CHOKE_1, CHOKE_2, CHOKE_3, and CHOKE_4 have the same specifications; capacitors Cbp_1, Cbp_2, Cbp_3, and Cbp_4 have the same specifications; transmission lines TL0_1, TL0_2, TL0_3, and TL0_4 have the same specifications; and transmission lines TL1_1 and TL1_2 have the same specifications.

[0025] The beneficial effects of this invention are as follows: Unlike traditional tree structures, the transistors in this invention adopt an X-shaped layout, breaking the length limitation of the secondary power combining transmission line in tree structures, significantly extending high-frequency characteristics, and utilizing a two-order LC low-pass matching network to ensure that impedance transformation is located in the low Q value region of the Smith chart throughout the ultra-wideband, further improving high-frequency bandwidth and insertion loss. This structure is axially symmetric both laterally and vertically, and is symmetrical with respect to the center of the secondary power combining point, improving the symmetry of the power combining network and the stability of large-signal even-mode operation, and facilitating chip heat dissipation, thus improving thermal stability. Each transistor drain allows for independent power supply, reducing voltage drop loss, increasing output voltage swing, and contributing to higher output power. The structure of this invention has the following advantages:

[0026] (1) The present invention adopts an X-shaped power combining network, which improves the circuit structure and layout structure, expands the high-frequency bandwidth in ultra-wideband matching, reduces insertion loss, and can improve the high-frequency output power and power-added efficiency of the power amplifier chip.

[0027] (2) The core circuit of the power combining network of the present invention is axially symmetrical in both the horizontal and vertical directions, and is symmetrical about the second-level power combining point. The high symmetry can improve the stability of the large signal even mode of the power amplifier chip.

[0028] (3) In this invention, each transistor is directly and independently powered at its own drain port, which improves the stability of the transistor, reduces voltage loss, and increases voltage swing, thereby improving the output power and power-added efficiency of the power amplifier chip.

[0029] (4) The present invention uses a two-order LC low-pass matching network, which can control the transformation trajectory of the output impedance in the circle diagram in the low Q value region, which is beneficial to ultra-wideband matching.

[0030] (5) The output terminal of this invention does not use a short-circuited microstrip line and integrates a series capacitor, so that the output terminal can realize the DC blocking function and simplify its use;

[0031] (6) In this invention, the transistors are more dispersed in the layout, which is beneficial to improving the chip's heat dissipation capacity and improving the chip's thermal stability. Attached Figure Description

[0032] Figure 1 This is a block diagram illustrating the principle of transistor impedance matching.

[0033] Figure 2 A schematic diagram illustrating the impact of output matching network loss on output power;

[0034] Figure 3 A schematic diagram illustrating the impact of output matching network loss on power-added efficiency;

[0035] Figure 4A schematic diagram illustrating the impact of matching network loss on link gain;

[0036] Figure 5 A schematic diagram illustrating the impact of input matching network loss on output power;

[0037] Figure 6 A schematic diagram illustrating the impact of input matching network loss on power-added efficiency;

[0038] Figure 7 A schematic diagram illustrating the impact of input matching network loss on link gain;

[0039] Figure 8 This is a schematic diagram of a traditional tree-shaped power combining network.

[0040] Figure 9 This is a schematic diagram of a traditional tree-shaped power combining network layout;

[0041] Figure 10 This is a schematic diagram of the X-shaped power combining network of the present invention;

[0042] Figure 11 This is a schematic diagram of the X-shaped power combining network layout of the present invention;

[0043] Figure 12 The transformation process of impedance in a traditional tree-shaped power synthesis network in a Smith diagram (TL2_1 and TL2_2, length 400μm);

[0044] Figure 13 The transformation process of the impedance of a traditional tree-shaped power synthesis network in the Smith diagram (TL2_1 and TL2_2 are 100μm in length);

[0045] Figure 14 This is a schematic diagram of the impedance transformation process of the X-shaped power combining network in the Smith chart according to the present invention;

[0046] Figure 15 This is a schematic diagram comparing the insertion loss of the present invention with that of the traditional structure;

[0047] Figure 16 This is a schematic diagram comparing the impedance matching of the present invention and the traditional structure in a Smith chart.

[0048] Figure 17 This is an example layout of a GaN high-frequency ultra-wideband power amplifier chip that applies the present invention;

[0049] Figure 18 Gain curve of an example GaN high-frequency ultra-wideband power amplifier chip applying the present invention;

[0050] Figure 19 The output power curve of an example GaN high-frequency ultra-wideband power amplifier chip applying the present invention is shown.

[0051] Figure 20 The power-added efficiency curve is shown for an example of a GaN high-frequency ultra-wideband power amplifier chip applying the present invention. Detailed Implementation

[0052] To facilitate understanding of the technical content of this invention by those skilled in the art, the following description, in conjunction with the accompanying drawings, further illustrates the invention.

[0053] Adopting such Figure 8 The traditional tree-structured power combining network shown matches the output stage over an ultra-wideband range. The function of the output power combining network is to match the system's 50-ohm impedance to the conjugate impedance Zopt* of the transistor's optimal power output impedance. Figure 12 and Figure 13 The impedance transformation results of the power combining network are presented for TL2_1 and TL2_2 lengths of 400μm and 100μm, respectively. When TL2_1 and TL2_2 are 400μm, the impedance Zb after TL2_1 has a Q value of 6 at 18GHz, which is much greater than the requirement of Q<1 for broadband matching. In subsequent transformations, the 18GHz impedance is always at the edge of the circle diagram, far from 50 ohms. However, if TL2_1 and TL2_2 are shortened to 100μm, the Q value of Zb at 18GHz is only 2. In subsequent transformations, the impedance Q value across the entire frequency band is even lower, and the high-frequency characteristics are significantly improved.

[0054] In practical engineering applications, due to limitations in transistor size, source-to-ground vias, and heat dissipation requirements, the lengths of TL2_1 and TL2_2 in this structure are often greater than 400μm. As the above analysis shows, this severely restricts high-frequency characteristics. Therefore, for high-frequency, ultra-wideband GaN power amplifier chips, reducing the loss of the output power combining network and expanding its high-frequency bandwidth has significant practical engineering implications.

[0055] Figure 10 This is a circuit diagram of the power combining network of the present invention. Figure 11This is a schematic diagram of the power combining network layout of this invention. The transistor gate direction is perpendicular to the chip input-output direction, and the dies are arranged laterally. The sources of all transistors are connected to ground, and the gates of all transistors are connected to the input signal. The drain d1 of transistor M1 is directly connected to the drain power pad via the CHOKE_1 inductor, and the grounding capacitor Cbp_1 is connected between the drain power pad and the ground via for filtering the power signal. The first-stage power combining transmission line TL0_1 is connected between the drain d1 of transistor M1 and the first-stage power combining point a1. The drain d2 of transistor M2 is directly connected to the drain power pad via the CHOKE_2 inductor, and the grounding capacitor Cbp_2 is connected between the drain power pad and the ground via for filtering the power signal. The first-stage power combining transmission line TL0_2 is connected between the drain d2 of transistor M2 and the first-stage power combining point a1. The drain d3 of transistor M3 is directly connected to the drain power pad via the CHOKE_3 inductor. The grounding capacitor Cbp_3 is connected between the drain power pad and the ground via for filtering the power signal. The first-stage power combining transmission line TL0_3 is connected between the drain d3 of transistor M3 and the first-stage power combining point a2. Similarly, the drain d4 of transistor M4 is directly connected to the drain power pad via the CHOKE_4 inductor. The grounding capacitor Cbp_4 is connected between the drain power pad and the ground via for filtering the power signal. The first-stage power combining transmission line TL0_4 is connected between the drain d4 of transistor M4 and the first-stage power combining point a2. The direct connection of each transistor's drain to the CHOKE inductor shortens the distance between the drain voltage and the transistor, resulting in lower voltage drop loss, improved output voltage swing, and increased output power. Furthermore, independent power supply reduces crosstalk between transistors, improving stability.

[0056] Secondary power combining transmission line TL1_1 is connected between primary power combining point a1 and secondary power combining point b, and secondary power combining transmission line TL1_2 is connected between primary power combining point a2 and secondary power combining point b. Capacitor C1 is connected between secondary power combining point b and ground via. Transmission line TL3 is connected between secondary power combining point b and point c, and capacitor C2 is connected between point c and ground via. Transmission line TL4 is connected between point c and point d, and capacitor C3 is connected between point d and ground via. Capacitor C4 is connected between point d and output port. In this invention, the lengths of secondary power combining transmission lines TL1_1 and TL1_2 are not limited by transistor layout, allowing for shorter lengths, from hundreds of micrometers to only tens of micrometers, breaking the lower limit of secondary power combining transmission line length in traditional tree structures and significantly improving high-frequency characteristics.

[0057] Transmission line TL3 and capacitor C2 form a first-order LC low-pass matching network, while transmission line TL4 and capacitor C3 form a second-order LC low-pass matching network, thus extending the effective bandwidth.

[0058] In this invention, transistors M1, M2, M3, and M4 have identical specifications; inductors CHOKE_1, CHOKE_2, CHOKE_3, and CHOKE_4 have identical specifications; capacitors Cbp_1, Cbp_2, Cbp_3, and Cbp_4 have identical specifications; transmission lines TL0_1, TL0_2, TL0_3, and TL0_4 have identical specifications; and transmission lines TL1_1 and TL1_2 have identical specifications. This structure ensures that the circuit is axially symmetrical both horizontally and vertically, and is symmetrical around the second-level power combining point b, forming an X-shaped layout. Compared to the traditional tree structure, this adds two dimensions of symmetry, improving the large-signal even-mode stability of the power amplifier chip. The more dispersed transistor distribution facilitates heat dissipation and improves the thermal stability of the power amplifier chip.

[0059] Using the present invention as follows Figure 10 The X-shaped power combining network shown also matches the output stage over the ultra-wideband range. Figure 14 The impedance distribution at different nodes of the X-shaped power combining network of this invention is shown in the Smith chart when the frequency freq is between 5-18 GHz, and the impedance range for Q=1 is also given. Figure 14 As can be seen, during the transformation process, most of the impedance across the entire frequency band at each node falls within the Q<1 region, resulting in a significant improvement in high-frequency characteristics. Figure 15 The insertion loss comparison results between the present invention and the traditional structure are presented. Figure 15 The middle horizontal axis represents the frequency freq, the left vertical axis represents the insertion loss S21 in the range of -20dB to 0dB, and the right vertical axis represents the insertion loss S21 in the range of -2dB to 0dB. Figure 16 The impedance matching results of the present invention and the conventional structure in the Smith chart are presented. Figure 16 Specifically, it provides the matching network port matching characteristic S22 when the frequency is between 5-18GHz. From Figure 15 , 16 As can be seen, the present invention has good matching in the entire frequency band from 5 to 18 GHz. In the frequency band above 10 GHz, the insertion loss of the X-shaped power combining network of the present invention is less than that of the traditional tree structure, while the insertion loss of the traditional tree structure increases sharply from 14 GHz and the matching deteriorates.

[0060] Compared with traditional structures, this invention has a wider high-frequency bandwidth, lower insertion loss, and significantly improved high-frequency characteristics.

[0061] For high-frequency, ultra-wideband GaN power amplifier chip applications, this invention designs a 12W ultra-wideband power amplifier chip with an operating frequency band covering the C-Ku band based on 0.25μm GaN HEMT technology. It employs a three-stage amplification structure, with the final stage using... Figure 10The X-shaped power combining network of this invention is shown. Specifically, it operates in the 4.5GHz-15.5GHz frequency band, achieving a relative bandwidth of 115%. The chip layout is shown below. Figure 17 As shown, the X-shaped power combining network of the present invention is as follows: Figure 17 The area shown in the box is labeled with the corresponding circuit structure. Figure 18 The small-signal gain and power gain curves of the chip are given. Figure 18 The horizontal axis represents frequency (freq), and the vertical axis represents small-signal gain (Gain) and power gain (Gp). Figure 19 The output power curve of the chip is given. Figure 19 The horizontal axis represents frequency freq, and the vertical axis represents saturated output power Psat. Figure 20 The power-added efficiency curve of the chip is given. Figure 20 The horizontal axis represents frequency (freq), and the vertical axis represents power-added efficiency (PAE). From Figure 18-20 As can be seen, in the 4.5GHz-15.5GHz frequency band, the chip has a power gain of 19dB, an output power of 12W, and a power-added efficiency of over 20%, which meets the requirements of ultra-wideband applications.

[0062] In summary, this invention discloses a high-symmetry ultrawideband gallium nitride (GaN) power amplifier power combining network. The transistors employ an X-shaped layout, breaking the length limitations of the second-stage power combining transmission lines in tree structures, significantly extending high-frequency characteristics. Furthermore, a second-order LC low-pass matching network ensures that the impedance transformation remains within the low-Q region of the Smith chart throughout the ultrawideband, further improving high-frequency bandwidth and insertion loss. This structure is axially symmetric both laterally and vertically, and is centrally symmetric with respect to the second-stage power combining point, improving the symmetry of the power combining network and the stability of large-signal even-mode operation, while also facilitating chip heat dissipation and enhancing thermal stability. Each transistor's drain can be independently powered, reducing voltage drop losses, increasing output voltage swing, and ultimately improving output power.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. The X-shaped high-symmetry ultrawideband power combining network described in this invention can be applied not only to gallium nitride power amplifier chips, but also to power amplifiers based on field-effect transistor principles such as gallium arsenide and indium phosphide, and can extend the application frequency band to the millimeter-wave band. Except for the C-Ku band GaN PA MMIC mentioned in the embodiments, all other types of processes and frequency bands mentioned above should be covered within the scope of the claims of this invention. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and should all be covered within the scope of the claims of this invention. Those skilled in the art will realize that the embodiments described herein are to help readers understand the principles of the present invention and should be understood as the scope of protection of the present invention not being limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the essence of the present invention, and these modifications and combinations are still within the scope of protection of the present invention.

Claims

1. A power combining network for a high-symmetry, ultra-wideband gallium nitride power amplifier, characterized in that, The power combining network is axially symmetric in both the horizontal and vertical directions, and is symmetrical about the second-level power combining point, forming an X-shaped layout; It includes four transistors, four inductors, four grounding capacitors, four first-stage power combining transmission lines, and two second-stage power combining transmission lines; the gate direction of the four transistors is perpendicular to the chip's input-output direction, and the transistor dies are arranged laterally; the power supplies connected to the four grounding capacitors are independent of each other; The drain of the first transistor is connected to the first terminal of the first grounding capacitor via the first inductor. The second terminal of the first grounding capacitor is grounded. The first terminal of the first grounding capacitor is also connected to the power supply. The source of the first transistor is grounded. The gate of the first transistor is connected to the input signal. The drain of the second transistor is connected to the first terminal of the second grounding capacitor via the second inductor. The second terminal of the second grounding capacitor is grounded, and the first terminal of the second grounding capacitor is also connected to the power supply. The source of the second transistor is grounded, and the gate of the second transistor is connected to the input signal. The drain of the third transistor is connected to the first terminal of the third grounding capacitor via the third inductor. The second terminal of the third grounding capacitor is grounded. The first terminal of the third grounding capacitor is also connected to the power supply. The source of the third transistor is grounded. The gate of the third transistor is connected to the input signal. The drain of the fourth transistor is connected to the first terminal of the fourth grounding capacitor via the fourth inductor. The second terminal of the fourth grounding capacitor is grounded. The first terminal of the fourth grounding capacitor is also connected to the power supply. The source of the fourth transistor is grounded. The gate of the fourth transistor is connected to the input signal. The first stage power combining transmission line is connected between the drain of the first transistor and the first stage power combining point; the second stage power combining transmission line is connected between the drain of the second transistor and the first stage power combining point; the third stage power combining transmission line is connected between the drain of the third transistor and the second stage power combining point; the fourth stage power combining transmission line is connected between the drain of the fourth transistor and the second stage power combining point. The first secondary power combining transmission line is connected between the first primary power combining point and the secondary power combining point, and the second secondary power combining transmission line is connected between the second primary power combining point and the secondary power combining point; the secondary power combining point is connected to the output terminal through the first-order LC low-pass matching network and the second-order LC low-pass matching network.

2. The high-symmetry ultrawideband gallium nitride power amplifier power combining network according to claim 1, characterized in that, The four transistors are identical, the four inductors are identical, the four grounding capacitors are identical, the four first-stage power combining transmission lines are identical, and the two second-stage power combining transmission lines are identical.

3. The high-symmetry ultrawideband gallium nitride power amplifier power combining network according to claim 2, characterized in that, The second-order LC low-pass matching network also includes a DC blocking capacitor between itself and the output.

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