Fin-shaped junction field-effect transistor, preparation method thereof, and chip

Abstract

The present application belongs to the field of semiconductor technology and provides a fin-shaped junction field-effect transistor and a preparation method and chip thereof. The present application forms an N-type drift layer on a semiconductor substrate, forms a connection region on the N-type drift layer, forms a P-type doped layer of a fin structure on both sides of the connection region, and sequentially forms a dielectric layer, a work function metal layer and a gate metal layer on the surface of the P-type doped layer. A first source doped layer and a second source doped layer are formed on the outer sides of the P-type doped layers on both sides, so that the current flowing out from the drain on the back side of the semiconductor substrate passes through the N-type drift layer and the connection region of the fin region, and reaches the source through the current channel induced by the first P-type doped layer and the second P-type doped layer structure of the fin structure. The device can be turned on by inducing a current channel by the gate metal layer on the fin structure, thereby achieving the purpose of taking into account high breakdown voltage, high current density and small device area.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a fin-junction field-effect transistor, a preparation method thereof, and a chip. Background Art

[0002] The breakdown voltage (BV) of a power transistor is a very important parameter. In order to increase the BV of a power transistor while saving chip area, the power transistor is transformed from a planar structure to a vertical structure.

[0003] However, the pursuit of high breakdown voltage, high current density and smaller device area is still the further development direction of power transistors. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application aim to provide a fin-junction field-effect transistor and a preparation method and chip thereof, which can simultaneously take into account high breakdown voltage, high current density and small device area.

[0005] According to a first aspect of an embodiment of the present application, a fin-junction field-effect transistor is provided. The fin-junction field-effect transistor includes:

[0006] semiconductor substrates;

[0007] An N-type drift layer is provided on the front surface of the semiconductor substrate;

[0008] A first P-type doping layer and a second P-type doping layer are provided on the N-type drift layer, and the first P-type doping layer and the second P-type doping layer are in a fin-shaped structure;

[0009] A first dielectric layer and a second dielectric layer are respectively provided on the surfaces of the first P-type doped layer and the second P-type doped layer;

[0010] A first work function metal layer and a second work function metal layer are respectively provided on the surfaces of the first dielectric layer and the second dielectric layer;

[0011] A first gate metal layer and a second gate metal layer are connected to the first work function metal layer and the second work function metal layer, respectively;

[0012] a connection region, provided between the first P-type doped layer and the second P-type doped layer;

[0013] A first source doping layer and a second source doping layer are respectively arranged on the outer side of the first P-type doping layer and the outer side of the second P-type doping layer;

[0014] The drain metal layer is arranged on the back side of the semiconductor substrate.

[0015] In one embodiment, the fin junction field effect transistor further comprises:

[0016] An insulating filling layer is filled on the first P-type doping layer and the second P-type doping layer to isolate the connection region, the first source doping layer and the second source doping layer.

[0017] In one embodiment, the first P-type doping layer and the second P-type doping layer are composed of a P-type doping region and a plurality of fin-shaped isolation structures, and the plurality of fin-shaped isolation structures are provided on the P-type doping region.

[0018] In one embodiment, the plurality of fin-shaped isolation structures in the first P-type doping layer and the plurality of fin-shaped isolation structures in the second P-type doping layer are arranged in a one-to-one correspondence.

[0019] In one embodiment, a concentration of P-type dopant ions in the fin isolation structure is less than a concentration of P-type dopant ions in the P-type doping region.

[0020] In one embodiment, the first gate metal layer and the second gate metal layer are disposed perpendicular to the fin-shaped isolation structure, and the widths of the first gate metal layer and the second gate metal layer are smaller than the length of the fin-shaped isolation structure.

[0021] In one embodiment, the first source doping layer is disposed on the P-type doping region and is in contact with the plurality of fin-shaped isolation structures; and / or

[0022] The second source doping layer is disposed on the P-type doping region and contacts the plurality of fin-shaped isolation structures.

[0023] In one embodiment, the first source doping layer and the second source doping layer are perpendicular to the fin isolation structure.

[0024] A second aspect of the present application further provides a method for preparing a fin junction field effect transistor, the method comprising:

[0025] forming an N-type drift layer on the front surface of the semiconductor substrate;

[0026] forming a first P-type doping layer and a second P-type doping layer on the N-type drift layer; wherein the first P-type doping layer and the second P-type doping layer are in a fin-shaped structure;

[0027] forming a first dielectric layer and a second dielectric layer on surfaces of the first P-type doped layer and the second P-type doped layer, respectively;

[0028] forming a first work function metal layer and a second work function metal layer on surfaces of the first dielectric layer and the second dielectric layer, respectively;

[0029] forming a connection region between the first P-type doping layer and the second P-type doping layer, and forming a first source doping layer and a second source doping layer on the outer sides of the first P-type doping layer and the outer sides of the second P-type doping layer, respectively;

[0030] Filling an insulating filling layer on the first P-type doping layer and the second P-type doping layer to isolate the connection region, the first source doping layer and the second source doping layer;

[0031] Filling an insulating filling layer on the first P-type doping layer and the second P-type doping layer to isolate the connection region, the first source doping layer and the second source doping layer;

[0032] A drain metal layer is formed on the back side of the semiconductor substrate.

[0033] A third aspect of the embodiments of the present application further provides a chip, wherein the chip integrates a fin junction field effect transistor as described in any one of the above items; or includes a fin junction field effect transistor prepared by the preparation method described in the above embodiments.

[0034] The beneficial effects of the embodiments of the present application compared with the prior art are: by forming an N-type drift layer on a semiconductor substrate, forming a connection area on the N-type drift layer, forming a P-type doped layer of a fin structure on both sides of the connection area, and sequentially forming a dielectric layer, a work function metal layer and a gate metal layer on the surface of the P-type doped layer, forming a first source doped layer and a second source doped layer on the outside of the P-type doped layers on both sides, so that the current flowing out from the drain on the back side of the semiconductor substrate passes through the N-type drift layer and the connection area of ​​the fin area, and reaches the source through the current channel induced by the first P-type doped layer and the second P-type doped layer structure of the fin structure. The device can be turned on by inducing a current channel by the gate metal layer on the fin structure, thereby achieving the purpose of taking into account high breakdown voltage, high current density and small device area. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic structural diagram of a fin junction field effect transistor provided by one embodiment of the present application;

[0036] Figure 2 yes Figure 1 A schematic cross-sectional view of the dashed line A;

[0037] Figure 3 yes Figure 1 A schematic cross-sectional view of the dashed line B;

[0038] Figure 4 It is a flow chart of a method for preparing a fin junction field effect transistor provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0040] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0041] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means one or more, unless otherwise specifically defined.

[0043] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," "in some other embodiments," "in a specific embodiment," and "in a specific application" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0044] The battery voltage (BV) of power transistors is a crucial parameter. To increase BV while saving chip area, power transistors have transitioned from a planar to a vertical structure. Since the invention of the fin transistor (FINFET), it has successfully demonstrated the feasibility of CMOS processes at 14nm and even 3-5nm processes.

[0045] In order to take into account high breakdown voltage, high current density and small device area, the embodiment of the present application provides a fin junction field effect transistor, combined with Figure 1 、 Figure 2 as well as Figure 3 As shown, the fin junction field effect transistor in this embodiment includes: a semiconductor substrate 100, an N-type drift layer 200, a first P-type doped layer 310, a second P-type doped layer 320, a first dielectric layer 410, a second dielectric layer 420, a first work function metal layer 510, a second work function metal layer 520, a first gate metal layer 710, a second gate metal layer 720, a connection area 830, a first source doped layer 810, a second source doped layer 820, and a drain metal layer 850.

[0046] In this embodiment, the N-type drift layer 200 is provided on the front surface of the semiconductor substrate 100, the first P-type doped layer 310 and the second P-type doped layer 320 are provided on the N-type drift layer 200, and the first P-type doped layer 310 and the second P-type doped layer 320 are in a fin-shaped structure, the first dielectric layer 410 and the second dielectric layer 420 are provided on the surface of the first P-type doped layer 310 and the second P-type doped layer 320, respectively, the first work function metal layer 510 and the second work function metal layer 520 are provided on the surface of the first dielectric layer 410 and the second dielectric layer 420, respectively, and the first gate The metal layer 710 and the second gate metal layer 720 are connected to the first work function metal layer 510 and the second work function metal layer 520 respectively. The connection area 830 is arranged between the first P-type doping layer 310 and the second P-type doping layer 320. The first source doping layer 810 and the second source doping layer 820 are arranged on the outside of the first P-type doping layer 310 and the second P-type doping layer 320 respectively. The first source doping layer 810 and the second source doping layer 820 are commonly connected to the source of the fin junction field effect transistor, and the drain metal layer 850 is arranged on the back side of the semiconductor substrate 100.

[0047] In this embodiment, an N-type drift layer 200 and a connection region 830 are formed on a semiconductor substrate 100, a first P-type doping layer 310 and a second P-type doping layer 320 of a fin-shaped structure are formed on both sides of the connection region 830, and a first dielectric layer 410, a first work function metal layer 510 and a first gate metal layer 710 are sequentially formed on the surface of the first P-type doping layer 310, a second dielectric layer 420, a second work function metal layer 520 and a second gate metal layer 720 are sequentially formed on the surface of the second P-type doping layer 320, and a first P-type doping layer 310, a second P-type doping layer 320, and a second P-type doping layer 310, a second P-type doping layer 320, a second P-type doping layer 320, a first P-type doping layer 310, a second P-type doping layer 320, a first P-type doping layer 310, a first ... A first source doping layer 810 and a second source doping layer 820 are formed on the outside of the doping layer 320, respectively, so that the current flowing out from the drain on the back side of the semiconductor substrate 100 passes through the N-type drift layer 200 and the connection area 830 of the fin region, and reaches the source through the current channel induced by the first P-type doping layer 310 and the second P-type doping layer 320 of the fin structure. The device can be turned on by inducing the current channel by the first gate metal layer 710 and the second gate metal layer 720 on the fin structure, thereby achieving the purpose of taking into account high breakdown voltage, high current density and smaller device area.

[0048] In one embodiment, the fin junction field effect transistor further includes an insulating filling layer.

[0049] Combine Figure 2 As shown, the first insulating filling layer 610 is filled on the first P-type doping layer 310 to isolate the connection region 830 from the first source doping layer 810 .

[0050] Combine Figure 3 As shown, the second insulating filling layer 620 is filled on the second P-type doping layer to isolate the connection region 830 from the second source doping layer 820 .

[0051] In one embodiment, combined Figure 2 and Figure 3 As shown, the first P-type doping layer 310 and the second P-type doping layer 320 are composed of a P-type doping region and a plurality of fin-shaped isolation structures, and the plurality of fin-shaped isolation structures are provided on the P-type doping region.

[0052] Specifically, the first P-type doping layer 310 includes a first P-type doping region 311 and a plurality of first fin-shaped isolation structures 312. The first P-type doping region 311 is horizontally arranged on the N-type drift layer 200. The plurality of first fin-shaped isolation structures 312 are arranged on the first P-type doping region 311 and in contact with the connection region 830 and the first source doping layer 810, so as to provide a plurality of current channels between the connection region 830 and the first source doping layer 810 when the device is turned on.

[0053] The second P-type doped layer 320 includes a second P-type doped region 321 and a plurality of second fin-shaped isolation structures 322. The second P-type doped region 321 is horizontally arranged on the N-type drift layer 200. The plurality of second fin-shaped isolation structures 322 are arranged on the second P-type doped region 321 and in contact with the connection region 830 and the second source doped layer 820, so as to provide a plurality of current channels between the connection region 830 and the second source doped layer 820 when the device is turned on.

[0054] In one embodiment, the first P-type doped layer 310 and the second P-type doped layer 320 are both made of P-type semiconductor materials, such as P-type silicon carbide, P-type silicon, or P-type gallium nitride.

[0055] In one embodiment, the semiconductor substrate 100 may be silicon carbide, silicon, or gallium nitride.

[0056] In one embodiment, the first dielectric layer 410 and the second dielectric layer 420 are both made of high dielectric materials.

[0057] In a specific embodiment, the dielectric constants of the first dielectric layer 410 and the second dielectric layer 420 are greater than 3.

[0058] In one embodiment, combined Figure 1 As shown, the multiple fin-shaped isolation structures in the first P-type doping layer 310 and the multiple fin-shaped isolation structures in the second P-type doping layer 320 are arranged in a one-to-one correspondence.

[0059] Specifically, the plurality of first fin-shaped isolation structures 312 and the plurality of second fin-shaped isolation structures 322 are arranged in a one-to-one correspondence, and ... Figure 1 As stated, Figure 1 The solid arrow in the figure represents the current path. After the first gate metal layer 710 and the second gate metal layer 720 on the fin structure induce a current channel, the current flows out from the drain on the back side of the semiconductor substrate 100, passes through the N-type drift layer 200 and the connection area 830 of the fin area, and reaches the source through the first P-type doped layer 310 and the second P-type doped layer 320 of the fin structure, achieving the purpose of taking into account high breakdown voltage, high current density and small device area.

[0060] In one embodiment, the gate metal layer can determine whether a current channel is induced in the device by being connected to the work function metal layer. Specifically, the first gate metal layer 710 is connected to the first work function metal layer 510, and the second gate metal layer 720 is connected to the second work function metal layer 520. When the voltage on the first gate metal layer 710 reaches the turn-on threshold voltage, a first current channel is induced at the interface between the first P-type doped layer 310 and the first dielectric layer 410. When the voltage on the second gate metal layer 720 reaches the turn-on threshold voltage, a second current channel is induced at the interface between the second P-type doped layer 320 and the second dielectric layer 420.

[0061] In a specific application embodiment, when the voltage on the first gate metal layer 710 and the second gate metal layer 720 reaches the turn-on threshold voltage, a current channel is induced in the first P-type doped layer 310 and the second P-type doped layer 320, and the device is turned on. When the voltage on the first gate metal layer 710 and the second gate metal layer 720 is lower than the turn-off threshold voltage, no current channel can be induced in the first P-type doped layer 310 and the second P-type doped layer 320, and the device is turned off.

[0062] In one embodiment, the device's withstand voltage can be increased by designing the thickness of the wafer, thereby cooperating with the switch of the fin junction field effect transistor and increasing the width of the device, such as Figure 1 The dotted arrow portion in FIG. achieves high current density and high breakdown voltage within the same chip area. Compared to conventional device designs, although the connection region 830 is added, as process evolution allows for the introduction of more high aspect ratio technologies, the fin junction field-effect transistor in this embodiment has significant development potential.

[0063] In one embodiment, the connection region 830 can be integrally formed with the N-type drift layer 200. For example, the connection region 830 is also an N-type semiconductor. The central protruding structure is retained by etching both sides of the N-type drift layer 200, and the protruding structure is used as the connection region 830. Then, a first P-type doped layer 310 and a second P-type doped layer 320 are formed on both sides of the connection region 830.

[0064] In one embodiment, the concentration of the P-type dopant ions in the fin isolation structure is less than the concentration of the P-type dopant ions in the P-type doping region.

[0065] In one embodiment, the first gate metal layer 710 and the second gate metal layer 720 are disposed perpendicular to the fin isolation structure, and the width of the first gate metal layer 710 and the second gate metal layer 720 is smaller than the length of the fin isolation structure.

[0066] In one embodiment, the first source doping layer 810 is disposed on the P-type doping region and is in contact with a plurality of fin-shaped isolation structures.

[0067] In this embodiment, the first source doping layer 810 and the multiple first fin isolation structures 312 are all arranged on the first P-type doping region 311, and the sum of the width of the first source doping layer 810 and the length of the first fin isolation structure 312 is equal to the length of the first P-type doping region 311.

[0068] In one embodiment, the second source doping layer 820 is disposed on the P-type doping region and is in contact with a plurality of fin-shaped isolation structures.

[0069] In this embodiment, the second source doping layer 820 and the plurality of second fin isolation structures 322 are both provided on the second P-type doping region 321 , and the sum of the width of the second source doping layer 820 and the length of the second fin isolation structure 322 is equal to the length of the second P-type doping region 321 .

[0070] In one embodiment, the first source doping layer 810 and the second source doping layer 820 are perpendicular to the fin isolation structure.

[0071] In this embodiment, the first source doping layer 810 is disposed perpendicular to the plurality of first fin isolation structures 312 , and the second source doping layer 820 is disposed perpendicular to the plurality of second fin isolation structures 322 .

[0072] In one embodiment, the first source doping layer 810 and the second source doping layer 820 are N-type semiconductors.

[0073] In one embodiment, the P-type semiconductor may be P-type silicon carbide, P-type silicon, or P-type gallium nitride, and the N-type semiconductor may be N-type silicon carbide, N-type silicon, or N-type gallium nitride.

[0074] The present invention also provides a method for preparing a fin-junction field effect transistor. Figure 1 As shown, the preparation method in this embodiment includes steps S10 to S70.

[0075] The following combination Figure 1 Steps S10 to S70 will be described.

[0076] In step S10 , an N-type drift layer 200 is formed on the front surface of the semiconductor substrate 100 .

[0077] Combine Figure 1 As described above, the N-type drift layer 200 is formed on the front surface of the semiconductor substrate 100 , and the semiconductor substrate 100 is an N-type semiconductor.

[0078] In one embodiment, the semiconductor substrate 100 may be silicon carbide, silicon, or gallium nitride.

[0079] In step S20 , a first P-type doping layer 310 and a second P-type doping layer 320 are formed on the N-type drift layer 200 .

[0080] In this embodiment, combined with Figure 1 As shown, the first P-type doped layer 310 and the second P-type doped layer 320 are in a fin-shaped structure.

[0081] In one embodiment, combined Figure 2 and Figure 3 As shown, the first P-type doping layer 310 and the second P-type doping layer 320 are composed of a P-type doping region and a plurality of fin-shaped isolation structures, and the plurality of fin-shaped isolation structures are provided on the P-type doping region.

[0082] Specifically, the first P-type doping layer 310 includes a first P-type doping region 311 and a plurality of first fin-shaped isolation structures 312. The first P-type doping region 311 is horizontally arranged on the N-type drift layer 200. The plurality of first fin-shaped isolation structures 312 are arranged on the first P-type doping region 311 and in contact with the connection region 830 and the first source doping layer 810, so as to provide a plurality of current channels between the connection region 830 and the first source doping layer 810 when the device is turned on.

[0083] The second P-type doped layer 320 includes a second P-type doped region 321 and a plurality of second fin-shaped isolation structures 322. The second P-type doped region 321 is horizontally arranged on the N-type drift layer 200. The plurality of second fin-shaped isolation structures 322 are arranged on the second P-type doped region 321 and in contact with the connection region 830 and the second source doped layer 820, so as to provide a plurality of current channels between the connection region 830 and the second source doped layer 820 when the device is turned on.

[0084] In one embodiment, combined Figure 1 As shown, the multiple fin-shaped isolation structures in the first P-type doping layer 310 and the multiple fin-shaped isolation structures in the second P-type doping layer 320 are arranged in a one-to-one correspondence.

[0085] Specifically, the plurality of first fin-shaped isolation structures 312 and the plurality of second fin-shaped isolation structures 322 are arranged in a one-to-one correspondence, and ... Figure 1 As stated, Figure 1 The solid arrow in the figure represents the current path. After the first gate metal layer 710 and the second gate metal layer 720 on the fin structure induce a current channel, the current flows out from the drain on the back side of the semiconductor substrate 100, passes through the N-type drift layer 200 and the connection area 830 of the fin area, and reaches the source through the first P-type doped layer 310 and the second P-type doped layer 320 of the fin structure, achieving the purpose of taking into account high breakdown voltage, high current density and small device area.

[0086] In one embodiment, the first P-type doped layer 310 and the second P-type doped layer 320 are both made of P-type semiconductor materials, such as P-type silicon carbide, P-type silicon, or P-type gallium nitride.

[0087] In step S30 , a first dielectric layer 410 and a second dielectric layer 420 are formed on the surfaces of the first P-type doping layer 310 and the second P-type doping layer 320 , respectively.

[0088] In step S40 , a first work function metal layer 510 and a second work function metal layer 520 are formed on the surfaces of the first dielectric layer 410 and the second dielectric layer 420 , respectively.

[0089] In one embodiment, the first dielectric layer 410 and the second dielectric layer 420 are both made of high dielectric materials.

[0090] In a specific embodiment, the dielectric constants of the first dielectric layer 410 and the second dielectric layer 420 are greater than 3.

[0091] In step S50 , a connection region 830 is formed between the first work function metal layer 510 and the second work function metal layer 520 , and a first P-type doping layer 310 and a second P-type doping layer 320 are formed outside the first P-type doping layer 310 and outside the second P-type doping layer 320 , respectively.

[0092] In one embodiment, both sides of the N-type drift layer 200 may be etched to retain a central protruding structure, with the protruding structure serving as the connection region 830 , and then a first P-type doped layer 310 and a second P-type doped layer 320 may be formed on both sides of the connection region 830 .

[0093] In step S60 , an insulating filling layer is filled on the first P-type doping layer 310 and the second P-type doping layer 320 to isolate the connection region 830 , the first source doping layer 810 and the second source doping layer 820 .

[0094] Combine Figure 2 As shown, the first insulating filling layer 610 is filled on the first P-type doping layer 310 to isolate the connection region 830 from the first source doping layer 810 .

[0095] Combine Figure 3 As shown, the second insulating filling layer 620 is filled on the second P-type doping layer to isolate the connection region 830 from the second source doping layer 820 .

[0096] In step S70 , a drain metal layer 850 is formed on the back surface of the semiconductor substrate 100 .

[0097] In one embodiment, the first source doping layer 810 and the second source doping layer 820 are connected to the source electrode of the device through a metal wire.

[0098] An embodiment of the present application further provides a chip, in which the fin junction field effect transistor as described in any of the above embodiments is integrated.

[0099] In one embodiment, the chip integrates a fin-shaped junction field effect transistor manufactured by the manufacturing method described in the above embodiment.

[0100] In this embodiment, the chip includes a chip substrate, on which one or more fin junction field effect transistors are arranged. The fin junction field effect transistor can be prepared by the preparation method in any of the above embodiments, or the fin junction field effect transistor in any of the above embodiments can be arranged on the chip substrate.

[0101] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit with the fin junction field effect transistor.

[0102] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0103] The beneficial effects of the embodiments of the present application compared with the prior art are: by forming an N-type drift layer on a semiconductor substrate, forming a connection area on the N-type drift layer, forming a P-type doped layer of a fin structure on both sides of the connection area, and sequentially forming a dielectric layer, a work function metal layer and a gate metal layer on the surface of the P-type doped layer, forming a first source doped layer and a second source doped layer on the outside of the P-type doped layers on both sides, so that the current flowing out from the drain on the back side of the semiconductor substrate passes through the N-type drift layer and the connection area of ​​the fin area, and reaches the source through the current channel induced by the first P-type doped layer and the second P-type doped layer structure of the fin structure. The device can be turned on by inducing a current channel by the gate metal layer on the fin structure, thereby achieving the purpose of taking into account high breakdown voltage, high current density and small device area.

[0104] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0105] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0106] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A fin junction field effect transistor, characterized in that: The fin junction field effect transistor comprises: semiconductor substrates; An N-type drift layer is provided on the front surface of the semiconductor substrate; A first P-type doping layer and a second P-type doping layer are provided on the N-type drift layer, and the first P-type doping layer and the second P-type doping layer are in a fin-shaped structure; A first dielectric layer and a second dielectric layer are respectively provided on surfaces of the first P-type doped layer and the second P-type doped layer; A first work function metal layer and a second work function metal layer are respectively provided on the surfaces of the first dielectric layer and the second dielectric layer; A first gate metal layer and a second gate metal layer are connected to the first work function metal layer and the second work function metal layer, respectively; a connection region, provided between the first P-type doped layer and the second P-type doped layer; A first source doping layer and a second source doping layer are respectively arranged on the outer side of the first P-type doping layer and the outer side of the second P-type doping layer; The drain metal layer is arranged on the back side of the semiconductor substrate.

2. The fin junction field effect transistor according to claim 1, wherein: The fin junction field effect transistor further comprises: An insulating filling layer is filled on the first P-type doping layer and the second P-type doping layer to isolate the connection region, the first source doping layer and the second source doping layer.

3. The fin junction field effect transistor according to claim 1, wherein: The first P-type doping layer and the second P-type doping layer are composed of a P-type doping region and a plurality of fin-shaped isolation structures, and the plurality of fin-shaped isolation structures are arranged on the P-type doping region.

4. The fin junction field effect transistor according to claim 3, wherein: The plurality of fin-shaped isolation structures in the first P-type doping layer and the plurality of fin-shaped isolation structures in the second P-type doping layer are arranged in a one-to-one correspondence.

5. The fin junction field effect transistor according to claim 3 or 4, wherein: The concentration of the P-type doping ions in the fin-shaped isolation structure is lower than the concentration of the P-type doping ions in the P-type doping region.

6. The fin junction field effect transistor according to claim 3 or 4, characterized in that: The first gate metal layer and the second gate metal layer are arranged perpendicular to the fin-shaped isolation structure, and the widths of the first gate metal layer and the second gate metal layer are smaller than the length of the fin-shaped isolation structure.

7. The fin junction field effect transistor according to claim 3 or 4, wherein: The first source doping layer is disposed on the P-type doping region and is in contact with the plurality of fin-shaped isolation structures; and / or The second source doping layer is disposed on the P-type doping region and contacts the plurality of fin-shaped isolation structures.

8. The fin junction field effect transistor according to claim 7, wherein: The first source doping layer and the second source doping layer are perpendicular to the fin-shaped isolation structure.

9. A method for preparing a fin-junction field-effect transistor, characterized in that: The preparation method comprises: forming an N-type drift layer on the front surface of the semiconductor substrate; forming a first P-type doping layer and a second P-type doping layer on the N-type drift layer; wherein the first P-type doping layer and the second P-type doping layer are in a fin-shaped structure; forming a first dielectric layer and a second dielectric layer on surfaces of the first P-type doped layer and the second P-type doped layer, respectively; forming a first work function metal layer and a second work function metal layer on surfaces of the first dielectric layer and the second dielectric layer, respectively; forming a connection region between the first P-type doping layer and the second P-type doping layer, and forming a first source doping layer and a second source doping layer on the outer sides of the first P-type doping layer and the outer sides of the second P-type doping layer, respectively; Filling an insulating filling layer on the first P-type doping layer and the second P-type doping layer to isolate the connection region, the first source doping layer and the second source doping layer; A drain metal layer is formed on the back side of the semiconductor substrate.

10. A chip, characterized in that: The chip integrates the fin junction field effect transistor according to any one of claims 1 to 8; or includes the fin junction field effect transistor prepared by the preparation method according to claim 9.

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