Nanoluminescent device and method of manufacturing the same

Abstract

The application relates to a nano light emitting device and a preparation method thereof. The preparation method comprises the following steps: providing an epitaxial wafer, forming a sacrifice layer on the epitaxial wafer, etching from top to bottom to form at least one nano pillar structure penetrating through the sacrifice layer, a first conductive layer, a first gallium nitride layer and a quantum well active layer of the gallium nitride stack, each nano pillar structure can be used as a pixel point of a nano light emitting device. After the nano pillar structure is filled with a silicon oxide layer, the sacrifice layer and part of the silicon oxide layer are removed, a first electrode is formed on the nano pillar structure and the gallium nitride stack, and a second electrode is formed on the gallium nitride stack. The nano light emitting device prepared by the method has a complete nano pillar structure shape, improved light emitting efficiency and light emitting performance, released stress, relieved polarization field influence caused by stress concentration, strengthened current limiting capacity in the nano scale in the vertical direction of electron transportation, and improved electro-optical conversion efficiency.

Description

Technical Field

[0001] This application relates to the field of micro-nano device manufacturing technology, and in particular to a nano-light-emitting device and its preparation method. Background Technology

[0002] With the continuous development of display technology, the market for small display devices such as Augmented Reality (AR) or Virtual Reality (VR) is expanding rapidly. These high-resolution, small-sized displays place higher technical demands on the structure and performance of the light-emitting units. Generally, display devices with light-emitting pixel sizes smaller than 1μm are defined as nano-LEDs. Based on gallium nitride, a third-generation semiconductor material, nano-LEDs possess advantages in material properties such as high saturated electron mobility, high thermal conductivity, and low dielectric constant. In terms of luminous performance, they offer advantages such as high luminous efficiency, low power consumption, fast response speed, and long lifespan.

[0003] The fabrication process of light-emitting diodes (LEDs) mainly includes epitaxial growth, photolithography, dry etching, wet etching, coating, and metal deposition. In actual fabrication, multiple overlay, etching, and coating steps are typically involved to achieve the desired performance indicators for the display device. Traditional fabrication processes face significant challenges in realizing LED devices at the hundred-nanometer scale. As the size of LED devices decreases, problems such as severe sidewall roughness, low processing precision, and low photoelectric conversion efficiency become increasingly prominent. Therefore, developing a technical method for manufacturing high-performance nanoscale light-emitting devices is one of the key technical challenges. Summary of the Invention

[0004] Therefore, it is necessary to provide a nano-light-emitting device and its preparation method to address the above-mentioned technical problems, which can effectively manufacture nano-light-emitting devices with good performance.

[0005] To achieve the above objectives, this application provides a method for fabricating a nano-light-emitting device. The method for fabricating the nano-light-emitting device includes:

[0006] An epitaxial wafer is provided, the epitaxial wafer comprising, from bottom to top, a substrate, a gallium nitride stack, a quantum well active layer, a first gallium nitride layer and a first conductive layer;

[0007] A sacrificial layer is formed on the first conductive layer;

[0008] The sacrificial layer, the first conductive layer, the first gallium nitride layer and the quantum well active layer are etched to form at least one nanopillar structure on the gallium nitride stack;

[0009] Wet etching was used to remove impurity particles from the periphery of the nanopillar structure;

[0010] A silicon oxide layer is formed on the gallium nitride stack and the nanopillar structure;

[0011] Remove the sacrificial layer and part of the silicon oxide layer to expose the first conductive layer of the nanopillar structure;

[0012] A first electrode is formed on the nanopillar structure and the silicon oxide layer, and the first electrode is disposed in contact with the first conductive layer;

[0013] A second electrode is formed on the gallium nitride stack, and the second electrode is spaced apart from the nanopillar structure and the silicon oxide layer.

[0014] In one embodiment, the etching of the sacrificial layer, the first conductive layer, the first gallium nitride layer, and the quantum well active layer to form at least one nanopillar structure on the gallium nitride stack includes:

[0015] Focused ion beam etching is used to etch the sacrificial layer, the first conductive layer, the first gallium nitride layer and the quantum well active layer to form at least one nanopillar structure on the gallium nitride stack.

[0016] In one embodiment, forming a silicon oxide layer on the gallium nitride stack and the nanopillar structure includes:

[0017] The nano-light-emitting device with the nanopillar structure is placed in a first solution and ultrasonically treated to form chemical bridging bonds on the surfaces of the gallium nitride stack and the nanopillar structure; wherein, the first solution includes toluene, 3-aminopropyltriethoxysilane and water;

[0018] The nano-light-emitting device with the chemically bridged bonds on its surface is placed in a second solution and subjected to low-pressure treatment, and after being left to stand in air, the silicon oxide layer is formed on the gallium nitride stack and the nanopillar structure; wherein the second solution includes the toluene, anhydrous ethanol and ammonia.

[0019] In one embodiment, the wet etching process for removing impurity particles from the periphery of the nanopillar structure includes:

[0020] Under a preset temperature environment, impurity particles on the periphery of the nanopillar structure are removed by wet etching using potassium hydroxide solution.

[0021] In one embodiment, forming a second electrode on the gallium nitride stack includes:

[0022] A photoresist layer is formed on the first electrode;

[0023] The photoresist layer is patterned, and the first electrode and the silicon oxide layer are etched to form an electrode contact window on the gallium nitride stack.

[0024] A second electrode is formed by filling the electrode contact window with conductive material;

[0025] Remove the photoresist layer.

[0026] On the other hand, this application also provides a nano-light-emitting device. The nano-light-emitting device includes:

[0027] Substrate;

[0028] A gallium nitride stack is located on the substrate;

[0029] At least one nanopillar structure, the nanopillar structure comprising, from bottom to top, a quantum well active layer, a first gallium nitride layer and a first conductive layer; wherein, the quantum well active layer is located on the gallium nitride stack;

[0030] A silicon oxide layer is located on the gallium nitride stack and is in contact with the nanopillar structure, and the upper surface of the silicon oxide layer is flush with the upper surface of the nanopillar structure.

[0031] The first electrode is located on the nanopillar structure and the silicon oxide layer, and is in contact with the first conductive layer;

[0032] The second electrode is located on the gallium nitride stack and is spaced apart from the nanopillar structure and the silicon oxide layer, respectively.

[0033] In one embodiment, the nano-light-emitting device includes a plurality of nanopillar structures arranged in an array, the nanopillar structures being spaced apart, and a silicon oxide layer being disposed between two adjacent nanopillar structures.

[0034] In one embodiment, the height of each nanopillar structure is 1.5μm-2.5μm, the diameter of each nanopillar structure is 100nm-1000nm, and the spacing between two adjacent nanopillar structures is 100nm-5μm.

[0035] In one embodiment, the active layer of the quantum well is a gallium nitride layer doped with indium atoms; wherein the doping ratio of indium atoms in the active layer of the quantum well is related to the emission wavelength of the nano-light-emitting device.

[0036] In one embodiment, the gallium nitride stack includes a second gallium nitride layer and a third gallium nitride layer disposed sequentially from bottom to top; wherein the second electrode is located on the third gallium nitride layer, and the conductivity type of the third gallium nitride layer is different from that of the first gallium nitride layer.

[0037] The nano-light-emitting device and its fabrication method provided in the above embodiments include an epitaxial wafer. After forming a sacrificial layer on the first conductive layer of the epitaxial wafer, at least one nanopillar structure is etched from top to bottom, penetrating the sacrificial layer, the first conductive layer, the first gallium nitride layer, the quantum well active layer, and extending to the gallium nitride stack. This ensures the integrity of the nanopillar structure of the nano-light-emitting device, and each nanopillar structure can serve as a pixel of a nano-LED. Then, wet etching is used to remove impurity particles around the nanopillar structure, avoiding the influence of impurity particles on the nano-light-emitting device and improving the light-emitting performance of the nano-light-emitting device. Next, a silicon oxide layer is formed on the gallium nitride stack and the nanopillar structure, and then the sacrificial layer is removed. The nano-LED is fabricated by forming a first conductive layer on the nanopillar structure and a partial silicon oxide layer to expose the first conductive layer. A first electrode is formed on the nanopillar structure and the silicon oxide layer, and the first electrode is in contact with the first conductive layer. A second electrode is formed on the gallium nitride stack, and the second electrode is spaced apart from the nanopillar structure and the silicon oxide layer. The nano-LED fabricated in this way has a complete nanopillar structure shape, which improves the light extraction efficiency and light emission performance of the nano-LED device. It also releases stress to a greater extent in the nanoscale processing technology, alleviates the polarization field effect caused by stress concentration, and strengthens the current confinement capability at the nanoscale during electron transport in the vertical direction, resulting in higher electro-optic conversion efficiency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic flowchart of a method for fabricating a nano-light-emitting device provided in one embodiment;

[0040] Figures 2a to 2h This is a schematic cross-sectional view of the structure obtained in steps S11 to S18 of the fabrication method of the nano-light-emitting device provided in one embodiment.

[0041] Figure 3a This is a schematic diagram of the cross-sectional structure of an epitaxial wafer provided in one embodiment;

[0042] Figure 3b Provided in one embodiment Figure 3a A schematic diagram of the cross-sectional structure of the structure obtained by forming a sacrificial layer on the epitaxial wafer;

[0043] Figure 4aThis is a schematic cross-sectional view of the structure obtained in step S13 of the fabrication method of the nano-light-emitting device provided in one embodiment;

[0044] Figure 4b This is a top view of a structure for removing impurity particles from the periphery of a nanopillar structure, as provided in one embodiment.

[0045] Figure 4c Provided in one embodiment Figure 4a A schematic diagram of the cross-sectional structure of the structure obtained after removing impurity particles from the periphery of the medium-nano pillar structure;

[0046] Figure 4d Provided in one embodiment Figure 4c A top view of the structure shown;

[0047] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S15 of the fabrication method of the nano-light-emitting device provided in one embodiment;

[0048] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S161 of the fabrication method of the nano-light-emitting device provided in one embodiment;

[0049] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S171 of the fabrication method of the nano-light-emitting device provided in one embodiment;

[0050] Figure 8 This is a schematic diagram of the process for forming a second electrode on a gallium nitride stack in one embodiment;

[0051] Figure 9 Execution provided in one embodiment Figure 8 A schematic diagram of the cross-sectional structure obtained by the method shown;

[0052] Figure 10 This is a schematic flowchart illustrating the fabrication method of a nano-light-emitting device provided in one embodiment.

[0053] Explanation of reference numerals in the attached figures:

[0054] 10 - Substrate, 20 - Gallium nitride stack, 210 - Second gallium nitride layer, 220 - Third gallium nitride layer, 30 - Quantum well active layer, 40 - First gallium nitride layer, 50 - First conductive layer, 60 - Sacrificial layer, 70 - Silicon oxide layer, 80 - First electrode, 90 - Second electrode. Detailed Implementation

[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0060] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0061] As mentioned in the background section, ensuring good performance of nano-light-emitting devices during fabrication presents certain challenges. To address this, this application provides a nano-light-emitting device and its fabrication method, capable of producing high-performance nano-light-emitting devices.

[0062] In one embodiment, a method for fabricating a nano-light-emitting device is provided. For example... Figure 1 As shown, the fabrication method of this nano-luminescent device may include the following steps S11 to S18.

[0063] S11: Provides epitaxial wafers.

[0064] Please see Figure 2a The epitaxial wafer comprises, from bottom to top, a substrate 10, a gallium nitride stack 20, a quantum well active layer 30, a first gallium nitride layer 40, and a first conductive layer 50. The substrate 10 can be made of any suitable substrate material, such as a sapphire substrate. The gallium nitride stack 20 comprises multiple layers of different gallium nitride layers. The number of stacked gallium nitride layers and the structural type of each layer can be set according to actual needs, without any limitations. The first conductive layer 50 can be made of any suitable transparent conductive material, such as indium tin oxide (ITO), without any limitations.

[0065] S12: A sacrificial layer is formed on the first conductive layer.

[0066] Please see Figure 2b The sacrificial layer 60 is located on the first conductive layer 50. The material of the sacrificial layer 60 can be any suitable material, such as silicon oxide (SiO2), without any limitation.

[0067] S13: Etch the sacrificial layer, the first conductive layer, the first gallium nitride layer and the quantum well active layer to form at least one nanopillar structure on the gallium nitride stack.

[0068] Please see Figure 2c The nanopillar structure includes, from bottom to top, a quantum well active layer 30, a first gallium nitride layer 40, a first conductive layer 50, and a sacrificial layer 60. The nanopillar structure formed on the gallium nitride stack 20 may include one or more, and the specific configuration can be determined according to the actual light-emitting requirements of the nano-light-emitting device; no limitations are imposed here.

[0069] S14: Wet etching is used to remove impurity particles from the periphery of the nanopillar structure.

[0070] Please continue reading. Figure 2c The nanopillar structure formed in step S13 will have excess impurity particles on its periphery. These impurity particles will affect the luminescence performance of the nano-light-emitting device. Therefore, in this embodiment, wet etching technology can be used to remove the impurity particles on the periphery of the nanopillar structure, such as... Figure 2d As shown, this method avoids the influence of impurity ions on the nano-light-emitting device, thereby improving the light-emitting performance of the nano-light-emitting device.

[0071] S15: A silicon oxide layer is formed on the gallium nitride stack and nanopillar structure.

[0072] Please see Figure 2eThe silicon oxide layer 70 is disposed in contact with each nanopillar structure, and the silicon oxide layer is located on the gallium nitride layer 70 and the nanopillar structure.

[0073] S16: Remove the sacrificial layer and part of the silicon oxide layer to expose the first conductive layer of the nanopillar structure.

[0074] Please see Figure 2f For example, the depth to which part of the silicon oxide layer 70 is removed can be 200nm-300nm, such as 220nm, 250nm, or 275nm, or any other value between 200nm and 300nm, without any limitation. The height of the first conductive layer 50 of the nanopillar structure exposed above the silicon oxide layer 70 is less than 50nm. After removing the sacrificial layer 60, the nanopillar structure includes a quantum well active layer 30, a first gallium nitride layer 40, and a first conductive layer 50 arranged sequentially from bottom to top.

[0075] S17: The first electrode is formed on the nanopillar structure and the silicon oxide layer.

[0076] Please see Figure 2g The first electrode 80 is disposed in contact with the first conductive layer 50, and the first conductive layer 50 forms an ohmic contact with the first gallium nitride layer 40. For example, the material of the first electrode 80 can be any suitable transparent conductive material.

[0077] S18: A second electrode is formed on the gallium nitride stack.

[0078] Please see Figure 2h The second electrode 90 is spaced apart from each nanopillar structure and silicon oxide layer 70. That is, the second electrode 90 does not contact each other with the nanopillar structures and silicon oxide layer 70. The material of the second electrode 90 can be any suitable material, such as a metal material like gold (Au) or chromium (Cr), without any limitation. For example, the thickness of the Au layer of the second electrode 90 can be 10 nm, and the thickness of the Cr layer of the second electrode 90 can be 50 nm. The second electrode 90 forms a good ohmic contact with the gallium nitride stack 20 to provide excellent performance.

[0079] The fabrication method of the nano-light-emitting device provided in the above embodiments includes an epitaxial wafer. After forming a sacrificial layer 60 on the first conductive layer 50 of the epitaxial wafer, at least one nanopillar structure is etched from top to bottom, penetrating the sacrificial layer 60, the first conductive layer 50, the first gallium nitride layer 40, the quantum well active layer 30, and reaching the gallium nitride stack 20. This ensures the integrity of the nanopillar structure of the nano-light-emitting device, and each nanopillar structure can serve as a pixel of a nano-LED. Then, wet etching is used to remove impurity particles around the nanopillar structure, avoiding the influence of impurity particles on the nano-light-emitting device and improving the light-emitting performance of the nano-light-emitting device. Next, a silicon oxide layer 70 is formed on the gallium nitride stack 20 and the nanopillar structure, and then the sacrificial layer 60 is removed. A portion of the silicon oxide layer 70 is used to expose the first conductive layer 50 of the nanopillar structure. A first electrode 80 is formed on the nanopillar structure and the silicon oxide layer 70, and the first electrode 80 is in contact with the first conductive layer 50. A second electrode 90 is formed on the gallium nitride stack 20, and the second electrode 90 is spaced apart from the nanopillar structure and the silicon oxide layer 70. The nano-LED fabricated in this way has a complete nanopillar structure shape, which improves the light extraction efficiency and light emission performance of the nano-LED device. It also releases stress to a greater extent in the nanoscale processing technology, alleviates the polarization field effect caused by stress concentration, and strengthens the current confinement capability at the nanoscale during electron transport in the vertical direction, resulting in higher electro-optic conversion efficiency.

[0080] In one embodiment, such as Figure 3a As shown, the gallium nitride stack 20 may include a second gallium nitride layer 210 and a third gallium nitride layer 220 disposed sequentially from bottom to top. A second electrode 90 is located on the third gallium nitride layer 220, and the second electrode 90 forms a good ohmic contact with the gallium nitride stack 20 to provide excellent performance. The third gallium nitride layer 220 and the first gallium nitride layer 40 have different conductivity types. For example, the first gallium nitride layer 40 is a doped P-type gallium nitride layer, the second gallium nitride layer 210 is an undoped gallium nitride layer, and the third gallium nitride layer 220 is an undoped N-type gallium nitride layer.

[0081] In one embodiment, the quantum well active layer 30 can be a gallium nitride layer doped with indium atoms. The doping ratio of indium atoms in the quantum well active layer 30 is related to the emission wavelength of the nano-light-emitting device. Specifically, the doping ratio of indium atoms in the quantum well active layer 30 is positively correlated with the wavelength of the emission wavelength of the nano-light-emitting device. Based on this, nano-light-emitting devices with different emission wavelengths can be formed, improving the diversity of nano-light-emitting devices.

[0082] For example, when the emission band of the nano-light-emitting device is the blue light band, the doping ratio of indium atoms in the corresponding quantum well active layer 30 is about 15%; when the emission band of the nano-light-emitting device is the green light band, the doping ratio of indium atoms in the corresponding quantum well active layer 30 is about 25%; and when the emission band of the nano-light-emitting device is the yellow light band, the doping ratio of indium atoms in the corresponding quantum well active layer 30 is about 35%.

[0083] In one embodiment, step S12, forming a sacrificial layer on the first conductive layer, may include step S121: depositing a silicon oxide layer (SiO2) on the first conductive layer as a sacrificial layer using plasma-enhanced chemical vapor deposition (PECVD) technology. Figure 3a Taking the epitaxial wafer shown as an example, the nano-light-emitting device structure with a SiO2 layer deposited on the first conductive layer 50 as a sacrificial layer 60 is as follows. Figure 3b As shown.

[0084] Specifically, the PECVD method for growing SiO2 involves introducing a mixture of nitrogen (N2) at 270 sccm, nitrous oxide (N2O) at 800 sccm, and a 5% silane (SiH4) and N2 mixture at 150 sccm into the reaction chamber. Under conditions of 250 mTorr pressure, 10 W low-frequency power, and 300°C chamber temperature, SiO2 is deposited on the epitaxial wafer surface for 23 minutes. For example, the thickness of the SiO2 layer can be set to 400 nm-1000 nm, such as 500 nm, 800 nm, or 95 nm, or any other value between 400 nm and 1000 nm; no limitations are imposed here.

[0085] In one embodiment, step S13, etching the sacrificial layer, the first conductive layer, the first gallium nitride layer, and the quantum well active layer to form at least one nanopillar structure on the gallium nitride stack, may include step S131: using focused ion beam (FIB) etching technology to etch the sacrificial layer, the first conductive layer, the first gallium nitride layer, and the quantum well active layer to form at least one nanopillar structure on the gallium nitride stack. Specifically, before using the FIB equipment, prepare a 24-bit black and white image in bmp format with a size not exceeding 4MB and import it into the equipment. The image contains information about the etching pattern. During the etching process, the operating voltage is 30kV, the operating beam current should be less than 2.5nA, and the energy density is 0.27μm. 3 / nC, the etching depth can be set to 1.5μm-2.5μm, thus ensuring that the etching stop surface remains on the gallium nitride stack.

[0086] In one embodiment, step S14, removing impurity particles from the periphery of the nanopillar structure by wet etching, may include step S141: removing impurity particles from the periphery of the nanopillar structure by wet etching based on potassium hydroxide solution under a preset temperature environment.

[0087] For example, a 9:50 potassium hydroxide:water solution can be used to treat nanopillar structures at 95°C for 4-5 minutes to remove impurity particles surrounding the nanopillar structures. Higher temperatures can enhance the remediation capacity of the potassium hydroxide solution and further improve efficiency. In actual treatment, the temperature can be set according to requirements, and no limitations are imposed here.

[0088] To better understand, Figure 3a Taking the epitaxial wafer shown as an example, step S141 will be explained above. After performing step S13, the periphery of the multiple nanopillar structures formed contains impurity particles, such as... Figure 4a As shown. To address this, step S141 is performed to remove impurity particles from the periphery of the nanopillar structure using wet etching with a potassium hydroxide solution, such as... Figure 4b As shown, the dashed line depicts the state of the nanopillar structure before an impurity particle is removed, and the arrow indicates the direction in which the impurity particle is removed. The nanopillar structure after removing the impurity particle is shown below. Figure 4c As shown, Figure 4c The corresponding top view is as follows Figure 4d As shown, its scale bar is 500 nm.

[0089] In one embodiment, step S15, forming a silicon oxide layer on the gallium nitride stack and the nanopillar structure, may include forming the silicon oxide layer on the gallium nitride stack and the nanopillar structure using a solution gel method, thereby forming a dense and flat SiO2 film layer on the gallium nitride stack. Taking the sacrificial layer 60 as being made of silicon oxide (SiO2) as an example, in this case, the silicon oxide layer 70 and the sacrificial layer 60 are both SiO2 layers, and the nano-light-emitting device structure after forming the silicon oxide layer 70 on the gallium nitride layer 20 is as follows. Figure 5 As shown. Specifically, step S15 may include steps S151 and S152.

[0090] S151: The nano-light-emitting device with the nanopillar structure is placed in the first solution and ultrasonically treated to form chemical bridging bonds on the surface of the gallium nitride stack and the nanopillar structure.

[0091] The first solution may include toluene, 3-aminopropyltriethoxysilane (APTES), and water. Exemplarily, the first solution may be configured as solution A comprising 10 ml of toluene solution, 2 ml of APTES, and 10 ml of aqueous solution. Exemplarily, the nanoluminescent device may be immersed in solution A and sonicated for 1-2 minutes to remove air bubbles from the surface of the nanopillar structure, thereby uniformly forming surface chemical bridging bonds on its surface.

[0092] S152: The nano-light-emitting device with chemically bridged bonds on its surface is placed in a second solution and subjected to low-pressure treatment, and after being left to stand in air, a silicon oxide layer is formed on the gallium nitride stack and nanopillar structure.

[0093] The second solution comprises the toluene, anhydrous ethanol, and ammonia. Exemplarily, the second solution can be configured as solution B comprising 10 ml of toluene, 0.2 ml of anhydrous ethanol, and 0.1 ml of ammonia. Exemplarily, the nano-light-emitting device with chemically bridged bonds on its surface is immersed in solution B and subjected to low-pressure treatment for 30 seconds to 1 minute. The low-pressure environment allows for thorough mixing and reaction, forming a dense film. After standing in air to absorb moisture, a flat silicon oxide layer (SiO2) 70 is finally obtained.

[0094] In one embodiment, to Figure 5 Taking the structure shown as an example, the sacrificial layer 60 is a silicon oxide layer (SiO2). That is, when the sacrificial layer 60 and the silicon oxide layer 70 are made of the same material, step S16, removing the sacrificial layer and part of the silicon oxide layer to expose the first conductive layer of the nanopillar structure, may include step S161: using inductively coupled plasma (ICP) technology to remove the sacrificial layer 60-SiO2 layer at the top of the nanopillar structure, and to remove part of the silicon oxide layer 70, or in other words, to thin the silicon oxide layer 70. Figure 6 As shown, based on this, the nanopillar structure includes, from bottom to top, a quantum well active layer 30, a first gallium nitride layer 40, and a first conductive layer 50.

[0095] For example, a mixture of carbon tetrafluoride (CF4) and oxygen (O2) can be introduced into the reaction chamber at a flow rate of 30 sccm:10 sccm (CF4:O2), a high-frequency power of 150 W, a pressure of 4 Pa, and an etching time of 50 s, so that the height of the nanopillar structure exposed on the surface is less than 50 nm. Specifically, the etching time can be controlled to ensure that the height of the nanopillar structure exposed on the surface is less than 50 nm.

[0096] In one embodiment, step S17, forming a first electrode on the nanopillar structure and the silicon oxide layer, may include step S171: using electron beam evaporation technology to deposit a first conductive layer on the top of the nanopillar structure. At this time, the material of the first electrode is the same as the material of the first conductive layer. The first electrode and the first conductive layer are in contact and form a good ohmic contact to improve device performance.

[0097] by Figure 6 Taking the structure shown as an example, if the first conductive layer 50 is an ITO conductive layer, the ITO conductive layer is deposited using electron beam evaporation technology. After deposition, the ITO conductive layer of the nano-light-emitting device is located on the silicon oxide layer 70 and the nanopillar structure, and the deposited ITO layer serves as the first electrode 80, forming an ohmic contact with the ITO conductive layer 50 at the top of the nanopillar structure. Figure 7 As shown.

[0098] For example, the method of depositing an ITO conductive layer using electron beam evaporation technology involves a chamber temperature of 160°C and a pressure of 5*10⁻⁶. -3 Pa, beam current of 20mA-30mA, the evaporation rate is controlled and stabilized according to the value displayed by the film thickness gauge. A 100 nm thick ITO conductive layer is deposited by vapor deposition and then subjected to rapid annealing to form an ohmic contact with the first gallium nitride layer 40. Specifically, the sample is placed in a rapid annealing furnace, the N2 gas flow valve is opened and the flow rate is controlled at 5000 sccm, the water cooling and air cooling devices are turned on, the heating rate is set to 100 °C / s, the maximum temperature is set to 600 °C, and the device is started to complete the rapid annealing operation so that the vapor-deposited ITO conductive layer 80 forms an ohmic contact with the first conductive layer 50 at the top of the nanopillar structure.

[0099] In one embodiment, such as Figure 8 As shown, step S18, forming a second electrode on the gallium nitride stack, may include steps S181 to S184.

[0100] S181: A photoresist layer is formed on the first electrode.

[0101] by Figure 7 Taking the structure shown as an example, both the first electrode 80 and the first conductive layer 50 at the top of the nanopillar structure are ITO conductive layers. In this case, a photoresist layer is formed on the first electrode 80. For example, C7510 photoresist can be spin-coated onto the ITO conductive layer, and the thickness of the photoresist layer can be 2.8 μm. Based on this, the nano-light-emitting device with the photoresist layer formed can be pre-baked at 115°C for a time controlled at 70°C to initially remove moisture from the photoresist.

[0102] S182: Pattern the photoresist layer and etch the first electrode and silicon oxide layer to form an electrode contact window on the gallium nitride stack.

[0103] For example, the prepared GDS file can be imported into the device via laser direct writing. The exposure start point is set in the area near the nanopillar structure using the microscope built into the device, and the exposure dose is set to 20ms-30ms. After the exposure ends, positive photoresist developer is used for development, and then the image is baked at 150°C for 30 minutes.

[0104] Based on step S181 above, if the first electrode 80 is an ITO conductive layer, ion beam etching (IBE) is first used to etch the ITO conductive layer. Specifically, the accelerating voltage is set to 200V, the gate voltage is set to 250V-300V, the beam current is 80mA, and the etching rate is approximately... The etching time was 12 min. Then, ICP technology was used to etch the silicon oxide layer 70. A mixed gas of CF4 and O2 was introduced into the reaction chamber. The gas flow rate of CF4:O2 was 30 sccm:10 sccm, the high-frequency power was 150 W, the pressure was 4 Pa, and the etching time was 3 min, until the third gallium nitride layer 220 was exposed, and finally the electrode contact window was obtained.

[0105] S183: A second electrode is formed by filling the electrode contact window with conductive material.

[0106] The second electrode 90 has the opposite electrode orientation to the first electrode 80, and is spaced apart from each nanopillar structure and the silicon oxide layer 70. For example, the first electrode 80 is a positive electrode, and the second electrode 90 can be a negative electrode. For example, a layer of metal can be deposited as the first electrode 90 using thermal evaporation technology. Specifically, the metal source is evaporated using a thermal evaporator, with a chamber temperature of 770℃-800℃ and a pressure of 3*10⁻⁶. -2 Pa, the evaporation time is 30 min.

[0107] S184: Remove the photoresist layer.

[0108] For example, the sample can be treated with acetone for 2 hours, then immersed in isopropanol solution to remove residual acetone, finally rinsed with anhydrous ethanol, dried with an air gun, and the photoresist and metal on the photoresist layer can be stripped away. Figure 7 Taking the structure shown as an example, a second electrode 90 is formed by filling the electrode contact window with conductive material. The nano-light-emitting device after removing the photoresist is as follows: Figure 9 As shown.

[0109] The method for fabricating the nano-light-emitting device provided in the above embodiments involves forming a second electrode 90 on a third gallium nitride stack 220 to form a nano-light-emitting device with a PN structure.

[0110] To better understand, such as Figure 10 As shown, another method for fabricating a nano-light-emitting device is provided, which may include the following steps S1001 to S1008.

[0111] S1001: Provides an epitaxial wafer. This epitaxial wafer may include, from bottom to top, a sapphire substrate, an undoped gallium nitride layer, an N-type gallium nitride layer, a quantum well active layer 30, a P-type gallium nitride layer, and an ITO conductive layer, such as... Figure 3a As shown.

[0112] S1002: A SiO2 layer is formed on an ITO conductive layer using PECVD technology. For example... Figure 3b As shown.

[0113] S1003: The SiO2 layer, ITO conductive layer, P-type gallium nitride layer, and quantum well active layer are etched from top to bottom using FIB technology to form an array of nanopillar structures on the N-type gallium nitride layer. For example... Figure 4a As shown.

[0114] S1004: Impurity particles on the periphery of the nanopillar structure are removed by wet etching with potassium hydroxide solution at 95°C. Figure 4c As shown.

[0115] S1005: A SiO2 layer is formed on an N-type gallium nitride layer using a solution gelation method to fill the nanopillar structure. For example... Figure 5 As shown.

[0116] S1006: The silicon oxide layer is thinned using ICP technology to expose the nanopillar-structured ITO conductive layer. For example... Figure 6 As shown.

[0117] S1007: An ITO conductive layer is deposited at the top of the nanopillar structure using electron beam evaporation technology, forming a conductive contact with the ITO conductive layer at the top of the nanopillar structure, and serving as the first electrode. For example... Figure 7 As shown.

[0118] S1008: C7510 photoresist is spin-coated onto the first electrode. After exposure and development, the ITO conductive layer is etched using IBE technology, and the silicon oxide layer is etched using ICP technology to form an N-type electrode contact window on the P-type gallium nitride layer. Then, a second electrode is formed on the P-type gallium nitride layer using thermal evaporation technology. For example... Figure 9 As shown.

[0119] It should be understood that although the steps in each flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in each flowchart may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0120] Based on the fabrication methods of the nano-light-emitting devices provided in the above embodiments, this application also provides a nano-light-emitting device. Please refer to... Figure 2h The nano-light-emitting device may include a substrate 10, a gallium nitride stack 20, at least one nanopillar structure, a silicon oxide layer 70, a first electrode 80, and a second electrode 90.

[0121] The substrate 10 can be made of any suitable substrate material, such as a sapphire substrate. A gallium nitride (GaN) stack 20 is located on the substrate 10 and can include multiple layers of different GaN layers. The nanopillar structure includes, from bottom to top, a quantum well active layer 30, a first GaN layer 40, and a first conductive layer 50, wherein the quantum well active layer 30 is located on the GaN stack 20. A silicon oxide layer 70 is located on the GaN stack 20 and in contact with the nanopillar structure, with its upper surface flush with the upper surface of the nanopillar structure. A first electrode 80 is located on the nanopillar structure and the silicon oxide layer 70 and in contact with the first conductive layer 50. A second electrode 90 is located on the GaN stack 20 and is spaced apart from each nanopillar structure and the silicon oxide layer 70. The projection of the second electrode 100 toward the substrate 10 does not overlap with the projection of each nanopillar structure toward the substrate 10, and the electrodes of the first electrode 90 and the second electrode 100 are opposite. For details on the specific structures of each part of the nano-light-emitting device, please refer to the above-mentioned examples of the fabrication methods of each nano-light-emitting device, which will not be repeated here.

[0122] The nano-light-emitting device provided in the above embodiments includes a substrate 10, a gallium nitride stack 20, at least one nanopillar structure, a silicon oxide layer 70, a first electrode 80, and a second electrode 90. Each nanopillar structure can serve as a pixel in the nano-light-emitting device, and its shape is intact. This improves the light extraction efficiency and luminous performance of the nano-light-emitting device. Furthermore, the stress caused by doping in the quantum well active layer of the nanopillar structure is released to a greater extent at the nanoscale, alleviating the polarization field effect caused by stress concentration. In addition, the current confinement capability at the nanoscale is strengthened during electron transport in the vertical direction, improving the electro-optical conversion efficiency.

[0123] In one embodiment, the nano-light-emitting device includes a plurality of nanopillar structures arranged in an array, with each nanopillar structure spaced apart and a silicon oxide layer 70 disposed between two adjacent nanopillar structures, and each nanopillar structure can serve as a pixel of a nano-LED.

[0124] In one embodiment, the height of each nanopillar structure is 1.5 μm to 2.5 μm, the diameter of each nanopillar structure is 100 nm to 1000 nm, and the spacing between two adjacent nanopillar structures is 100 nm to 5 μm.

[0125] In one embodiment, such as Figure 9 As shown, the gallium nitride stack 20 may include a second gallium nitride layer 210 and a third gallium nitride layer 220 disposed sequentially from bottom to top. The second electrode 90 is located on the third gallium nitride layer 220, and the third gallium nitride layer 220 and the first gallium nitride layer 40 have different conductivity types. For example, the first gallium nitride layer 40 is a doped P-type gallium nitride layer, the second gallium nitride layer 210 is an undoped gallium nitride layer, and the third gallium nitride layer 220 is an undoped N-type gallium nitride layer.

[0126] In one embodiment, the thickness of the second gallium nitride layer 210 can be 1 μm-2 μm, for example, 1.2 μm, 1.5 μm, 1.7 μm, 1.8 μm, or any other value between 1 μm and 2 μm, without any limitation herein. The thickness of the third gallium nitride layer 220 can be 2 μm-5 μm, for example, 2 μm, 2.5 μm, 3.2 μm, 3.6 μm, or any other value between 2 μm and 5 μm, without any limitation herein. The thickness of the quantum well active layer 30 can be 10 nm-30 nm, for example, 15 nm, 18 nm, 20 nm, 25 nm, 31 nm, or any other value between 10 nm and 30 nm, without any limitation herein. The thickness of the first gallium nitride layer 40 can be set to 200nm-500nm, for example, 260nm, 390nm, 440nm, or any other value between 200nm and 500nm, without any limitation. The thickness of the first conductive layer 50 can be set to 100nm-300nm, for example, 120nm, 200nm, 260nm, or any other value between 100nm and 300nm, without any limitation.

[0127] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0128] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a nano-light-emitting device, characterized in that, include: An epitaxial wafer is provided, comprising, from bottom to top, a substrate, a gallium nitride stack, a quantum well active layer, a first gallium nitride layer, and a first conductive layer; the gallium nitride stack comprises, from bottom to top, a second gallium nitride layer and a third gallium nitride layer; a second electrode is located on the third gallium nitride layer; the first gallium nitride layer is a doped p-type gallium nitride layer, the second gallium nitride layer is an undoped gallium nitride layer, and the third gallium nitride layer is an undoped n-type gallium nitride layer; The active layer of the quantum well is a gallium nitride layer doped with indium atoms; A sacrificial layer is formed on the first conductive layer; The sacrificial layer, the first conductive layer, the first gallium nitride layer, and the quantum well active layer are etched to form at least one nanopillar structure on the N-type gallium nitride layer; the nanopillar structure includes the quantum well active layer, the first gallium nitride layer, and the first conductive layer arranged from bottom to top. Wet etching was used to remove impurity particles from the periphery of the nanopillar structure; The nano-light-emitting device with the nanopillar structure is placed in a first solution and ultrasonically treated to form chemical bridging bonds on the surfaces of the N-type gallium nitride layer and the nanopillar structure. The nano-light-emitting device with the chemical bridging bonds on its surface is then placed in a second solution and subjected to low-pressure treatment. After being left to stand in air, a silicon oxide layer is formed on the N-type gallium nitride layer and the nanopillar structure. The first solution comprises toluene, 3-aminopropyltriethoxysilane, and water. The second solution comprises toluene, anhydrous ethanol, and ammonia. The sacrificial layer and part of the silicon oxide layer are removed to expose the first conductive layer of the nanopillar structure; the height of the first conductive layer of the nanopillar structure exposed above the silicon oxide layer is less than 50 nm. Using electron beam evaporation technology, the first conductive layer is deposited on the top of the nanopillar structure, and a first electrode is formed on the nanopillar structure and the silicon oxide layer, with the first electrode in contact with the first conductive layer; the first electrode and the first conductive layer are made of the same material. A second electrode is formed on the p-type gallium nitride layer, and the second electrode is spaced apart from the nanopillar structure and the silicon oxide layer.

2. The method for fabricating the nano-light-emitting device according to claim 1, characterized in that, The etching of the sacrificial layer, the first conductive layer, the first gallium nitride layer, and the quantum well active layer to form at least one nanopillar structure on the N-type gallium nitride layer includes: Focused ion beam etching is used to etch the sacrificial layer, the first conductive layer, the first gallium nitride layer, and the quantum well active layer to form at least one nanopillar structure on the N-type gallium nitride layer.

3. The method for fabricating the nano-light-emitting device according to claim 1, characterized in that, The formation of a sacrificial layer on the first conductive layer includes: A silicon oxide layer is deposited on the first conductive layer as the sacrificial layer using plasma-enhanced chemical vapor deposition (PECVD). The silicon oxide layer is grown using PECVD by introducing a mixture of nitrogen (270 sccm), nitrous oxide (800 sccm), and a 5% silane and N2 gas (150 sccm) into the reaction chamber. Under conditions of 250 mTorr pressure, 10 W low-frequency power, and 300°C chamber temperature, SiO2 is deposited on the epitaxial wafer surface for 23 minutes. The thickness of the SiO2 layer is set to 400 nm-1000 nm.

4. The method for fabricating the nano-light-emitting device according to claim 1, characterized in that, The process of removing impurity particles from the periphery of the nanopillar structure using wet etching includes: Under a preset temperature environment, impurity particles on the periphery of the nanopillar structure are removed by wet etching using potassium hydroxide solution.

5. The method for fabricating the nano-light-emitting device according to claim 1, characterized in that, The process of forming a second electrode on the P-type gallium nitride layer includes: A photoresist layer is formed on the first electrode; The photoresist layer is patterned, and the first electrode and the silicon oxide layer are etched to form an electrode contact window on the P-type gallium nitride layer; A second electrode is formed by filling the electrode contact window with conductive material; Remove the photoresist layer.

6. A nano-light-emitting device, characterized in that, include: Substrate; A gallium nitride (GaN) stack is located on the substrate; the GaN stack includes a second GaN layer and a third GaN layer disposed sequentially from bottom to top; a second electrode is located on the third GaN layer; the first GaN layer is a doped P-type GaN layer, the second GaN layer is an undoped GaN layer, and the third GaN layer is an undoped N-type GaN layer; the quantum well active layer is a GaN layer doped with indium atoms; At least one nanopillar structure, the nanopillar structure comprising, from bottom to top, a quantum well active layer, a first gallium nitride layer and a first conductive layer; wherein, the quantum well active layer is located on the N-type gallium nitride layer; A silicon oxide layer is located on the N-type gallium nitride layer and is in contact with the nanopillar structure, and the upper surface of the silicon oxide layer is flush with the upper surface of the nanopillar structure. The first electrode is located on the nanopillar structure and the silicon oxide layer, and is in contact with the first conductive layer; The second electrode is located on the p-type gallium nitride layer and is spaced apart from the nanopillar structure and the silicon oxide layer, respectively; the nano-light-emitting device is fabricated using the method described in any one of claims 1-5.

7. The nano-light-emitting device according to claim 6, characterized in that, The nano-light-emitting device includes a plurality of nanopillar structures arranged in an array, with each nanopillar structure spaced apart and a silicon oxide layer disposed between two adjacent nanopillar structures.

8. The nano-light-emitting device according to claim 7, characterized in that, The height of each nanopillar structure is 1.5μm-2.5μm, the diameter of each nanopillar structure is 100nm-1000nm, and the spacing between two adjacent nanopillar structures is 100nm-5μm.

9. The nano-light-emitting device according to claim 6, characterized in that, The active layer of the quantum well is a gallium nitride layer doped with indium atoms; wherein, the doping ratio of indium atoms in the active layer of the quantum well is related to the emission wavelength of the nano-light-emitting device.

10. The nano-light-emitting device according to claim 6, characterized in that, The thickness of the second gallium nitride layer is 1μm-2μm; the thickness of the third gallium nitride layer is 2μm-5μm.

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