Potential conversion circuit

Abstract

This disclosure provides a potential conversion circuit for converting a first signal having an input voltage range V1 into a potential conversion output having an output voltage range V2. The potential conversion circuit includes: an NMOS depletion mode transistor having a drain connected to an output range upper-level supply node, a source connected to an intermediate node, and a gate connected to an output node; a PMOS enhancement mode transistor having a drain connected to an output node, a source connected to an intermediate node, and a gate connected to an input node; and an NMOS enhancement mode transistor having a drain connected to an output node, a source connected to an output range lower-level supply node, and a gate connected to an input node.

Description

Technical Field

[0001] This disclosure relates to a potential conversion circuit used to increase the voltage range of an input signal to a higher voltage range. Background Technology

[0002] In various electronic devices, a control signal is generated using a first low power supply voltage, and then the control signal is converted to a second high power supply voltage. The voltage conversion control signal can then be applied to a high-voltage circuit. The voltage conversion circuit may include multiple transistors, thus requiring a large layout area. See, for example, U.S. Patent No. 8,638,618, issued January 28, 2014, by Hung et al. The problem of a large layout area is amplified, especially in devices utilizing multiple voltage conversion circuits. It is desirable to provide a voltage conversion circuit that requires a smaller layout area but can operate under high voltage conversion. Summary of the Invention

[0003] This disclosure describes a miniaturized potential conversion circuit. In one embodiment, the potential conversion circuit is used to connect a first signal having an input voltage range V1 having an input high potential and an input low potential (e.g., VDD and VSS) to generate a potential-converted output having an output voltage range V2 having an output high potential and an output low potential (e.g., HV and VSS), the output voltage range being greater than the input voltage range. The potential conversion circuit may include: an NMOS depletion-type transistor having a drain terminal connected to an output range upper-level supply node, a source terminal connected to an intermediate node, and a gate terminal connected to an output node; a PMOS enhancement-type transistor having a drain terminal connected to an output node, a source terminal connected to an intermediate node, and a gate terminal connected to a first node; and an NMOS enhancement-type transistor having a drain terminal connected to an output node, a source terminal connected to an output range lower-level supply node, and a gate terminal connected to the first node.

[0004] In the embodiments described in this disclosure, the NMOS depletion-type transistor has a first threshold voltage and the PMOS enhancement-type transistor has a second threshold voltage, and the first threshold voltage is also negative (i.e. less than) the second threshold voltage, and the sum of the high potential of the input range and the first threshold voltage is less negative (i.e. greater than) the second threshold voltage.

[0005] In the embodiments described in this disclosure, the potential switching circuit includes a second NMOS depletion-type transistor having a drain terminal connected to a high-potential supply node of the output range, a source terminal connected to an intermediate node, and a gate terminal connected to a complementary signal of the first signal. In this embodiment, the NMOS depletion-type transistor has a first threshold voltage, the PMOS enhancement-type transistor has a second threshold voltage, and the second NMOS depletion-type transistor has a third threshold voltage, wherein the third threshold voltage plus the high-potential input range is less negative than the second threshold voltage, and the second threshold voltage is less negative than the third threshold voltage minus the high-potential input range.

[0006] Other aspects and advantages of this disclosure will become apparent from the following drawings and detailed description.

[0007] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0008] Figure 1 A simplified diagram of an electronic device including a miniaturized potentiometer as described in this disclosure.

[0009] Figure 2 for Figure 1 The voltage potential curve of the circuit.

[0010] Figure 3 This is a schematic diagram of a miniaturized potentiometer as described in this disclosure.

[0011] Figure 4 Figure 3 The circuit timing diagram.

[0012] Figure 5 This is a schematic diagram of another embodiment of the miniaturized potentiometer as described in this disclosure.

[0013] Figure 6 This is a schematic diagram of yet another embodiment of the miniaturized potentiometer as described in this disclosure.

[0014] Explanation of reference numerals in the attached figures

[0015] 100: Potentiometer

[0016] 101, 102, 103, 106, 107: Lines

[0017] 105: Transistor

[0018] 301, 501: Inverters

[0019] 302, 502: Low-range high-potential supply nodes

[0020] 303, 503: Low-range low-potential supply nodes

[0021] 305, 505: High-potential supply node for output range

[0022] 306, 506: Output range low-potential supply node

[0023] 401, 402, 403, 411, 412, 413, 610: Arrows

[0024] HV: High voltage

[0025] A: Node

[0026] MV: Intermediate potential voltage

[0027] M1: First NMOS depletion-type transistor

[0028] M2: First PMOS enhancement transistor

[0029] M3: First NMOS enhancement transistor

[0030] N1: First node

[0031] N2: Intermediate node

[0032] IN: Input signal

[0033] VDD: Voltage power supply

[0034] VSS: Low-potential supply voltage

[0035] OUT: Output node

[0036] Vthn_M1: Threshold voltage

[0037] M4: Second NMOS depletion-type transistor Detailed Implementation

[0038] in accordance with Figure 1-6 A detailed description of embodiments of this technology is provided.

[0039] Figure 1 A simplified diagram of an electronic device including a miniaturized potentiometer 100 is shown. A low-voltage LV digital control signal is received on line 101. This low-voltage LV digital control signal has an input voltage range established using a lower voltage power supply (e.g., VDD). A high-voltage power supply (HV Power) is applied to line 103 of the miniaturized potentiometer 100. The miniaturized potentiometer 100 outputs a high-voltage HV control signal to line 102, which is established using the high-voltage power supply.

[0040] In this example, the electronic device outputs a high-voltage control signal on line 102 to the gate of transistor 105, which is used to transmit an intermediate potential voltage MV signal to node A on line 107. This configuration can be used as an example of node A coupled to a word line as a word line driver circuit, as described in U.S. Patent Publication No. 8,638,618 to Hung et al., which is incorporated herein by reference as if fully set forth herein.

[0041] Figure 2 for Figure 1 Voltage potential diagram of the circuit. In the circuit, a signal with three voltage ranges... Figure 2 The ranges are marked as HV, MV, and LV. For example... Figure 2 As shown, the HV range has a high voltage rangeupper level, which can be, for example, two voltages: 16V or 32V. Additionally, the HV range has a low voltage rangelow level, which can be, for example, ground or 0V. In some embodiments, the low voltage rangelow voltage can be other values, such as a negative voltage. The potential difference between the high voltage rangehigh potential and the high voltage rangelow potential is called the high voltage range. In both examples, where the high voltage rangelow potential is ground, the high voltage range can be 16V or 32V. Embodiments of the miniaturized potential converter described in this disclosure can operate with other high voltage ranges having a wider range.

[0042] Furthermore, the LV range has a high potential in the low voltage range, which can be, for example, two voltages: 5V or 2.5V. Additionally, the LV range has a low potential in the low voltage range, which can be, for example, ground or 0V. In some embodiments, the low voltage in the low voltage range can be other values, such as a negative voltage. The potential difference between the high potential and the low potential in the low voltage range is called the low voltage range. In both examples, where the low potential in the low voltage range is ground, the low voltage range can be 5V or 2.5V.

[0043] The miniaturized potentiometer embodiments described in this disclosure are operable in a smaller low-voltage range, such as less than 2.5V (e.g., 2.3V) and less than 1.5V (e.g., 1.2V).

[0044] Figure 2 It also shows the middle voltage range (MV), which has a middle voltage upper level and a middle voltage lower level. Figure 1In the example shown, in order to transmit the middle voltage signal on line 106 to node A, the high voltage control signal on line 102 must be high enough to turn on transistor 105. Therefore, the high voltage control signal must be at least the threshold voltage of transistor 105, which is higher than the middle voltage signal.

[0045] During operation, the digital control signal is the input on line 101, and as follows: Figure 2 The change from low potential to high potential is shown. In response, the high-voltage control signal is as follows: Figure 2 The signal changes from low to high potential. When the high-voltage control signal changes to high potential, node A also changes to medium-voltage high potential. When the digital control signal changes from high to low potential, the high-voltage control signal also changes to low potential, and transistor 105 turns off.

[0046] Figure 3 This is a schematic diagram of a miniaturized potential conversion circuit. In this example, the input signal IN is applied as input to inverter 301, which is coupled to lower range upper-level supply node 302 (which is applied with VDD) and lower range lower-level supply node 303 (which is applied with VSS). The output of inverter 301 is the first signal applied to the first node N1.

[0047] This potential conversion circuit includes a first NMOS depletion mode transistor M1, a first PMOS enhancement mode transistor M2, and a first NMOS enhancement mode transistor M3. The first NMOS depletion mode transistor M1 has a drain terminal connected to the output range upper-level supply node 305, a source terminal connected to the intermediate node N2, and a gate terminal connected to the output node OUT. The first PMOS enhancement mode transistor M2 has a drain terminal connected to the output node OUT, a source terminal connected to the intermediate node N2, and a gate terminal connected to the first node N1. The first NMOS enhancement mode transistor M3 has a drain terminal connected to the output node OUT, a source terminal connected to the output range lower-level supply node 306 to receive VSS, and a gate terminal connected to the first node N1.

[0048] The first NMOS depletion transistor M1 has a negative threshold voltage (i.e., threshold voltage Vthn_M1), such that the potential difference between the voltage at the output node OUT and the voltage at the intermediate node N2 must be equal to or greater than (less negative than) Vthn_M1 of the first NMOS depletion transistor M1 in order to turn on the first NMOS depletion transistor M1.

[0049] The first PMOS enhancement-mode transistor M2 has a negative threshold voltage (i.e., threshold voltage Vthp_M2), such that the potential difference between the voltage at the first node N1 and the voltage at the intermediate node N2 must be less than (and more negative than) Vthp_M2 of the first PMOS enhancement-mode transistor M2 in order to turn on the first PMOS enhancement-mode transistor M2. In the embodiments of the potential converter described in this disclosure, the threshold voltage Vthp_M2 of the first PMOS enhancement-mode transistor M2 is greater than (less negative than, or has a smaller absolute value) the threshold voltage Vthn_M1 of the first NMOS depletion-mode transistor M1.

[0050] The first NMOS enhancement-mode transistor M3 has a positive threshold voltage Vthn_M3, such that the potential difference between the voltage on the first node N1 and the low-potential supply voltage VSS must be equal to or greater than (positively greater than) Vthn_M3 of the first NMOS enhancement-mode transistor M3 in order to turn on the first NMOS enhancement-mode transistor M3.

[0051] In various embodiments, the low-range low-potential supply node 303 and the output-range low-potential supply node 306 are connected to a VSS, which can be DC ground or another DC reference voltage. In other embodiments, the low-range low-potential supply node 303 and the output-range low-potential supply node 306 may be connected to a VSS that is the same as AC ground. In other embodiments, the low-range low-potential supply node 303 and the output-range low-potential supply node 306 may be connected to a VSS that is the same as a negative voltage. In the illustrated embodiments, the low-potential supply node 303 and the output-range low-potential supply node 306 are coupled to ground or a 0V reference voltage, or otherwise have the same voltage potential.

[0052] Figure 4 for Figure 3 The timing diagram of the circuit operation. Figure 4In the diagram, the first trace line shows the signal at the input signal IN. The second trace line shows the signal at the first node N1. The third trace line shows the signal at the intermediate node N2. The fourth trace line shows the signal at the output node OUT. During operation, when the input signal changes from a low input potential (0V) to a high input potential (voltage supply VDD), the signal at the first node N1 changes from a high input potential to a low input potential (as shown by arrow 401). This change causes the voltage at the intermediate node N2 to change from a low potential (which is -Vthn_M1) to a high output potential (high voltage HV) (as shown by arrow 402). This change causes the output node OUT to change between a low output potential and a high output potential (as shown by arrow 403). When the input signal changes from a high input potential to a low input potential, the complementary sequence of changes occurs, as shown by arrows 411, 412, and 413.

[0053] In order for the output node OUT to change from a low output potential to a high output potential, when the voltage of the first node N1 changes to a low input potential (0V), the first NMOS enhancement-mode transistor M3 must be turned off, and the first PMOS enhancement-mode transistor M2 and the first NMOS depletion-mode transistor M1 must be turned on.

[0054] For the first PMOS enhancement-mode transistor M2 to turn on, the voltage VN1 at the first node N1 minus the voltage VN2 at the intermediate node N2 must be less than or even negative than Vthp_M2. With this change, the voltage at the first node N1 drops to the low potential of the input range or zero volts. Since the voltage at the output node OUT, which is at the low potential of the output range, is 0V, the voltage at the intermediate node N2 is clamped at OUT-Vthn_M1, i.e., -Vthn_M1. Therefore, for the first PMOS enhancement-mode transistor M2 to turn on, VN1-VN2 < Vthp_M2 (Equation 1).

[0055] However, the voltage VN1 at the first node N1 is 0V, and the voltage VN2 at the intermediate node N2 is Vthn_M1. Therefore, Equation 1 can be interpreted as:

[0056] Vthn_M1<Vthp_M2 (Equation 2)

[0057] Similarly, in order for the output node OUT to change from a high output potential to a low output potential, the first NMOS enhancement-mode transistor M3 must be turned on, and the first PMOS enhancement-mode transistor M2 and the first NMOS depletion-mode transistor M1 must be turned off.

[0058] To turn off the first PMOS enhancement-mode transistor M2, the voltage VN1 at the first node N1 minus the voltage VN2 at the intermediate node N2 must be greater than or even negative than Vthp_M2. For this change, the voltage at the first node N1 rises to the high end of the input range, or VDD volts. The voltage at the intermediate node N2 starts from OUT - Vthn_M1, but when the first NMOS enhancement-mode transistor M3 is turned on, OUT is pulled low, so the voltage at the intermediate node N2 also drops to its minimum value -Vthn_M1. Therefore, to turn off the first PMOS enhancement-mode transistor M2, VN1 - VN2 > Vthp_M2 (Equation 3).

[0059] However, the voltage VN1 at the first node N1 is VDD, and the voltage VN2 at the intermediate node N2 drops to -Vthn_M1. Therefore, Equation 1 can be interpreted as follows:

[0060] VDD-(-Vthn_M1)>Vthp_M2 (Equation 4)

[0061] Combining Equations 2 and 4, the threshold voltage conditions for the first NMOS depletion-type transistor M1 and the first PMOS enhancement-type transistor M2 are as follows:

[0062] VDD+Vthn_M1>Vthp_M2>Vthn_M1 (Equation 5)

[0063] Therefore, in Figure 3 In the circuit, the threshold voltage Vthp_M2 must be less than (i.e., also negative, with a higher absolute value) the sum of the high potential of the input range (voltage supply VDD) and the threshold voltage Vthp_M1 of transistor M1, and greater than (i.e., a smaller negative value, with a lower absolute value) the threshold voltage of the first NMOS depletion-type transistor M1. The potential difference between the absolute values ​​of VDD and Vthp_M1 provides a design window for operation. For example, during manufacturing, the threshold voltage of the transistor can be adjusted by modifying the channel doping concentration or other structural features of the transistor.

[0064] Therefore, when setting the threshold voltage of the first PMOS enhancement-mode transistor M2 according to Equation 5, Figure 3 The potential conversion circuit operates.

[0065] For example, assuming VDD is 2.3V and Vthn_M1 is -3V, the design window from Vthp_M2 is 0.7V > Vthp_M2 > -3V. To reduce leakage current, a PMOS turn-off margin w1 is added, and to increase transient speed, a PMOS turn-on margin w2 is added, changing the design window to -(0.7 + w1) > Vthp_M2 > -(3 - w2). In one example, w1 is approximately 1V and w2 is approximately 0.5V. The design window shrinks to: -1.7V > Vthp_M2 > -2.5V, assuming VDD is 2.3V.

[0066] However, the design window shrinks further as the input range drops below 2.3V. For example, when VDD equals 1.2V, the calculated design window for the above example is -2.8V > Vthp_M2 > -2.5V, which is not acceptable (because -2.8V is less than -2.5V).

[0067] Figure 5 An embodiment suitable for input ranges below 1.5V (e.g., 1.2V) is shown.

[0068] Figure 5 This is a schematic diagram of a miniaturized potential conversion circuit. In this example, the input signal IN is applied as input to inverter 501, which is coupled to low-range high-potential supply node 502 (which applies VDD) and low-range low-potential supply node 503 (which applies VSS). The output of inverter 501 is applied to the first node N1.

[0069] This potential conversion circuit includes a first NMOS depletion-type transistor M1, a first PMOS enhancement-type transistor M2, a first NMOS enhancement-type transistor M3, and a second NMOS depletion-type transistor M4. The first NMOS depletion-type transistor M1 has a drain terminal connected to the high-potential supply node 505 of the output range, a source terminal connected to the intermediate node N2, and a gate terminal connected to the output node OUT. The first PMOS enhancement-type transistor M2 has a drain terminal connected to the output node OUT, a source terminal connected to the intermediate node N2, and a gate terminal connected to the first node N1. The first NMOS enhancement-type transistor M3 has a drain terminal connected to the output node OUT, a source terminal connected to the low-potential supply node 506 of the output range to receive VSS, and a gate terminal connected to the first node N1.

[0070] The second NMOS depletion-type transistor M4 has a drain terminal connected to the high-potential supply node 505 of the output range, a source terminal connected to the intermediate node N2, and a gate terminal connected to the input signal IN.

[0071] The first NMOS depletion transistor M1 has a negative threshold voltage (i.e., threshold voltage Vthn_M1), such that the potential difference between the voltage at the output node OUT and the voltage at the intermediate node N2 must be equal to or greater than (less negative than) Vthn_M1 of the first NMOS depletion transistor M1 in order to turn on the first NMOS depletion transistor M1.

[0072] The first PMOS enhancement-mode transistor M2 has a negative threshold voltage (i.e., threshold voltage Vthp_M2), such that the potential difference between the voltage at the first node N1 and the voltage at the intermediate node N2 must be less than (and negative) Vthp_M2 of the first PMOS enhancement-mode transistor M2 in order to turn on the first PMOS enhancement-mode transistor M2.

[0073] The first NMOS enhancement-mode transistor M3 has a positive threshold voltage Vthn_M3, such that the potential difference between the voltage on the first node N1 and the low-potential supply voltage VSS must be equal to or greater than (positively greater than) Vthn_M3 of the first NMOS enhancement-mode transistor M3 in order to turn on the first NMOS enhancement-mode transistor M3.

[0074] The second NMOS depletion-type transistor M4 has a negative threshold voltage (i.e., threshold voltage Vthn_M4), such that the potential difference between the voltage at the input node and the voltage at the intermediate node N2 must be equal to or greater than (less negative than) Vthn_M4 of the second NMOS depletion-type transistor M4 to turn it on. In an embodiment of the circuit, since the first NMOS depletion-type transistor M1 and the second NMOS depletion-type transistor M4 are implemented using the same specified size and the same specified doping concentration, the first NMOS depletion-type transistor M1 and the second NMOS depletion-type transistor M4 have substantially the same threshold voltage (Vthn_M4 = Vthn_M1). In some embodiments, the first NMOS depletion-type transistor M1 and the second NMOS depletion-type transistor M4 have different threshold voltages. In operation, when VIN goes high, this second NMOS depletion-type transistor M4 is used to set a high voltage at the intermediate node N2. During the change, the voltage at the output node OUT remains low, and the high voltage cannot be passed to the intermediate node N2 through the first NMOS depletion-type transistor M1.

[0075] In various embodiments, the low-range low-potential supply node 503 and the output-range low-potential supply node 506 are connected to a VSS that is the same as DC ground or another DC reference voltage. In other embodiments, the low-range low-potential supply node 503 and the output-range low-potential supply node 506 may be connected to AC ground. In the illustrated embodiments, the low-range low-potential supply node 503 and the output-range low-potential supply node 506 are coupled to ground or a 0V reference voltage, or otherwise have the same voltage potential. As mentioned above, in some embodiments, the low-potential supply node may be coupled to a negative voltage.

[0076] In order for the output node OUT to change from a low output potential to a high output potential, when the voltage of the first node N1 changes to a low input potential (0V), the first NMOS enhancement-mode transistor M3 must be turned off, and the second NMOS depletion-mode transistor M4, the first PMOS enhancement-mode transistor M2, and the first NMOS depletion-mode transistor M1 must be turned on.

[0077] For the first PMOS enhancement-mode transistor M2 to turn on, the voltage VN1 of the first node N1 minus the voltage VN2 of the intermediate node N2 must be less than Vthp_M2 or even more negative than Vthp_M2. With this change, the voltage at the input node rises to the high end of the input range, or VDD, and the voltage at the first node N1 falls to the low end of the input range, or zero volts. The second NMOS depletion-mode transistor M4 receives VDD faster than the intermediate node N2, and the voltage at the intermediate node N2, clamped by the second NMOS depletion-mode transistor M4, rises to -Vthn_M4 + VDD. Therefore, for the first PMOS enhancement-mode transistor M2 to turn on, VN1 - VN2 < Vthp_M2 (Equation 6).

[0078] However, the voltage VN1 at the first node N1 is 0V, and the voltage VN2 at the intermediate node N2 is -Vthn_M4 + VDD. Therefore, equation 6 can be interpreted as:

[0079] Vthn_M4-VDD<Vthp_M2 (Equation 7)

[0080] Similarly, in order for the output node OUT to change from a high output potential to a low output potential, the first NMOS enhancement-mode transistor M3 must be turned on, and the second NMOS depletion-mode transistor M4, the first PMOS enhancement-mode transistor M2, and the first NMOS depletion-mode transistor M1 must be turned off.

[0081] To turn off the first PMOS enhancement-mode transistor M2, the voltage VN1 of the first node N1 minus the voltage VN2 of the intermediate node N2 must be greater than or less than Vthp_M2. For this change, the voltage of the first node N1 rises to the high end of the input range, or VDD, and the voltage of the input node drops to the low end of the input range, or 0V, turning off M4. The voltage of the intermediate node N2 starts at HV, but when the first NMOS enhancement-mode transistor M3 is turned on, OUT is pulled low, so the voltage of the intermediate node N2 drops to its minimum value -Vthn_M1. Therefore, to turn off the first PMOS enhancement-mode transistor M2, VN1 - VN2 > Vthp_M2 (Equation 8).

[0082] However, the voltage VN1 at the first node N1 is VDD, and the voltage VN2 at the intermediate node N2 drops to -Vthn_M1. Therefore, equation 8 can be interpreted as follows:

[0083] VDD-(-Vthn_M1)>Vthp_M2 (Equation 9)

[0084] Combining Equations 7 and 9, and setting Vthn_M1 = Vthn_M4, the threshold voltage conditions for the first NMOS depletion-type transistor M1 and the first PMOS enhancement-type transistor M2 are as follows:

[0085] VDD + Vthn_M4 > Vthp_M2 > Vthn_M4 - VDD (Equation 10)

[0086] Therefore, in Figure 5 In the circuit, the threshold voltage Vthp_M2 must be less than (i.e. negative, with a higher absolute value) the sum of the input range high potential (voltage supply VDD) and the threshold voltage Vthp_M4 of the second NMOS depletion transistor M4, and greater than (i.e. a smaller negative value, with a lower absolute value) the threshold voltage of the second NMOS depletion transistor M4 minus the input range high potential (voltage supply VDD).

[0087] Therefore, when setting the threshold voltage of the first PMOS enhancement-mode transistor M2 according to Equation 10, Figure 5 The potential conversion circuit operates.

[0088] For example, assuming VDD is 2.3V and Vthn_M1 and Vthn_M4 are -3V, the design window from Vthp_M2 is 0.7V > Vthp_M2 > -5.3V. With the addition of a PMOS turn-off margin w1 for low leakage current and a turn-on margin w2 for instantaneous speed, the design window becomes -(0.7 + w1) > Vthp_M2 > -(5.3 - w2). In one example, w1 is approximately 1V and w2 is approximately 0.5V. The design window shrinks to: -1.7V > Vthp_M2 > -4.8V, assuming VDD is 2.3V.

[0089] If VDD drops to 1.2V, the design window for Vthp_M2 is -1.8V > Vthp_M2 > -4.2V. With the addition of a PMOS turn-off margin w1 for low leakage current and a turn-on margin w2 for instantaneous speed, the design window becomes -(1.8 + w1) > Vthp_M2 > -(4.2 - w2). In one example, w1 is approximately 1V and w2 is approximately 0.5V. The design window shrinks to: -2.8 > Vthp_M2 > -3.7V. This example is based on Vthn_M1 = -3V. The high and low boundaries of the threshold voltage Vthp_M2 can be shifted by the threshold voltages Vthn_M4 and Vthn_M1.

[0090] Figure 6 Showing something similar to Figure 3 Another embodiment, and has the same component number. Figure 6 and Figure 3 The difference lies in the fact that the source of the first PMOS enhancement-mode transistor M2 is connected to its channel body (arrow 610). This source-to-body connection can also be applied to... Figure 5 The circuit's second NMOS depletion-type transistor, M4, has a source-to-body connection that may affect the threshold voltage.

[0091] While this disclosure has been made public with reference to the detailed preferred embodiments and examples above, it should be understood that these examples are intended to be illustrative rather than limiting. Modifications and combinations will readily occur to those skilled in the art and will fall within the spirit of this disclosure and the scope of the appended claims.

[0092] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A potential conversion circuit for connecting a first signal having an input voltage range having a high input voltage range and an input voltage range having a low input voltage range, to generate a potential-converted output having an output voltage range having a high output voltage range and an output voltage range having a low output voltage range, the output voltage range being greater than the input voltage range, the potential conversion circuit comprising: An NMOS depletion-type transistor includes: One leakage endpoint is connected to a high-potential supply node for the output range; A source pole, connected to an intermediate node; and A gate is connected to an output node; A PMOS enhancement-mode transistor, comprising: Connect the leaky extreme to the output node; One source pole, connected to the intermediate node; and A gate, connected to a first node, the first node receiving the first signal; and An NMOS enhancement-mode transistor, comprising: Connect the leaky extreme to the output node; One source is connected to a low-potential supply node for the output range; and A gate is connected to the first node; A second NMOS depletion-type transistor, comprising: One leakage extreme is connected to the high-potential supply node of this output range; One source pole, connected to the intermediate node; and A gate is connected to the complementary signal of the first signal.

2. The potential conversion circuit according to claim 1, wherein the NMOS depletion-type transistor has a first threshold voltage and the PMOS enhancement-type transistor has a second threshold voltage, the first threshold voltage being less than the second threshold voltage, and the sum of the input range high potential and the first threshold voltage being greater than the second threshold voltage.

3. The potential conversion circuit according to claim 1, wherein the NMOS depletion-type transistor has a first threshold voltage, and the PMOS enhancement-type transistor has a second threshold voltage, and the sum of the input voltage range, the first threshold voltage and a PMOS turn-off threshold voltage is greater than the second threshold voltage, and the sum of the first threshold voltage and a negative turn-on threshold voltage is less than the second threshold voltage.

4. The potential conversion circuit of claim 1, wherein the NMOS depletion-type transistor has a first threshold voltage; and When the first signal changes from a high potential in the input range to a low potential in the input range, the intermediate node changes from a voltage equal to the output low potential minus the first threshold voltage to a high potential in the output range, and the output voltage changes between the low potential and the high potential in the output range; and When the first signal changes from a low potential in the input range to a high potential in the input range, the intermediate node changes from a high potential in the output range to a low potential in the output range minus the first threshold voltage, and the output voltage changes between the low potential in the output range and the high potential in the output range.

5. The potential conversion circuit according to claim 1, wherein: When the first signal changes from a high potential in the input range to a low potential in the input range, the NMOS depletion-type transistor switches from off to on, the PMOS enhancement-type transistor switches from off to on, and the NMOS enhancement-type transistor switches from on to off; and When the first signal changes from a low potential in the input range to a high potential in the input range, the NMOS depletion transistor switches from on to off, the PMOS enhancement transistor switches from on to off, and the NMOS enhancement transistor switches from off to on.

6. The potential conversion circuit of claim 1, wherein the NMOS depletion-type transistor has a first threshold voltage, the PMOS enhancement-type transistor has a second threshold voltage, and the second NMOS depletion-type transistor has a third threshold voltage; and The third threshold voltage plus the high potential of the input range is greater than the second threshold voltage, and the second threshold voltage is greater than the third threshold voltage minus the high potential of the input range.

7. The potential conversion circuit according to claim 6, wherein the first threshold voltage and the third threshold voltage are substantially the same voltage.

8. The potential conversion circuit according to claim 5, wherein the NMOS depletion-type transistor has a first threshold voltage, the PMOS enhancement-type transistor has a second threshold voltage, and the second NMOS depletion-type transistor has a third threshold voltage; When the first signal changes from a high potential in the input range to a low potential in the input range, the intermediate node changes from a voltage equal to the low potential in the output range minus the first threshold voltage to a voltage equal to the high potential in the input range minus the third threshold voltage, and the output voltage changes between the low potential in the output range and the high potential in the output range; and When the first signal changes from a low potential in the input range to a high potential in the input range, the intermediate node changes from a high potential in the output range to a low potential in the output range minus the first threshold voltage, and the output voltage changes from a high potential in the output range to a low potential in the output range.

9. The potential conversion circuit according to claim 5, wherein: When the first signal changes from a high potential in the input range to a low potential in the input range, the NMOS depletion-type transistor and the second NMOS depletion-type transistor switch from off to on, the PMOS enhancement-type transistor switches from off to on, and the NMOS enhancement-type transistor switches from on to off; and When the first signal changes from a low potential in the input range to a high potential in the input range, the NMOS depletion-type transistor and the second NMOS depletion-type transistor switch from being on to being off, the PMOS enhancement-type transistor switches from being on to being off, and the NMOS enhancement-type transistor switches from being off to being on.

10. The potential conversion circuit according to claim 5, wherein the input voltage range is less than 1.5V.

11. The potential conversion circuit according to claim 1, wherein the input voltage range is less than 2.5V.

12. The potential conversion circuit according to claim 1, wherein the input voltage range is less than 2.5V and the output voltage range is greater than 15V.

13. The potential conversion circuit according to claim 1, wherein the input voltage range is less than 2.5V and the output voltage range is greater than 25V.

14. The potential conversion circuit according to claim 1, wherein the low potential of the input range and the low potential of the output range are the same voltage.

15. A potential conversion circuit for generating a potential-converted output having an output voltage range having a high output voltage range and an output voltage range having a low output voltage range, the output voltage range being greater than an input voltage range, the potential conversion circuit comprising: An input gate has an input node connected to an input signal to generate a first signal at a first node, the first signal being a complementary signal to the input signal, the input signal having the input voltage range having an input range high potential and an input range low potential; An NMOS depletion-type transistor includes: One leakage endpoint is connected to a high-potential supply node for the output range; A source pole, connected to an intermediate node; and A gate is connected to an output node; A PMOS enhancement-mode transistor, comprising: Connect the leaky extreme to the output node; One source pole, connected to the intermediate node; and A gate is connected to the first node; An NMOS enhancement-mode transistor, comprising: Connect the leaky extreme to the output node; One source is connected to a low-potential supply node for the output range; and A gate, connected to the first node; and A second NMOS depletion-type transistor, comprising: One leakage extreme is connected to the high-potential supply node of this output range; One source pole, connected to the intermediate node; and A gate is connected to the input signal, wherein When the first signal changes from a high potential in the input range to a low potential in the input range, the NMOS depletion-type transistor switches from off to on, the PMOS enhancement-type transistor switches from off to on, and the NMOS enhancement-type transistor switches from on to off; and When the first signal changes from a low potential in the input range to a high potential in the input range, the NMOS depletion transistor switches from on to off, the PMOS enhancement transistor switches from on to off, and the NMOS enhancement transistor switches from off to on.

16. The potential conversion circuit according to claim 15, wherein: When the first signal changes from a high potential in the input range to a low potential in the input range, the NMOS depletion-type transistor and the second NMOS depletion-type transistor switch from off to on; and When the first signal changes from a low potential in the input range to a high potential in the input range, the NMOS depletion transistor and the second NMOS depletion transistor switch from being on to being off.

17. The potential conversion circuit of claim 15, wherein the input voltage range is less than 1.5V.

18. The potential conversion circuit of claim 15, wherein the input voltage range is less than 2.5V and the output voltage range is greater than 15V.

19. The potential conversion circuit of claim 15, wherein the input gate includes an inverter.

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