An OPA driving circuit based on a shared resistor chain DAC and its driving method

Abstract

The present invention discloses an OPA driving circuit based on a shared resistor chain DAC, belonging to the technical field of optical detection and measurement. It includes a resistor chain, a switch array control module, a sample and hold module, an output stage, and a phase modulation module. One end of the resistor chain is connected to the switch array control module, and the other end of the switch array control module is connected to the input end of the sample and hold module and the output stage. The output end of the sample and hold module and the output stage is connected to the phase modulation module, and the phase modulation module is used to control the deflection phase of the OPA antenna under the control of the driving voltage. By using a shared DAC architecture, the power consumption of the multi-channel OPA driving circuit is reduced, the circuit scale is reduced, hardware resources are saved, and the integratability of the OPA lidar system is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of optical detection and measurement, and particularly relates to an OPA driving circuit based on a shared resistor chain DAC and a driving method thereof. Background Art

[0002] An optical phased array (OPA) lidar system generally consists of a laser light source, an optical phased array chip, a phase control circuit, and an upper computer system. The optical phased array technology adjusts the phase angle of the optical signal emitted by the waveguide through the phase control circuit, so that the lidar system can flexibly achieve the deflection of the scanning beam angle. To achieve the above functions, a dedicated circuit needs to be designed to drive the phase shifter in the optical phased array system. With the expansion of application scenarios and the update and iteration of technologies, large-scale optical phased array technology has become an urgent need in high-performance lidar systems. In this complex system, if multiple digital-to-analog converters (DACs) are used to control the phase of the phase shifter, it will consume a very large amount of hardware resources, increase the difficulty of system integration, and also cause extremely high system power consumption.

[0003] At present, the driving circuits applied to OPA lidars mainly adopt the scheme of multiple DACs; if each OPA unit is driven by one DAC, in a large-scale OPA lidar, a great deal of hardware resources will be required to place multiple DACs, which will cause problems such as large chip size or high system complexity. For traditional resistor-type or capacitor-type DACs, the former is limited by static power consumption. When the resistance value in the resistor chain is too small, there will be a large static power consumption in the circuit, and when the resistance value is too large, it will consume a large circuit area; for capacitor-type DACs, although there is no static power consumption problem, building a capacitor array with unit capacitors that meet the accuracy requirements will also cause the problem of overly large circuit area. Therefore, when multiple DACs based on traditional architectures are applied to large-scale OPA lidar systems, they will all have problems of large area, large consumption of hardware resources, high power consumption, and low energy efficiency. Summary of the Invention

[0004] Aiming at the problems such as the large circuit scale and complexity of the OPA driving circuit of multiple resistor-type DACs in the prior art, the present invention provides an OPA driving circuit based on a shared resistor chain DAC and a driving method thereof. By using a shared DAC architecture, the power consumption of the multiple OPA driving circuit is reduced, the circuit scale is reduced, hardware resources are saved, and the integratability of the OPA lidar system is improved.

[0005] The present invention is realized through the following technical solutions:

[0006] An OPA driving circuit based on a shared resistor chain DAC includes a resistor chain, a switch array control module, a sample and hold module, an output stage, and a phase modulation module; one end of the resistor chain is connected to the switch array control module, and the resistor chain is used to provide N node voltages for all DAC channels; the switch array control module is used to connect each voltage node in the resistor chain to the sample and hold circuit module, and under the control of external data, realize the conduction and closing of each path; the other end of the switch array control module is connected to the input end of the sample and hold module and the output stage, and the sample and hold module and the output stage are used to sample, hold and output the voltage value output by the switch array control module; the output end of the sample and hold module and the output stage is connected to the phase modulation module, and the phase modulation module is used to control the deflection phase of the OPA antenna under the control of the driving voltage.

[0007] Further, the resistor chain is composed of N + 1 resistors connected in series, N is a positive integer, one end of the first resistor is grounded, and one end of the (N + 1)th resistor is connected to the power supply voltage; among them, the node between the first resistor and the second resistor is connected to port A1 of the switch array control module; the node between the second resistor and the third resistor is connected to port A2 of the switch array control module,..., and the node between the Nth resistor and the (N + 1)th resistor is connected to port A N connection.

[0008] Further, the switch array control module includes an input port, an output port, a switch array, and a data configuration and writing module; the input port is connected to one end of the corresponding switch in the switch array, and the output port is connected to the other end of the corresponding switch in the switch array; the data configuration and writing module is connected to the switch array and is used to output switch control codes to control the switches in the switch array.

[0009] Further, the switch array is composed of M×N switches. The M switches in each row are used to represent the connection relationship between a group of input ports and M output ports, and the N switches in each column are used to represent the connection relationship between N groups of input ports and one output port.

[0010] Further, the input port is composed of N groups of ports, and each group of interfaces contains M signal lines, M is a positive integer; the first group of input ports A1<0:M - 1> are respectively connected to the switches S 1_0 , S 1_1 , ……, S 1_M-1 at one end; the second group of input ports A2<0:M - 1> are respectively connected to the switches S 2_0 , S 2_1 , ……, S 2_M-1 at one end; ……; the Nth group of input ports A N<0:M-1> are respectively connected to one ends of switches S N_0 , S N_1 , ……, S N_M-1 ; the output port is composed of M signals. The first signal B<0> is connected to the other ends of switches S 1_0 , S 2_0 , ……, S N_0 ; the second signal B<1> is connected to the other ends of switches S 1_1 , S 2_1 , ……, S N_1 ; ……; the Mth signal B <m-1>Connected to the other ends of switches S in the switch array 1_M-1 , S 2_M-1 , ……, S N_M-1 respectively.

[0011] Furthermore, the sample and hold module and the output stage include an output stage timing control module, M sample and hold circuits, and corresponding drivers; one ends of the M sample and hold circuits are respectively and correspondingly connected to M output ports of the switch array control module, and the other ends of the M sample and hold circuits are respectively connected to their corresponding drivers; the output stage timing control module is respectively connected to control ports in the M sample and hold circuits, and is used to control the working timing of the sample and hold circuits to perform sample and hold operations on the voltage values output by the switch array control module.

[0012] Furthermore, the phase modulation module includes M phase modulators and OPA transmitting units; one ends of the M phase modulators are respectively connected to the output ends of the corresponding drivers, and the other ends of the M phase modulators are respectively connected to the corresponding OPA transmitting units.

[0013] On the other hand, the present invention also provides a driving method for an OPA driving circuit based on a shared resistor chain DAC, specifically including the following steps:

[0014] Step 1: The resistors in the resistor chain complete voltage division statically, and distribute N-level voltages to N nodes;

[0015] Step 2: Write the DAC control word required for the first working cycle into the register of the data configuration and writing module;

[0016] Step 3: The data configuration and writing module inputs the switch control code to the control port S of the switch array. At the beginning of the first working cycle, according to the switch control code, complete the conduction operation of switches S i_0 , S j_1 , …… S k_M-1 , where i, j, k are positive integers less than or equal to N; transfer the node voltages V i , V j , …… V k of the corresponding nodes i, j, …… k in the resistor chain to the output ports B<0>, B<1>, …… B <m-1>in;

[0017] Step Four: Under the control of the sampling clock, the sample and hold circuit samples B<0>, B<1>, …… B at the rising edge of the sampling clock <m-1>Sample the voltage in the port so that its output port is V out <0>, V out <1>, …… V out <m-1>respectively maintain the sampled voltage states V i ,V j ,……V k ; After passing through the corresponding driver, this group of voltage values is input to the phase modulation module to regulate the phase of the OPA;

[0018] Step Five: Write the DAC control word required for the second working cycle into the register in the data configuration and writing module, and then repeat the working process of Step Three to Step Four to make the output ports V out <0>, V out <1>, ……V out <m-1>respectively maintain the sampled voltage states V l , V m , ……V n ; This set of voltage values is input to the phase modulation module through the driver to regulate the phase of the OPA; Then continue to repeat the working process of steps two to four.

[0019] Compared with the prior art, the advantages of the present invention are as follows:

[0020] The OPA driver circuit based on the shared resistor chain DAC proposed by the present invention adopts the method of multiple DACs sharing the resistor chain, provides the voltage of each node in the resistor chain to the output ends of each path of DACs in parallel, controls the on-off of the path from each node in the resistor chain to the DAC output end through the switch array, and then cooperates with modules such as the multiple sampling and holding circuit, the driver, and the phase shifter to achieve the functional effect of a fully parallel multi-channel DAC driver circuit with very small resistor and capacitor resources;

[0021] This driver circuit reduces the circuit area consumed by multiple DACs. No matter how large the scale of the OPA to be driven is, the fully parallel signal conversion function of multiple DACs can be achieved by sharing a single resistor chain, and then the high-speed regulation of multiple OPAs can be realized. At the same time, based on the typical resistor-type DAC, the method of multiple DACs sharing a single resistor chain also reduces the static power consumption, can significantly reduce the overall power consumption, improve the energy efficiency of the system, and is beneficial to the system integration of large-scale OPA chips and driver circuits. Description of the Drawings

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0023] Figure 1 is the architecture diagram of the OPA driver circuit based on the shared resistor chain DAC;

[0024] Figure 2 is the schematic diagram of the connection relationship of the switch array;

[0025] Figure 3 is the working timing diagram of the OPA driver circuit. Specific Embodiments

[0026] To clearly and completely describe the technical solutions of the present invention and their specific working processes, in combination with the drawings in the specification, the specific embodiments of the present invention are as follows:

[0027] Embodiment 1

[0028] This embodiment provides an OPA driving circuit based on a shared resistor chain DAC, including a resistor chain, a switch array control module, a sample and hold module, an output stage, and a phase modulation module; one end of the resistor chain is connected to the switch array control module, and the resistor chain is used to provide N node voltages for all DAC channels; the switch array control module is used to connect each voltage node in the resistor chain to the sample and hold circuit module, and under the control of external data, realize the conduction and closing of each path; the other end of the switch array control module is connected to the input end of the sample and hold module and the output stage, and the sample and hold module and the output stage are used to sample, hold and output the voltage value output by the switch array control module; the output end of the sample and hold module and the output stage is connected to the phase modulation module, and the phase modulation module is used to control the deflection phase of the OPA antenna under the control of the driving voltage.

[0029] In this embodiment, the resistor chain is composed of N + 1 resistors connected in series, where N is a positive integer. One end of the first resistor is grounded, and one end of the (N + 1)th resistor is connected to the power supply voltage; among them, the node between the first resistor and the second resistor is connected to port A1 of the switch array control module; the node between the second resistor and the third resistor is connected to port A2 of the switch array control module,..., and the node between the Nth resistor and the (N + 1)th resistor is connected to port A N connection.

[0030] In this embodiment, N voltage nodes in the resistor chain are respectively connected to N groups of input ports in the switch array control module; M output ports of the switch array control module are connected to the input ends of M sample and hold circuits in the sample and hold module and the output stage; the output ends of M drivers in the sample and hold module and the output stage are connected to the input ends of M phase modulators in the phase modulation module.

[0031] In this embodiment, the switch array control module includes an input port, an output port, a switch array, and a data configuration and writing module; the input port is connected to one end of the corresponding switch in the switch array, and the output port is connected to the other end of the corresponding switch in the switch array; the data configuration and writing module is connected to the switch array and is used to output switch control codes to control the switches in the switch array.

[0032] As Figure 2 shown, the switch array is composed of M × N switches. The M switches in each row are used to represent the connection relationship between a group of input ports and M output ports, and the N switches in each column are used to represent the connection relationship between N groups of input ports and one output port;

[0033] The input port is composed of N groups of ports, namely A1<0>-A N <0>, each group of interfaces includes M signal lines, where M is a positive integer; the first group of input ports A1<0:M-1> are respectively connected to one ends of switches S 1_0 , S 1_1 , ……, S 1_M-1 ; the second group of input ports A2<0:M-1> are respectively connected to one ends of switches S 2_0 , S 2_1 , ……, S 2_M-1 ; ……; the Nth group of input ports A N <0:M-1> are respectively connected to one ends of switches S N_0 , S N_1 , ……, S N_M-1 ; the output port is composed of M signals. The first signal B<0> is connected to the other ends of switches S 1_0 , S 2_0 , ……, S N_0 ; the second signal B<1> is connected to the other ends of switches S 1_1 , S 2_1 , ……, S N_1 ; ……; the Mth signal B <m-1>is connected to the other ends of the switches S 1_M-1 , S 2_M-1 , ……, S N_M-1 ; the other ends of the switches S 1_0 , S 2_0 …… S N_0 ; S 1_1 , S 2_1 …… S N_1 ; …… S 1_M-2 , S 2_M-2 …… S N_M-2 ; S 1_M-1 , S 2_M-1 …… S N_M-1 are respectively controlled by the control ports S<0>, S<1>, S<2>…… S<M×N - 2>, S<M×N - 1>.

[0034] In this embodiment, the sampling and holding and output stage module includes an output stage timing control module, M sampling and holding circuits, and corresponding drivers; one ends of the M sampling and holding circuits are respectively and correspondingly connected to M output ports of the switch array control module, and the other ends of the M sampling and holding circuits are respectively connected to their corresponding drivers; the output stage timing control module is respectively connected to the control ports in the M sampling and holding circuits, and is used to control the working timing of the sampling and holding circuits to perform sampling and holding operations on the voltage values output by the switch array control module.

[0035] Specifically, the input end of the first sampling and holding circuit is connected to the output port B<0> in the switch array control module, and the output end outputs a signal Vout<0>; the input end of the second sampling and holding circuit is connected to the output port B<1> in the switch array control module, and the output end outputs a signal Vout<1>; …… the input end of the (M - 1)th sampling and holding circuit is connected to the output port B <m-2>Connect, and the output terminal outputs the signal Vout <m-2>; The input end of the Mth sample-and-hold circuit is connected to output port B in the switch array control module <m-1>Connect, and the output terminal outputs the signal Vout <m-1>Furthermore, the output signal Vout<1> is connected to the input terminal of driver 1; the output signal Vout<2> is connected to the input terminal of driver 2;... the output signal Vout <m-2>Connected to the input terminal of driver M-2; output signal Vout <m-1>Connect to the input terminal of driver M-1.

[0036] The phase modulation module is composed of M phase modulators and OPA transmitting units. The control terminal of the first phase modulator is connected to the output terminal of driver M-1 in the sample and hold and output stage module; the control terminal of the second phase modulator is connected to the output terminal of driver M-2 in the sample and hold and output stage module;... the control terminal of the (M-1)th phase modulator is connected to the output terminal of driver M-2 in the sample and hold and output stage module; the control terminal of the Mth phase modulator is connected to the output terminal of driver M-1 in the sample and hold and output stage module; the other ends of the M phase modulators are respectively connected to the corresponding OPA transmitting units.

[0037] Embodiment 2

[0038] According to Figure 3 the working timing diagram of the OPA driving circuit shown, this embodiment provides an OPA parallel driving method based on a shared resistor chain, and its process is divided into the following steps:

[0039] Step 1: The resistors in the resistor chain complete voltage division statically, and distribute N-level voltages to N nodes.

[0040] Step 2: Write the DAC control word required for the first working cycle into the register of the data configuration and writing module.

[0041] Step 3: The data configuration and writing module inputs the switch control code to the switch array control port S. At the beginning of the first working cycle, according to the switch control code, complete the conduction operation of switches S i_0 S j_1 ,... S k_M-1 (i, j, k are positive integers less than or equal to N), and transfer the node voltages V i , V j ,... V k of the corresponding nodes i, j,... k in the resistor chain to the output ports B<0>, B<1>,... B <m-1>in (such as Figure 3 shown as the working timing);

[0042] Step 4: Under the control of the sampling clock, the sample-and-hold circuit samples B<0>, B<1>, …… B <m-1>Sample the voltage in the port to make the output port V out <0>, V out <1>, …… V out <m-1>respectively maintain the sampled voltage states V i , V j , ……V k ; The set of voltage values is input to the phase modulation module through the driver to regulate the phase of the OPA;

[0043] Step Five: Write the DAC control word required for the second working cycle into the register in the data configuration and writing module, and then repeat the working process of Step Three to Step Four to make the output ports V out <0>, V out <1>, ……V out <m-1>respectively maintain the sampled voltage states V l , V m , ……V n ; This set of voltage values is input to the phase modulation module through the driver to regulate the phase of the OPA. Then continue to repeat the working process of steps two to four.

[0044] The preferred embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0045] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

[0046] Furthermore, any combination can be made between different embodiments of the present invention, as long as it does not violate the idea of the present invention, it should also be regarded as the content disclosed by the present invention.

Claims

1. An OPA driving circuit based on a shared resistor chain DAC, characterized in that It includes a resistor chain, a switch array control module, a sample and hold module, an output stage and a phase modulation module; one end of the resistor chain is connected to the switch array control module, and the resistor chain is used to provide N node voltages for all DAC channels; the switch array control module is used to connect each voltage node in the resistor chain to the sample and hold circuit module, and under the control of external data, realize the conduction and closing of each path; the other end of the switch array control module is connected to the input end of the sample and hold module and the output stage, and the sample and hold module and the output stage are used to sample, hold and output the voltage value output by the switch array control module; the output end of the sample and hold module and the output stage is connected to the phase modulation module, and the phase modulation module is used to control the deflection phase of the OPA antenna under the control of the driving voltage; Among them, the sample and hold module and the output stage include an output stage timing control module, M sample and hold circuits and corresponding drivers; one ends of the M sample and hold circuits are respectively connected to M output ports of the switch array control module, and the other ends of the M sample and hold circuits are respectively connected to their corresponding drivers; the output stage timing control module is respectively connected to the control ports in the M sample and hold circuits, and is used to control the working timing of the sample and hold circuits to sample and hold the voltage value output by the switch array control module.

2. The OPA driving circuit based on a shared resistor chain DAC according to claim 1, characterized in that The resistor chain is composed of N + 1 resistors connected in series, where N is a positive integer. One end of the first resistor is grounded, and one end of the (N + 1)-th resistor is connected to the power supply voltage. Among them, the node between the first resistor and the second resistor is connected to port A1 of the switch array control module; the node between the second resistor and the third resistor is connected to port A2 of the switch array control module, ……, the node between the N-th resistor and the (N + 1)-th resistor is connected to port A N connection.

3. The OPA driving circuit based on a shared resistor chain DAC according to claim 1, characterized in that The switch array control module includes an input port, an output port, a switch array and a data configuration and writing module; the input port is connected to one end of the corresponding switch in the switch array, and the output port is connected to the other end of the corresponding switch in the switch array; the data configuration and writing module is connected to the switch array and is used to output switch control codes to control the switches in the switch array.

4. The OPA driving circuit based on a shared resistor chain DAC according to claim 3, characterized in that The switch array is composed of M×N switches. The M switches in each row are used to represent the connection relationship between a group of input ports and M output ports, and the N switches in each column are used to represent the connection relationship between N groups of input ports and one output port.

5. The OPA driving circuit based on a shared resistor chain DAC according to claim 3, characterized in that The input port is composed of N groups of ports, and each group of interfaces includes M signal lines, where M is a positive integer; the first group of input ports A1<0:M - 1> are respectively connected to the switches S 1_0 , S 1_1 , ……, S 1_M-1 at one end; the second group of input ports A2<0:M - 1> are respectively connected to the switches S 2_0 , S 2_1 , ……, S 2_M-1 at one end; ……; the Nth group of input ports A N <0:M - 1> are respectively connected to the switches S N_0 , S N_1 , ……, S N_M-1 at one end; the output port is composed of M signals, the first signal B<0> is connected to the switches S 1_0 , S 2_0 , ……, S N_0 at the other end; the second signal B<1> is connected to the switches S 1_1 , S 2_1 , ……, S N_1 at the other end; ……; the Mth signal B <m-1>is connected to the other end of switch S in the switch array 1_M-1 , S 2_M-1 , ……, S N_M-1 .

6. The OPA driving circuit based on a shared resistor chain DAC according to claim 1, characterized in that The phase modulation module includes M phase modulators and an OPA transmitting unit; one ends of the M phase modulators are respectively connected to the output ends of the corresponding drivers, and the other ends of the M phase modulators are respectively connected to the corresponding OPA transmitting units.

7. A driving method for the OPA driving circuit based on a shared resistor chain DAC according to claim 1, specifically including the following steps: Step 1: The resistors in the resistor chain complete voltage division statically, and distribute N-level voltages to N nodes; Step 2: Write the DAC control word required for the first working cycle into the register of the data configuration and writing module; Step 3: The data configuration and writing module inputs the switch control code to the control port S of the switch array. At the beginning of the first working cycle, according to the switch control code, complete the conduction operation of switches S i_0 , S j_1 , …… S k_M-1 , where i, j, k are positive integers less than or equal to N; the node voltages V i , V j , …… V k are respectively transmitted to the output ports B<0>, B<1>, …… B <m-1>in;< / m-1> Step 4: Under the control of the sampling clock, the sample-and-hold circuit samples B<0>, B<1>, …… B at the rising edge of the sampling clock <m-1>Sample the voltage at the port so that its output port is V out <0>, V out <1>, …… V out <m-1>respectively hold the sampled voltage states V i , V j , …… V k ; This group of voltage values are input to the phase modulation module after passing through the corresponding drivers to regulate the phase of the OPA; Step 5: Write the DAC control word required for the second working cycle into the register in the data configuration and writing module, and then repeat the working process of Steps 3 to 4 to make the output ports V out <0>, V out <1>, …… V out <m-1>respectively maintain the sampled voltage states V l , V m , …… V n ; this set of voltage values is input to the phase modulation module through the driver to regulate the phase of the OPA; then continue to repeat the working process of steps two to four.

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