Variable gain pixel unit circuit, HDR image sensor

Abstract

The present invention discloses a variable gain pixel unit circuit and an HDR image sensor. The circuit includes: a photodiode, a transmission tube, a reset tube, a source follower tube, and a gain control unit. The gain control unit includes a first control tube, a second control tube, and an anti-overflow capacitor. The drain of the first control tube is connected to the source of the reset tube, and the source of the second control tube is connected to the anti-overflow capacitor. The drain of the transmission tube, the gate of the source follower tube, the source of the first control tube, and the drain of the second control tube are respectively connected to a suspended drain. The gate of the transmission tube serves as the signal input terminal of the pixel unit, and the source of the source follower tube serves as the signal output terminal of the pixel unit. The gate of the first control tube serves as the first control terminal, and the gate of the second control tube serves as the second control terminal. Utilizing the present invention, the pixel unit can be switched between different gains, so that the pixel unit can obtain better response characteristics under different illumination conditions.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a variable gain pixel unit circuit and an HDR image sensor. Background Art

[0002] CMOS image sensors (CIS) are widely used in various fields such as consumer electronics, surveillance and security, and mobile phones. In order to ensure the performance of image sensors under different lighting conditions, people have put forward requirements for the dynamic range of CIS. For this reason, HDR (High Dynamic Range) CIS has emerged in the industry.

[0003] A common implementation of HDR CIS uses a pixel circuit with variable conversion gain. By using a lower conversion gain for bright images and a higher conversion gain for darker images, the voltage of the useful signal is ensured to fall within the sensor's quantifiable range. Depending on the number of conversion gains in the pixel circuit, these methods are categorized as dual conversion gain (DCG) and triple conversion gain (TCG). These implementations sequentially read out data at different conversion gains and piece together multiple sets of data to create an HDR image, allowing the HDR image to display both bright and dark areas of the image with higher quality. The DCG method requires reading out two sets of reference values ​​and two sets of signal values, while the TCG method requires reading out three sets of reference values ​​and three sets of signal values. Summary of the Invention

[0004] On one hand, an embodiment of the present invention provides a variable gain pixel unit circuit, which can realize the switching of the pixel unit between different gains, so that the pixel unit can obtain better response characteristics under different illumination conditions, thereby obtaining high-quality images.

[0005] On the other hand, an embodiment of the present invention further provides an HDR image sensor, which can better meet the requirements of CMOS image sensors for high sensitivity and large dynamic range.

[0006] To this end, the embodiments of the present invention provide the following technical solutions:

[0007] An embodiment of the present invention provides a variable-gain pixel unit circuit, comprising: a photodiode PD, a transmission tube TG, a reset tube RG, a source follower tube SG, and a gain control unit; the gain control unit comprises a first control tube CG1, a second control tube CG2, and an anti-overflow capacitor C2; the drain of the first control tube CG1 is connected to the source of the reset tube RG, and the source of the second control tube CG2 is connected to the anti-overflow capacitor C2; the drain of the transmission tube TG, the gate of the source follower tube SG, the source of the first control tube CG1, and the drain of the second control tube CG2 are respectively connected to a floating drain;

[0008] The gate of the transmission tube TG is the signal input terminal of the pixel unit, and the source of the source follower tube SG is the signal output terminal of the pixel unit;

[0009] The gate of the first control tube CG1 is the first control terminal DCG, and the gate of the second control tube CG2 is the second control terminal TCG. The first control terminal DCG and the second control terminal TCG are used to input control signals.

[0010] Optionally, the first control transistor CG1 and the second control transistor CG2 are both NMOS transistors.

[0011] Optionally, the reset transistor RG, the transmission transistor TG and the source follower transistor SG are all NMOS transistors.

[0012] Optionally, the source of the transmission tube TG is connected to the cathode of the photodiode PD.

[0013] Optionally, the drain of the source follower tube SG is connected to the first power supply voltage; the drain of the reset tube RG is connected to the second power supply voltage, and the gate of the reset tube RG is connected to the reset control signal.

[0014] Optionally, the first control terminal DCG and the second control terminal TCG are used to apply voltage biases of different magnitudes to the first control tube CG1 and the second control tube CG2 so that the floating drain has a variety of different capacitance values ​​to enable the pixel unit to switch between a variety of different conversion gains.

[0015] Optionally, there are three combinations of voltages at the first control terminal DCG and the second control terminal TCG, namely:

[0016] The first control terminal DCG and the second control terminal TCG are both at low level;

[0017] The first control terminal DCG and the second control terminal TCG are both at high level;

[0018] The first control terminal DCG is at a high level, and the second control terminal TCG is at a low level.

[0019] An embodiment of the present invention further provides an HDR image sensor, comprising a pixel array unit composed of the aforementioned variable gain pixel unit circuit, a driving circuit connected to each of the pixel array units, an analog-to-digital conversion array, and a signal processing unit connected to the analog-to-digital conversion array;

[0020] The driving circuit is used to output a control signal to the first control terminal DCG and the second control terminal TCG of the variable gain pixel unit circuit;

[0021] The analog-to-digital conversion array is used to convert the analog signal output by the variable gain pixel unit circuit into a digital signal and output the digital signal;

[0022] The signal processing unit is used to process the digital signal output by the analog-to-digital conversion array.

[0023] Optionally, the HDR image sensor further includes:

[0024] a judgment unit, configured to judge the voltage of the floating drain and output a judgment result to the driving circuit;

[0025] The driving circuit is further configured to apply different bias voltages to the first control terminal DCG and the second control terminal TCG according to the judgment result.

[0026] Optionally, the judgment unit is a comparator, and the comparator inputs a first reference voltage and a second reference voltage;

[0027] If V PXD >V ref2 , the driving circuit controls the first control terminal DCG and the second control terminal TCG to be high level;

[0028] If V ref1 <V PXD <V ref2 , the driving circuit controls the first control terminal DCG to be a high level and the second control terminal TCG to be a low level;

[0029] If V PXD <V ref1 , the driving circuit controls the first control terminal DCG and the second control terminal TCG to be low level;

[0030] Among them, V PXD is the signal output terminal voltage of the pixel unit, V ref1 is the first reference voltage, V ref2 is the second reference voltage.

[0031] The variable gain pixel unit circuit provided in an embodiment of the present invention utilizes different voltage configuration combinations of the first control tube and the second control tube to enable the floating drain of the transmission tube to form a variety of different capacitance values, making it adaptable to a variety of different illumination conditions, so that the pixel unit can obtain better response characteristics under different illumination conditions, thereby obtaining high-quality images.

[0032] Accordingly, the HDR image sensor provided by the embodiment of the present invention, including the variable gain pixel unit circuit, can obtain high-quality images and better meet the requirements of CMOS image sensors for high sensitivity and large dynamic range.

[0033] Furthermore, by adding a judgment unit to the HDR image sensor to judge the voltage of the floating drain, the driver circuit can apply corresponding bias voltages to the first control terminal and the second control terminal based on the judgment result, effectively reducing the number of image signal readouts and improving data processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic structural diagram of a variable gain pixel unit circuit according to an embodiment of the present invention;

[0035] Figure 2 This is a schematic structural diagram of a variable gain pixel unit circuit according to an embodiment of the present invention;

[0036] Figure 3 This is a schematic structural diagram of an HDR image sensor according to an embodiment of the present invention;

[0037] Figure 4 yes Figure 3 A signal timing diagram of an HDR image sensor having the structure shown;

[0038] Figure 5 1 is another structural diagram of an HDR image sensor according to an embodiment of the present invention;

[0039] Figure 6 yes Figure 5 Signal timing diagram in the HDR image sensor with the shown structure. DETAILED DESCRIPTION

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] like Figure 1 FIG. 1 is a schematic structural diagram of a variable gain pixel unit circuit according to an embodiment of the present invention.

[0042] The variable gain pixel unit circuit includes: a photodiode PD, a transmission tube TG, a reset tube RG, a source follower tube SG and a gain control unit. The gain control unit includes a first control tube CG1, a second control tube CG2, and an anti-overflow capacitor C2; the drain of the first control tube CG1 is connected to the source of the reset tube RG, and the source of the second control tube CG2 is connected to the anti-overflow capacitor C2; the drain of the transmission tube TG, the gate of the source follower tube SG, the source of the first control tube CG1, and the drain of the second control tube CG2 are respectively connected to the floating drain, that is, Figure 1 Node FD in.

[0043] The gate of the transmission tube TG is the signal input terminal of the pixel unit, which is used to input the image signal; the source of the source follower tube SG is the signal output terminal of the pixel unit, which is used to output the image signal.

[0044] In a non-limiting application, the first control transistor CG1 and the second control transistor CG2 are both NMOS transistors, such as Figure 1 Correspondingly, the reset transistor RG, the transmission transistor TG and the source follower transistor SG can also be NMOS transistors.

[0045] like Figure 1 As shown, the source of the transmission tube TG is connected to the cathode of the photodiode PD, and the gate of the transmission tube TG inputs the transmission control signal TX.

[0046] Correspondingly, the drain of the source follower transistor SG is connected to the first power supply voltage VDD1; the drain of the reset transistor RG is connected to the second power supply voltage VDD2, and the gate of the reset transistor RG is connected to the reset control signal RST. Figure 1 In the illustrated embodiment, the reset control signal RST is a positive pulse signal.

[0047] It should be noted that, depending on application requirements and the types of MOS transistors used, the first power supply voltage VDD1 and the second power supply voltage VDD2 may be the same or different, which is not limited in this embodiment of the present invention.

[0048] The photodiode PD is used to convert photons into electrons, and the transmission tube TG is used to transfer the electrons in the photodiode PD to the suspended drain FD. The suspended drain FD converts the charge signal into a voltage signal and amplifies and outputs it through the source follower tube SG.

[0049] Because the capacitance of the floating drain FD determines the conversion gain of the pixel unit, in an embodiment of the present invention, a first control transistor CG1 and a second control transistor CG2 are connected to the floating drain FD. The gate of the first control transistor CG1 is the first control terminal DCG, and the gate of the second control transistor CG2 is the second control terminal TCG. The first control terminal DCG and the second control terminal TCG are used to input control signals. Specifically, by applying different voltage biases to the first control terminal DCG and the second control terminal TCG, the capacitance of the two control transistors can be changed. Since the capacitance of the two control transistors is connected in parallel with the floating drain capacitance, the total capacitance of the floating drain FD can be varied by changing the capacitance of the control transistors, resulting in a variety of different capacitance values. This enables the pixel unit to switch between different conversion gains. This allows the pixel unit to select between different conversion gains in response to different lighting environments, enabling the image sensor to switch to a sensitivity and dynamic range that is appropriate for the lighting environment. Conversion gain refers to the ratio of electrons to voltage. A higher conversion gain results in a higher sensitivity and a smaller dynamic range for the image transmitter; conversely, a lower conversion gain results in a lower sensitivity and a larger dynamic range for the image transmitter.

[0050] In a non-limiting specific application, the voltage bias of the first control terminal DCG and the second control terminal TCG can be combined in the following three ways:

[0051] (1) The first control terminal DCG and the second control terminal TCG are both at low levels, denoted as: DCG = 0, TCG = 0;

[0052] (2) The first control terminal DCG and the second control terminal TCG are both at high levels, which is recorded as: DCG = 1, TCG = 1;

[0053] (3) The first control terminal DCG is at a high level and the second control terminal TCG is at a low level, which is recorded as: DCG=1, TCG=0.

[0054] Accordingly, under the above-mentioned voltage bias (1), capacitors C1 and C2 are not connected, and the total capacitance of the floating drain FD is the smallest; under the above-mentioned voltage bias (2), capacitors C1 and C2 are both connected, and the total capacitance of the floating drain FD is the largest; under the above-mentioned voltage bias (3), capacitor C1 is connected and C2 is not connected, and the total capacitance of the floating drain FD is between the above-mentioned two cases (1) and (2).

[0055] It should be noted that if Figure 1As shown, the capacitor C1 is the capacitor between the drain of the first control tube DCG and the ground. In specific applications, the capacitor C1 can be an external capacitor or a parasitic capacitor, which is not limited in this embodiment of the present invention. When the capacitor C1 is connected to the FD point, the conversion gain of the circuit can be changed, thereby improving the dynamic range. Similarly, the capacitor C2 can also improve the dynamic range by changing the conversion gain of the FD point. In addition, during the exposure process, the capacitor C2 can be connected to absorb the overflow electrons during the exposure process, further improving the dynamic range.

[0056] The variable gain pixel unit circuit provided in an embodiment of the present invention utilizes different voltage configuration combinations of the first control tube and the second control tube to enable the floating drain of the transmission tube to form a variety of different capacitance values, making it adaptable to a variety of different illumination conditions, so that the pixel unit can obtain better response characteristics under different illumination conditions, thereby obtaining high-quality images.

[0057] Further, if Figure 2 As shown, in another non-limiting embodiment of the variable-gain pixel unit circuit of the present invention, the variable-gain pixel unit circuit may further include a row select transistor LG connected to the source of the source follower transistor SG, for controlling the output of the voltage signal for each row of the pixel unit. The row select transistor LG may be an NMOS transistor, with its drain connected to the source of the source follower transistor SG, its source serving as the output terminal PXD of the pixel unit, and its gate receiving the row select control signal SEL.

[0058] Correspondingly, an embodiment of the present invention further provides a chip, comprising the variable gain pixel unit circuit of each of the above embodiments.

[0059] Correspondingly, an embodiment of the present invention further provides an HDR image sensor, comprising the above-mentioned variable gain pixel unit circuit.

[0060] like Figure 3 FIG. 1 is a schematic structural diagram of an HDR image sensor according to an embodiment of the present invention.

[0061] In this embodiment, the HDR image sensor includes: a pixel array unit 100 composed of variable gain pixel unit circuits, a driving circuit 101 connected to the pixel array unit 100, an analog-to-digital conversion array 102, and a signal processing unit 103 connected to the analog-to-digital conversion array 102.

[0062] The driving circuit 101 is used to output a control signal to the first control terminal DCG and the second control terminal TCG of the variable gain pixel unit circuit;

[0063] The analog-to-digital conversion array 102 is used to convert the analog signal output by the variable gain pixel unit circuit into a digital signal and output it;

[0064] The signal processing unit 103 is configured to process the digital signal output by the analog-to-digital conversion array 102 .

[0065] In this embodiment, the driving circuit 101 can change the level of the output control signal to change the Figure 1 The capacitance of the control tube in the variable gain pixel unit circuit changes the total capacitance of the suspended drain FD so that it has a variety of different capacitance values, thereby enabling the pixel unit to switch between a variety of different conversion gains.

[0066] In specific applications, it is necessary to read the voltage value output by the output terminal PXD of the variable gain pixel unit circuit, including the reference voltage and signal voltage under different control states, so that the signal processing unit 103 can obtain the actual pixel value of each pixel unit according to the corresponding reference voltage and signal voltage.

[0067] It should be noted that, in actual applications, the signal to be read is the voltage value output by the output terminal PXD of the variable gain pixel unit circuit. Since the voltage value output by the output terminal PXD of the variable gain pixel unit circuit has a certain correspondence with the voltage value of the node FD, in order to facilitate understanding of the scheme of the present invention in the following description, the read voltage signal will be directly described as the voltage of the read node FD.

[0068] Figure 4 Shown Figure 3 A signal timing diagram of the HDR image sensor with the structure shown below is also referred to Figure 3 and Figure 4 The specific process of timing control in this embodiment is as follows:

[0069] 1) At time t1, the reset transistor RG is turned on to perform a reset operation. During time period ①, the transmission transistor TG is turned on once. At the same time, since the first control transistor CG1 and the second control transistor CG2 are in the on state, the capacitor C1 and the node FD are reset.

[0070] 2) After the reset transistor RG is turned off at time t2, the voltage R3 (reference voltage, LOW DCG + LOW TCG) at node FD is read during time period ②.

[0071] 3) At time t3, the first control tube CG1 is turned off, and the exposure operation is performed in time period ③. During this process, the second control tube CG2 is turned on, so the photoelectrons overflowing under strong light will be collected on the capacitor C2;

[0072] 4) At time t4, the second control tube CG2 is turned off, and then the first control tube CG1 is turned on;

[0073] 5) At time t5, the reset transistor RG is turned on to perform a reset operation. At this time, since only the first control transistor CG1 is turned on, the capacitor C1 and the node FD are reset.

[0074] 6) After reset is complete, the reference voltage R2 (reference voltage, Low DCG + High TCG) of node FD is read during time period ⑤.

[0075] 7) At time t6, the first control transistor CG1 is turned off, and then the voltage R1 (reference voltage, High DCG + High TCG) of the node FD is read during time period ⑥.

[0076] 8) During time period ⑦, the transmission transistor TG is turned on once, and after the transmission transistor TG is turned off, the voltage S1 (signal voltage, High DCG + High TCG) of the node FD at this time is read;

[0077] 9) At time t8, the first control transistor CG1 is turned on, and the transmission transistor TG is turned on again within time period ⑧. The voltage S2 (signal voltage, LOW DCG + HIGH TCG) at the node FD is then read.

[0078] 10) At time t9, the second control transistor CG2 is turned on, and the transmission transistor TG is turned on for the third time within time period ⑨. The voltage S3 (signal voltage, LOW DCG + LOW TCG) at the node FD at this time is read.

[0079] 11) At time t10, the reset transistor RG will turn on again to perform the reset operation of the next row.

[0080] The HDR image sensor provided by the embodiment of the present invention, including the variable gain pixel unit circuit, can obtain high-quality images and better meet the requirements of CMOS image sensors for high sensitivity and large dynamic range.

[0081] like Figure 5 , which is another structural schematic diagram of an HDR image sensor according to an embodiment of the present invention.

[0082] and Figure 3 The difference from the illustrated embodiment is that, in this embodiment, the HDR image sensor further includes: a judgment unit 104 , configured to judge the voltage of the floating drain FD and output the judgment result to the driving circuit 101 .

[0083] Accordingly, in this embodiment, the driving circuit 101 is further configured to apply different bias voltages to the first control terminal DCG and the second control terminal TCG based on the determination result. That is, in this embodiment, when applying the bias voltages to the first control terminal DCG and the second control terminal TCG, the driving circuit 101 also considers the current voltage of the floating drain FD.

[0084] It should be noted that the above judgment process is performed after the reference signal is read, ie, after the exposure is completed, and the driving circuit 101 controls the levels of the first control terminal DCG and the second control terminal TCG according to the judgment result.

[0085] The final quantization result of the pixel signal is determined by the comparison result and the conversion gain of the floating drain FD. Therefore, the judgment result also needs to be sent to the signal processing unit 103 at the same time to determine the final output together with the quantization data output by the analog-to-digital conversion array 102.

[0086] In a non-limiting embodiment, the judgment unit 104 can be implemented by a comparator, and the comparator inputs a first reference voltage V ref1 and the second reference voltage V ref2 .

[0087] Specifically, the driving circuit 101 may adjust the bias voltage applied to the first control terminal DCG and the second control terminal TCG in the following manner:

[0088] In V PXD >V ref2 When , the first control terminal DCG and the second control terminal TCG are at high level, which is recorded as: DCG=1, TCG=1;

[0089] In V ref1 <V PXD <V ref2 When , the first control terminal DCG is at a high level and the second control terminal TCG is at a low level, which is recorded as: DCG=1, TCG=0;

[0090] In V PXD <V ref1 When , the first control terminal DCG and the second control terminal TCG are at low level, which is recorded as: DCG=0, TCG=0;

[0091] Among them, V PXD is the voltage at the signal output terminal of the pixel unit.

[0092] Figure 6 Shown Figure 5 A signal timing diagram of the HDR image sensor with the structure shown below is also referred to Figure 5 and Figure 6 The specific process of timing control in this embodiment is as follows:

[0093] 1) At time t1, the reset transistor RG is turned on to perform a reset operation. Within time period ①, the transmission transistor TG is turned on once. At the same time, since the first control transistor CG1 and the second control transistor CG2 are in the on state, a reset operation is performed;

[0094] 2) After the reset transistor RG is turned off at time t1, the voltage R3 (reference voltage, LOW DCG + LOW TCG) of the node FD is read during time period ②.

[0095] 3) At time t3, the first control tube CG1 is turned off, and the exposure operation is performed in time period ③. During this process, the second control tube CG2 is turned on, so the photoelectrons overflowing under strong light will be collected on the capacitor C2;

[0096] 4) At time t4, the second control tube CG2 is turned off, and then the first control tube CG1 is turned on;

[0097] 5) At time t5, the reset transistor RG is turned on to perform a reset operation. At this time, since only the first control transistor CG1 is turned on, the capacitor C1 and the node FD are reset.

[0098] 6) After reset is complete, the reference voltage R2 (reference voltage, Low DCG + High TCG) of node FD is read during time period ⑤.

[0099] 7) At time t6, the first control transistor CG1 is turned off, and then the voltage R1 (reference voltage, High DCG + High TCG) of the node FD is read during time period ⑥.

[0100] 8) In time period ⑦, the transmission transistor TG is turned on once, and after the transmission transistor TG is turned off, the voltage V at the node FD is read. PXD , and two reference voltages V ref1 、V ref2 Make a judgment, and control the bias voltage applied to the first control terminal DCG and the second control terminal TCG according to the judgment result, as follows:

[0101] If V PXD >V ref2 , then DCG=1, TCG=1;

[0102] If V ref1 <V PXD <V ref2 , then DCG=1, TCG=0;

[0103] If V PXD <V ref1 , then DCG=0, TCG=0;

[0104] 9) At time t8, the second control transistor CG2 and the first control transistor CG1 are controlled according to the judgment result, and the transmission transistor TG is turned on again within the time period ⑧, and then the voltage of the node FD is read;

[0105] 10) At time t9, the reset transistor RG will turn on again to perform the reset operation of the next row.

[0106] Depend on Figure 6 As can be seen from the timing diagram, compared with Figure 3 The solution of the embodiment shown, using Figure 5 The solution of the embodiment shown only requires reading the signal once, which can effectively reduce the number of times the image signal is read out and improve data processing efficiency.

[0107] It should be noted that the above Figure 4 and Figure 6 Both timings shown can achieve an improvement in dynamic range. Figure 4 The timing shown needs to output three reference voltage results and three signal voltage results, and then the three sets of results are processed by the digital circuit to output the final result. Figure 4 The timing shown, Figure 6 The timing shown in the figure adds a pre-judgment process. The input signal voltage is compared with the fixed voltage through the comparator. The approximate range of the pixel signal voltage is first determined and the appropriate conversion gain is selected. This not only improves the dynamic range but also saves the time of two signal voltage quantizations, further improving work efficiency.

[0108] Correspondingly, an embodiment of the present invention further provides a chip, comprising the HDR image sensor of each of the above embodiments.

[0109] It should be understood that the term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document indicates that the related objects are in an "or" relationship.

[0110] The term “plurality” used in the embodiments of the present invention refers to two or more than two.

[0111] The first, second, etc. descriptions appearing in the embodiments of the present invention are only used for illustration and distinction of the description objects. There is no order, nor does it indicate any special limitation on the number of devices in the embodiments of the present invention, and cannot constitute any limitation on the embodiments of the present invention.

[0112] The various embodiments provided by the present invention may be implemented in whole or in part through software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. It should be understood that in the various embodiments of the present invention, the order of the sequence numbers of the above processes does not necessarily indicate the order of execution. The order of execution of the processes should be determined by their functions and inherent logic and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0113] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A variable gain pixel unit circuit, characterized in that: The circuit comprises: a photodiode (PD), a transmission tube (TG), a reset tube (RG), a source follower tube (SG) and a gain control unit; the reset tube (RG), the transmission tube (TG) and the source follower tube (SG) are all NMOS tubes; the gain control unit comprises a first control tube (CG1), a second control tube (CG2) and an anti-overflow capacitor (C2); the first control tube (CG1) and the second control tube (CG2) are both NMOS tubes; the drain of the first control tube (CG1) is connected to the source of the reset tube (RG), and the source of the second control tube (CG2) is connected to the anti-overflow capacitor (C2); the drain of the transmission tube (TG), the gate of the source follower tube (SG), the source of the first control tube (CG1) and the drain of the second control tube (CG2) are respectively connected to the suspended drain; The gate of the transmission tube (TG) is the signal input end of the pixel unit, and the source of the source follower tube (SG) is the signal output end of the pixel unit; The gate of the first control tube (CG1) is a first control terminal (DCG), the gate of the second control tube (CG2) is a second control terminal (TCG), and the first control terminal (DCG) and the second control terminal (TCG) are used to input control signals.

2. The variable gain pixel unit circuit according to claim 1, wherein: The source of the transmission tube (TG) is connected to the cathode of the photodiode (PD).

3. The variable gain pixel unit circuit according to claim 1, wherein: The drain of the source follower tube (SG) is connected to the first power supply voltage; the drain of the reset tube (RG) is connected to the second power supply voltage, and the gate of the reset tube (RG) is connected to the reset control signal.

4. The variable gain pixel unit circuit according to any one of claims 1 to 3, characterized in that: The first control terminal (DCG) and the second control terminal (TCG) are used to apply voltage biases of different magnitudes to the first control tube (CG1) and the second control tube (CG2), so that the floating drain has a variety of different capacitance values, thereby enabling the pixel unit to switch between a variety of different conversion gains.

5. The variable gain pixel unit circuit according to claim 4, characterized in that: There are three combinations of voltages at the first control terminal (DCG) and the second control terminal (TCG): The first control terminal (DCG) and the second control terminal (TCG) are both low level; The first control terminal (DCG) and the second control terminal (TCG) are both high level; The first control terminal (DCG) is at a high level, and the second control terminal (TCG) is at a low level.

6. An HDR image sensor, characterized in that: A pixel array unit comprising the variable gain pixel unit circuit according to any one of claims 1 to 5, a driving circuit respectively connected to the pixel array unit, an analog-to-digital conversion array, and a signal processing unit connected to the analog-to-digital conversion array; The driving circuit is used to output a control signal to a first control terminal (DCG) and a second control terminal (TCG) of the variable gain pixel unit circuit; The analog-to-digital conversion array is used to convert the analog signal output by the variable gain pixel unit circuit into a digital signal and output the digital signal; The signal processing unit is used to process the digital signal output by the analog-to-digital conversion array.

7. The HDR image sensor according to claim 6, wherein: The HDR image sensor further includes: a judgment unit, configured to judge the voltage of the floating drain and output a judgment result to the driving circuit; The driving circuit is further configured to apply different bias voltages to the first control terminal (DCG) and the second control terminal (TCG) according to the judgment result.

8. The HDR image sensor according to claim 7, wherein: The judgment unit is a comparator, and the comparator inputs a first reference voltage and a second reference voltage; If V PXD >V ref2 , the driving circuit controls the first control terminal (DCG) and the second control terminal (TCG) to be high level; If V ref1 < V PXD < V ref2 , the driving circuit controls the first control terminal (DCG) to be a high level and the second control terminal (TCG) to be a low level; If V PXD <V ref1 , the driving circuit controls the first control terminal (DCG) and the second control terminal (TCG) to be low level; Among them, V PXD is the signal output terminal voltage of the pixel unit, V ref1 is the first reference voltage, V ref2 is the second reference voltage.

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