A low-overhead radiation-resistant storage unit layout structure

Abstract

A low-overhead radiation-resistant memory cell layout structure is composed of two half-edge basic unit layout modules spliced ​​together. In each half-edge basic unit layout module, a first P-well is located on one side of a first transmission tube and pull-down tube layout structure; the other side of the first transmission tube and pull-down tube layout structure is closely aligned with the first pull-up tube layout structure; an N-well is located between the first pull-up tube layout structure and the second pull-up tube layout structure; a second P-well is located on one side of the second transmission tube and pull-down tube layout structure; the other side of the second transmission tube and pull-down tube layout structure is closely aligned with the second pull-up tube layout structure; two first pull-up tube layout structures are connected, two first transmission tubes and pull-down tube layout structures are connected, two second pull-up tube layout structures are connected, and two second transmission tubes and pull-down tube layout structures are connected; and the two half-edge basic unit layout modules are closely aligned. This invention reduces layout area consumption and enhances radiation resistance.

Description

Technical Field

[0001] The invention relates to a low-overhead radiation-resistant storage unit layout structure, and relates to the field of static random access memory. Background Art

[0002] Static random access memory is a volatile memory mainly used for data storage and access.

[0003] In the complex radiation environment of space, static random access memory is susceptible to radiation, resulting in performance degradation or failure. The radiation resistance of the memory array directly determines the reliability of the memory reading data. In particular, as the process size decreases, the upset error rate will increase significantly. Therefore, it is extremely important to reinforce the memory cell for aerospace applications. The dual-interlocked memory cell structure is a typical redundant reinforcement structure. It is immune to single-particle upsets, but it cannot cope with multiple node upsets. To improve the single-particle upset resistance of the memory cell, it is common to remotely locate the memory cell nodes and increase the layout spacing between sensitive nodes. However, for different dual-interlocked memory cell structures, the remote node placement results in a less compact layout structure, which is not suitable for high-density SRAM memory cell structures. How to improve the radiation resistance of the memory cell and reduce area loss based on the dual-interlocked memory cell structure and its characteristics is an important problem. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, improve the radiation resistance of the storage unit, and reduce area loss.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A low-overhead radiation-resistant storage unit layout structure, consisting of two half-edge basic unit layout modules;

[0007] Each half-edge basic unit layout module includes: a first pull-up tube layout structure, a second pull-up tube layout structure, a first transmission tube and pull-down tube layout structure, a second transmission tube and pull-down tube layout structure, a first P-well, an N-well, and a second P-well; the first P-well is located on one side of the first transmission tube and pull-down tube layout structure; the other side of the first transmission tube and pull-down tube layout structure is closely attached to the first pull-up tube layout structure; the N-well is located between the first pull-up tube layout structure and the second pull-up tube layout structure; the second P-well is located on one side of the second transmission tube and pull-down tube layout structure; the other side of the second transmission tube and pull-down tube layout structure is closely attached to the second pull-up tube layout structure;

[0008] The two first pull-up tube layout structures of the two half-edge basic unit layout modules are connected, the two first transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected; the two second pull-up tube layout structures of the two half-edge basic unit layout modules are connected; the two second transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected; the two half-edge basic unit layout modules are positioned closely together.

[0009] Preferably, in each half-edge basic unit layout module, the first pull-up tube layout structure, the second pull-up tube layout structure, the first transmission tube and pull-down tube layout structure, the second transmission tube and pull-down tube layout structure, the first P well, the N well, and the second P well are distributed in the vertical or horizontal direction.

[0010] Preferably, in each half-edge basic unit layout module, the drain end of the first pull-up tube layout structure is adjacent to the drain end of the first transmission tube and pull-down tube layout structure; the drain end of the second pull-up tube layout structure is adjacent to the drain end of the second transmission tube and pull-down tube layout structure.

[0011] Preferably, the first pull-up tube layout structure and the second pull-up tube layout structure each include at least: an active area pattern, a P-type implantation region located on the active area pattern, two polysilicon patterns spanning the active area pattern, and contact holes located on the polysilicon pattern; the two polysilicon patterns are distributed in a vertical or horizontal direction, and both share a source region;

[0012] The first transmission tube and pull-down tube layout structure and the second transmission tube and pull-down tube layout structure each include at least: an active area pattern, an N-type implantation region located on the active area pattern, four polysilicon patterns spanning the active area pattern, and contact holes located on the polysilicon pattern; the four polysilicon patterns are distributed in a vertical or horizontal direction, and two adjacent polysilicon patterns share a source region or a drain region;

[0013] The active area patterns included in the first pull-up tube layout structure, the second pull-up tube layout structure, the first transmission tube and pull-down tube layout structure, and the second transmission tube and pull-down tube layout structure form a whole.

[0014] Preferably, each half-edge basic unit layout module further includes:

[0015] a power line pattern, the power line pattern being located above the N-well;

[0016] A ground pattern is located above the first P-well and the second P-well.

[0017] Preferably, each half-edge basic unit layout module further includes a word line pattern;

[0018] The word line pattern is located in the middle of the half-edge basic unit layout module; the word line pattern is a non-top metal process layer.

[0019] Preferably, each half-edge basic unit layout module further includes a bit line pair pattern;

[0020] The bit line pair pattern is respectively located above the first transmission tube and pull-down tube layout structure and the second transmission tube and pull-down tube layout structure; the bit line pair pattern is a non-top metal process layer.

[0021] Preferably, the two first pull-up tube layout structures of the two half-edge basic unit layout modules are connected, and the two first transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected, as a basic storage unit; the two second pull-up tube layout structures of the two half-edge basic unit layout modules are connected, and the two second transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected, as another basic storage unit.

[0022] Preferably, the four half-unit structures of the two storage units are arranged in a cross pattern in a vertical or horizontal direction.

[0023] Preferably, in the layout structure, when a storage node in any basic storage unit is flipped, it can be restored to the original storage value.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] (1) The present invention discloses a low-overhead radiation-resistant storage unit layout structure, which solves the problem that the radiation-resistant static random access memory storage unit is susceptible to interference from single particle and total dose effects, thereby reducing layout area consumption and enhancing radiation resistance.

[0026] (2) Insert non-sensitive unit nodes into sensitive node pairs to achieve the separation of sensitive node pairs without sacrificing area. By increasing the spacing between sensitive node pairs, the charge sharing effect is reduced and the ability to resist single event upset is enhanced.

[0027] (3) By rationally distributing and arranging devices, the amount of charge collected at key nodes can be reduced, thereby lowering the possibility of single-particle upset errors.

[0028] (4) Enhanced single-particle latch-up resistance through closely arranged N-well and P-well.

[0029] (5) Using the SET reduction principle, the NMOS drain region and the PMOS drain region belonging to the same circuit node are placed adjacent to each other. The charge sharing effect between the non-sensitive node pairs is utilized. The complementary transient level change trend between the two mitigates the single-particle transient pulse amplitude of the sensitive node and reduces the sensitivity of the sensitive node to single-particle events. In other words, the charge sharing effect between non-sensitive nodes is utilized to further reduce the impact of single-particle-induced multi-node upsets on the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a low-overhead radiation-resistant storage unit layout structure provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of a half-edge basic unit layout module provided by an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of a memory cell according to an embodiment of the present invention;

[0033] Figure 4 A layout diagram of a half-edge basic unit layout module provided by an embodiment of the present invention;

[0034] Figure 5 A cell distribution diagram of a low-overhead radiation-resistant storage cell layout structure provided by an embodiment of the present invention;

[0035] Figure 6 A layout diagram of a low-overhead radiation-resistant storage unit layout structure provided by an embodiment of the present invention;

[0036] Figure 7 This is a layout diagram of word lines and bit lines of a half-edge basic unit layout module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0038] Figure 1 A schematic diagram of a low-overhead radiation-resistant storage unit layout structure provided by an embodiment of the present invention; Figure 2 A schematic diagram of a half-edge basic unit layout module provided by an embodiment of the present invention; Figure 3 A circuit schematic diagram of a low-overhead radiation-resistant storage unit layout structure provided by an embodiment of the present invention; Figure 4 A layout diagram of a half-edge basic unit layout module provided by an embodiment of the present invention; Figure 5 A cell distribution diagram of a low-overhead radiation-resistant storage cell layout structure provided by an embodiment of the present invention; Figure 6 A layout diagram of a low-overhead radiation-resistant storage unit layout structure provided by an embodiment of the present invention; Figure 7This is a layout diagram of word lines and bit lines of a half-edge basic unit layout module provided by an embodiment of the present invention.

[0039] This embodiment provides a low-overhead radiation-resistant memory unit layout structure, including: a half-edge basic unit layout module;

[0040] Among them, such as Figure 1 As shown, the low-overhead radiation-resistant storage unit layout structure is composed of two half-edge basic unit layout modules;

[0041] Specifically, the half-edge basic unit layout module, such as Figure 2 As shown, it includes: a first pull-up tube layout structure; a second pull-up tube layout structure; a first transmission tube and a pull-down tube layout structure; a second transmission tube and a pull-down tube layout structure;

[0042] A first P-well, the first P-well is located on the left side of the first transmission tube and the pull-down tube layout structure;

[0043] N-well, the N-well is located between the first pull-up tube layout structure and the second pull-up tube layout structure;

[0044] The second P-well is located on the right side of the second transmission tube and the pull-down tube layout structure.

[0045] like Figure 1 As shown, the first pull-up tube layout structure, the first transmission tube, and the pull-down tube layout structure of the two half-edge basic unit layout modules are cross-interconnected to form a whole, which serves as a basic storage unit of the circuit; the second pull-up tube layout structure, the second transmission tube, and the pull-down tube layout structure of the two half-edge basic unit layout modules are cross-interconnected to form an overall structure, which serves as another storage unit of the circuit.

[0046] As described above, the low-overhead radiation-hardened memory cell layout of this embodiment is a dual-cell layout. Four half-cell structures from two memory cells are arranged vertically or horizontally in a cross-wise fashion to isolate sensitive node pairs storing the same data within the original memory cells. The two DICE cell layouts are cross-coupled to form a new layout.

[0047] Furthermore, if Figure 2 As shown, the first pull-up tube layout structure; the second pull-up tube layout structure; the first transmission tube and pull-down tube layout structure; the second transmission tube and pull-down tube layout structure; the first P well; the N well; the second P well; can be distributed in the vertical or horizontal direction, and the splicing direction of the unit module can be changed according to the specific layout.

[0048] Furthermore, the first pull-up tube layout structure is adjacent to the first transmission tube and the pull-down tube layout structure, and the second pull-up tube layout structure is adjacent to the second transmission tube and the pull-down tube layout structure.

[0049] Figure 3 This is a schematic diagram of a memory cell according to an embodiment of the present invention. The memory cell structure comprises four pull-up PMOS transistors AP1, AP2, AP3, and AP4; four pull-down NMOS transistors AN1, AN2, AN3, and AN4; and four transmission NMOS transistors AN5, AN6, AN7, and AN8. The memory cell comprises four storage nodes: na, nb, nc, and nd. Na and nc store the same data type, such as "0" or "1," while nb and nd store the same data type. Furthermore, the memory cell structure includes a word line WL and a pair of bit lines BL and BLB (i.e., BL NOT).

[0050] This storage cell structure is a dual interlocked cell (DICE) structure, a typical redundant reinforcement structure. This cell provides SEU (single event upset) resistance and is immune to single-node upsets. If any of the storage nodes is upset, it can be restored to the original stored value.

[0051] Specifically, such as Figure 4 As shown, the half-edge basic unit layout module includes:

[0052] One of the storage units has pull-up PMOS transistors AP1 and AP2; pull-down NMOS transistors AN1 and AN4; and transmission NMOS transistors AN5 and AN8;

[0053] And the pull-up PMOS tubes BP3 and BP4 of another storage unit; the pull-down NMOS tubes BN2 and BN3; and the transmission NMOS tubes BN6 and BN7.

[0054] Furthermore, if Figure 4 As shown, AP1 and AP2 are pull-up PMOS tubes;

[0055] AN1 and AN4 are pull-down NMOS transistors;

[0056] AN5 and AN8 are transmission NMOS transistors;

[0057] BP3 and BP4 are pull-up PMOS tubes of another storage unit;

[0058] BN2 and BN3 are pull-down NMOS tubes of another storage unit;

[0059] BN6 and BN7 are transmission NMOS tubes of another storage unit.

[0060] Similarly, the other half-edge basic unit layout module that constitutes the low-overhead radiation-resistant memory unit layout structure also includes: pull-up PMOS transistors BP1 and BP2; pull-down NMOS transistors BN1 and BN4; transmission NMOS transistors BN5 and BN8; and pull-up PMOS transistors AP3 and AP4 of another memory unit; pull-down NMOS transistors AN2 and AN3; and transmission NMOS transistors AN6 and AN7.

[0061] Identification description: MOS transistors named AP1, AN1, etc., where the ones starting with "A" represent MOS transistors belonging to one storage unit; MOS transistors named BP1, BN1, etc., where the ones starting with "B" represent MOS transistors belonging to another storage unit.

[0062] Specifically, such as Figure 5 As shown,

[0063] Unit 1 is the layout structure of the first transmission tube and the pull-down tube;

[0064] Unit 2 is the first pull-up tube layout structure;

[0065] Unit 3 is the second pull-up tube layout structure;

[0066] Unit 4 is the layout structure of the second transmission tube and the pull-down tube;

[0067] The first transmission tube and pull-down tube layout structure of the other half-edge basic unit layout module of unit 5;

[0068] The first pull-up tube layout structure of the other half-edge basic unit layout module of unit 6;

[0069] The second pull-up tube layout structure of the other half-edge basic unit layout module of unit 7;

[0070] The second transmission tube and pull-down tube layout structure of the other half-edge basic unit layout module of unit 8;

[0071] Among them, unit 1, unit 2, unit 5, and unit 6 are connected to each other to form Figure 3 A memory cell of the memory cell schematic diagram provided by an embodiment of the present invention;

[0072] Unit 3, unit 4, unit 7, unit 8 are connected to each other to form Figure 3 This is another memory cell in the memory cell schematic diagram provided by an embodiment of the present invention.

[0073] Inserting non-sensitive unit nodes between sensitive node pairs allows for greater separation of sensitive node pairs without sacrificing area. This approach increases the spacing between sensitive node pairs to reduce charge sharing effects and enhance single event upset resistance.

[0074] Specifically, such as Figure 6 As shown,

[0075] The left half of the basic unit layout module, the first pull-up tube layout structure AP1, AP2; the first transmission tube and pull-down tube layout structure AN1, AN4, AN5, AN8; and the right half of the basic unit layout module, the first pull-up tube layout structure AP3, AP4; the first transmission tube and pull-down tube layout structure AN2, AN3, AN6, AN7; a total of 12 MOS tubes, constitute Figure 3 A storage location for a schematic diagram.

[0076] Furthermore, if Figure 4 As shown, the drain of the first pull-up transistor layout is adjacent to the drain of the first transmission transistor and pull-down transistor layout, while the drain of the second pull-up transistor layout is adjacent to the drain of the second transmission transistor and pull-down transistor layout. Using the SET reduction principle, the drain regions of the NMOS and PMOS belonging to the same circuit node are placed adjacent to each other. This leverages the charge sharing effect between pairs of non-sensitive nodes. The complementary transient level changes between these two nodes mitigate the amplitude of single-event transient pulses at sensitive nodes, reducing the sensitivity of sensitive nodes to single-event events. This charge sharing effect between non-sensitive nodes further reduces the impact of single-event event-induced multi-node upsets on the memory.

[0077] Furthermore, if Figure 4 As shown, the first pull-up tube layout structure and the second pull-up tube layout structure at least include: an active area pattern, a polysilicon pattern spanning the active area pattern, a P-type implantation region, and contact holes located on the active area pattern and the polysilicon pattern;

[0078] The first transmission tube and pull-down tube layout structure and the second transmission tube and pull-down tube layout structure include at least: an active area pattern, a polysilicon pattern spanning the active area pattern, an N-type implantation region, and contact holes located on the active area pattern and the polysilicon pattern.

[0079] Furthermore, the polysilicon patterns of the first pull-up tube layout structure and the second pull-up tube layout structure include: two polysilicon patterns distributed along the vertical or horizontal direction, such as AP1, AP2 and AP3, AP4, and the two share a source region.

[0080] Furthermore, the polysilicon patterns of the first transmission tube and pull-down tube layout structure and the second transmission tube and pull-down tube layout structure include: four polysilicon patterns distributed in the vertical or horizontal direction, such as AN1, AN5, AN4 and AN8; and two adjacent polysilicon patterns share a source region or a drain region.

[0081] Furthermore, if Figure 7 As shown,

[0082] The half-edge basic unit layout module also includes:

[0083] a power line pattern, the power line pattern being located above the N-well;

[0084] A ground pattern is located above the first P-well and the second P-well.

[0085] Furthermore, if Figure 7 As shown, the half-edge basic unit layout module also includes a word line pattern WL;

[0086] The word line pattern WL is located in the middle of the half-edge basic unit layout module; the word line pattern WL is a non-top metal process layer to reduce the interference of the top metal wiring on the WL line.

[0087] Furthermore, if Figure 7 As shown, the half-edge basic unit layout module includes a bit line pair (BL / BLB) pattern; the bit line pair pattern is located above the first transmission tube and pull-down tube layout structure and the second transmission tube and pull-down tube layout structure respectively; the bit line pair pattern is a non-top metal process layer to reduce the interference of the top metal wiring on the bit line pair.

[0088] The technical solution of this embodiment solves the problem that the radiation-resistant static random access memory storage unit is susceptible to interference from single particle and total dose effects by remotely placing sensitive nodes through a cross-connected dual-unit storage unit layout structure, thereby reducing layout area consumption and enhancing radiation resistance.

[0089] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0090] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A low-overhead radiation-resistant storage unit layout structure, characterized in that: It is composed of two half-edge basic unit layout modules; Each half-edge basic unit layout module includes: a first pull-up tube layout structure, a second pull-up tube layout structure, a first transmission tube and pull-down tube layout structure, a second transmission tube and pull-down tube layout structure, a first P-well, an N-well, and a second P-well; the first P-well is located on one side of the first transmission tube and pull-down tube layout structure; the other side of the first transmission tube and pull-down tube layout structure is closely attached to the first pull-up tube layout structure; the N-well is located between the first pull-up tube layout structure and the second pull-up tube layout structure; the second P-well is located on one side of the second transmission tube and pull-down tube layout structure; the other side of the second transmission tube and pull-down tube layout structure is closely attached to the second pull-up tube layout structure; The two first pull-up tube layout structures of the two half-edge basic unit layout modules are connected, the two first transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected; the two second pull-up tube layout structures of the two half-edge basic unit layout modules are connected; the two second transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected; the two half-edge basic unit layout modules are positioned closely together.

2. The layout structure according to claim 1, characterized in that: In each half-edge basic unit layout module, the first pull-up tube layout structure, the second pull-up tube layout structure, the first transmission tube and pull-down tube layout structure, the second transmission tube and pull-down tube layout structure, the first P well, the N well, and the second P well; Distribute vertically or horizontally.

3. The layout structure according to claim 1, characterized in that: In each half-edge basic unit layout module, the drain end of the first pull-up tube layout structure is adjacent to the drain end of the first transmission tube and pull-down tube layout structure; the drain end of the second pull-up tube layout structure is adjacent to the drain end of the second transmission tube and pull-down tube layout structure.

4. The layout structure according to claim 1, characterized in that: The first pull-up tube layout structure and the second pull-up tube layout structure each include at least: an active area pattern, a P-type implantation region located on the active area pattern, two polysilicon patterns spanning the active area pattern, and contact holes located on the polysilicon pattern; the two polysilicon patterns are distributed in a vertical or horizontal direction and share a source region; The first transmission tube and pull-down tube layout structure and the second transmission tube and pull-down tube layout structure each include at least: an active area pattern, an N-type implantation region located on the active area pattern, four polysilicon patterns spanning the active area pattern, and contact holes located on the polysilicon pattern; the four polysilicon patterns are distributed in a vertical or horizontal direction, and two adjacent polysilicon patterns share a source region or a drain region; The active area patterns included in the first pull-up tube layout structure, the second pull-up tube layout structure, the first transmission tube and pull-down tube layout structure, and the second transmission tube and pull-down tube layout structure form a whole.

5. The layout structure according to claim 1, characterized in that: Each half-edge basic unit layout module also includes: a power line pattern, the power line pattern being located above the N-well; A ground pattern is located above the first P-well and the second P-well.

6. The layout structure according to claim 1, characterized in that: Each half-edge basic unit layout module also includes a word line pattern; The word line pattern is located in the middle of the half-edge basic unit layout module; the word line pattern is a non-top metal process layer.

7. The layout structure according to claim 1, characterized in that: Each half-edge basic unit layout module also includes a bit line pair pattern; The bit line pair pattern is respectively located above the first transmission tube and pull-down tube layout structure and the second transmission tube and pull-down tube layout structure; the bit line pair pattern is a non-top metal process layer.

8. The layout structure according to any one of claims 1 to 7, characterized in that: The two first pull-up tube layout structures of the two half-edge basic unit layout modules are connected, and the two first transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected, as a basic storage unit; the two second pull-up tube layout structures of the two half-edge basic unit layout modules are connected, and the two second transmission tubes and the pull-down tube layout structure of the two half-edge basic unit layout modules are connected, as another basic storage unit.

9. The layout structure according to claim 8, characterized in that: The four half-unit structures of the two storage units are arranged in a cross pattern in a vertical or horizontal direction.

10. The layout structure according to claim 8, characterized in that: In this layout structure, when a storage node in any basic storage unit is flipped, it can be restored to the original storage value.

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