Optimized circuit compiler for trapped-ion quantum computers
Patent Information
- Application Number
- CN202180067433.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-11-02
- Filing Date
- 2021-09-30
- Publication Date
- 2026-08-28
- Estimated Expiration
- 2041-09-30
AI Technical Summary
对量子比特的不完美控制会导致在计算过程中积累的错误,从而限制了能够执行可靠计算的量子计算机的规模
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Figure CN116249992B_ABST
Abstract
Claims
1. A method for performing computation using a quantum computer, the method comprising: A first quantum circuit constructed using one or more gates from a conventional gate set is transformed into a second quantum circuit constructed using one or more gates from a standard trapped ion gate set using a classical computer. The conventional gate set includes NOT gates, Hadamard H gates, phase shift gates Rz(θ), and two-qubit CNOT gates. The standard trapped ion gate set includes single-qubit [φ](π) gates and [φ](π / 2) gates, as well as two-qubit [φ][φ'](π / 2) gates. By using the classical computer to adjust the second quantum circuit, a first optimized quantum circuit is generated using one or more gates from the standard trapped ion gate set; The first optimized quantum circuit is transformed into a third quantum circuit by the classical computer using one or more gates from a set of phase-insensitive trapped ion gates, wherein the set of phase-insensitive trapped ion gates includes single-qubit [φ](π) gates and [φ](π / 2) gates, as well as two-qubit ZZ(π / 2) gates; By using the classical computer to adjust the third quantum circuit, a second optimized quantum circuit is generated using one or more gates from the phase-insensitive trapped ion gate set; as well as The first optimized quantum circuit or the second optimized quantum circuit is applied to a quantum computer to perform computation, wherein... Optimizing the second quantum circuit includes: Remove the [ϕ](π) gate that appears in the second quantum circuit, or propagate the [ϕ](π) gate to the end of the second quantum circuit; In the second quantum circuit, one [ϕ](π / 2) gate is combined with another [ϕ'](π / 2) gate; Reduce the [ϕ][ϕ'](π / 2) gate count in the second quantum circuit; The SWAP gate is propagated to the end of the second quantum circuit; Swap the ZZ(π / 2) gate with the [0][0](π / 2) gate.
2. The method according to claim 1, further comprising: The first quantum circuit is preprocessed before conversion.
3. The method of claim 1, wherein optimizing the second quantum circuit further comprises: The initialization initiated by the second quantum circuit further reduces the gate count.
4. The method of claim 1, wherein optimizing the second quantum circuit further comprises: Measurements based on the termination of the second quantum circuit further reduce the gate count.
5. An ion trap quantum computing system, comprising: A quantum processor comprising multiple qubits, each qubit comprising a trapped ion with two hyperfine states; One or more lasers configured to emit a first Raman laser beam and a second Raman laser beam provided to trapped ions in the quantum processor; A classic computer configured to perform operations including: A first quantum circuit constructed using one or more gates from a conventional gate set is transformed into a second quantum circuit constructed using one or more gates from a standard trapped ion gate set, wherein the conventional gate set includes NOT gates, Hadamard H gates, phase shift gates Rz(θ), and two-qubit CNOT gates, and the standard trapped ion gate set includes single-qubit [φ](π) gates and [φ](π / 2) gates, as well as two-qubit [φ][φ'](π / 2) gates; The second quantum circuit is modulated to generate a first optimized quantum circuit using one or more gates from the standard trapped ion gate set; The first optimized quantum circuit is converted into a third quantum circuit using one or more gates from a set of phase-insensitive trapped ion gates, wherein the set of phase-insensitive trapped ion gates includes single-qubit [φ](π) gates and [φ](π / 2) gates, as well as two-qubit ZZ(π / 2) gates; By adjusting the third quantum circuit, a second optimized quantum circuit is generated using one or more gates from the phase-insensitive trapped ion gate set; and A system controller is configured to execute a control program to control the one or more lasers to perform operations on the quantum processor, the operations including: Applying the first optimized quantum circuit or the second optimized quantum circuit to the quantum processor to perform computation; and Measuring the population of the qubit states in the quantum processor The classical computer is further configured to output the population of the measured qubit states in the quantum processor, wherein Optimizing the second quantum circuit includes: Remove the [ϕ](π) gate that appears in the second quantum circuit, or propagate the [ϕ](π) gate to the end of the second quantum circuit; In the second quantum circuit, one [ϕ](π / 2) gate is combined with another [ϕ'](π / 2) gate; Reduce the [ϕ][ϕ'](π / 2) gate count in the second quantum circuit; Propagate the SWAP gate to the end of the second quantum circuit; and Swap the ZZ(π / 2) gate with the [0][0](π / 2) gate.
6. The ion trap quantum computing system according to claim 5, wherein the operation further comprises: The first quantum circuit is preprocessed before conversion.
7. The ion trap quantum computing system of claim 5, wherein optimizing the second quantum circuit further comprises: The initialization initiated by the second quantum circuit further reduces the gate count.
8. The ion trap quantum computing system of claim 5, wherein optimizing the second quantum circuit further comprises: Measurements based on the termination of the second quantum circuit further reduce the gate count.
9. An ion trap quantum computing system, comprising: Classic computer; A quantum processor comprising multiple qubits, each qubit comprising a trapped ion with two hyperfine states; A system controller configured to execute a control program to control one or more lasers to perform operations on the quantum processor; as well as A non-volatile memory having a plurality of instructions stored therein, which, when executed by one or more processors, cause the ion trap quantum computing system to perform operations, including: The classical computer transforms a first quantum circuit constructed using one or more gates from a conventional gate set into a second quantum circuit constructed using one or more gates from a standard trapped ion gate set, wherein the conventional gate set includes NOT gates, Hadamard H gates, phase shift gates Rz(θ), and two-qubit CNOT gates, and the standard trapped ion gate set includes single-qubit [φ](π) gates and [φ](π / 2) gates, as well as two-qubit [φ][φ'](π / 2) gates; By using the classical computer to adjust the second quantum circuit, a first optimized quantum circuit is generated using one or more gates from the standard trapped ion gate set; The first optimized quantum circuit is converted into a third quantum circuit by the classical computer using one or more gates from a set of phase-insensitive trapped ion gates, wherein the set of phase-insensitive trapped ion gates includes single-qubit [φ](π) gates and [φ](π / 2) gates, as well as two-qubit ZZ(π / 2) gates; By using the classical computer to adjust the third quantum circuit, a second optimized quantum circuit is generated using one or more gates from the phase-insensitive trapped ion gate set; and The system controller applies the first optimized quantum circuit or the second optimized quantum circuit to perform computation on the quantum computer. The population of the qubit states in the quantum processor is measured by the system controller; and The population of the qubit states in the quantum processor, as measured by the output of the classical computer, wherein... Optimizing the second quantum circuit includes: Remove the [ϕ](π) gate that appears in the second quantum circuit, or propagate the [ϕ](π) gate to the end of the second quantum circuit; Combine one [ϕ](π / 2) gate with another [ϕ'](π / 2) gate; Reduce the gate count by [ϕ][ϕ'](π / 2); Propagate the SWAP gate to the end of the second quantum circuit; and Swap the ZZ(π / 2) gate with the [0][0](π / 2) gate.
10. The ion trap quantum computing system according to claim 9, further comprising: The first quantum circuit is preprocessed before conversion.
11. The ion trap quantum computing system of claim 9, wherein optimizing the second quantum circuit further comprises: The initialization initiated by the second quantum circuit further reduces the gate count.
12. The ion trap quantum computing system of claim 9, wherein optimizing the second quantum circuit further comprises: Measurements based on the termination of the second quantum circuit further reduce the gate count.