A method for eliminating memory access conflict based on rescheduling and cyclic transformation

Abstract

The application discloses a memory access conflict elimination method based on rescheduling and loop transformation, and relates to the field of coarse-grained reconfigurable architecture compiler.The application establishes a memory access conflict model to accurately predict the memory access conflict condition under the premise of a continuous placement strategy.Based on the model, a communication-aware memory access optimization method is provided.The method reduces the memory access conflict in the time domain and the space domain through rescheduling and loop transformation, and can effectively reduce the memory access conflict while minimizing the data communication overhead.The two methods of rescheduling and loop transformation provided by the application are implemented through a pure software mode, do not depend on cache resources, and can be easily applied to various CGRA structures, and are better in universality.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of coarse-grained reconfigurable architecture compiler, and particularly relates to a memory access conflict elimination method based on rescheduling and loop transformation. BACKGROUND

[0002] As a promising hardware accelerator for compute-intensive applications, coarse-grained reconfigurable architecture (CGRA) is attracting more and more attention due to its high performance and energy efficiency. Currently, CGRA has been widely used in machine learning and video processing fields. Figure 1 A typical CGRA structure is shown. In order to fully exploit the parallelism, existing CGRA compilers abstract the loop kernel part of the program into a data flow graph (DFG), and then use software pipelining technology to map the loop kernel part onto the processing element array (PEA). The machine cycle interval between two adjacent iterations is called initiation interval (II). Existing software pipelining techniques [1]-[3] aim to minimize II, thereby improving the acceleration performance.

[0003] However, due to the limited memory bandwidth, multi-bank CGRA is proposed to meet the demand of data parallel access. If multiple PEs access the same bank at the same time, memory access conflict will occur, causing pipeline stall and reducing the acceleration performance of CGRA. Therefore, how to fully use on-chip data memory (ODM) to reduce the pipeline stall caused by memory access conflict has become a bottleneck affecting the efficiency of CGRA. The data placement algorithm based on linear transformation allocates the data accessed at the same time to different banks to reduce the memory access conflict caused by software pipelining. However, this kind of algorithm has limitations and does not consider the data communication overhead between on-chip and off-chip. Existing algorithms cannot guarantee that data is stored continuously in ODM, while data is stored continuously in main memory, which will bring additional data communication overhead. In addition, some strategies to reduce memory access conflict will rely on cache resources such as global register buffer (GRB) and local register file (LRF), but it is difficult to provide these cache resources for some low-power CGRA, thereby making it difficult to apply this kind of algorithm in low-power architecture.

[0004] To fully utilize ODM, many optimization algorithms for multi-bank on-chip memory are proposed. Linear transformation algorithms [4]-[6] place the data that will be accessed simultaneously in different banks, thus avoiding memory access conflicts. Conflict-free mapping strategies [6] reduce memory access conflicts and minimize II through a scheduling algorithm called dual-force. However, these algorithms do not consider the data communication overhead from the main memory to the on-chip memory, which may lead to a decrease in the actual performance of CGRA. Some algorithms [7][8] attempt to consider data communication overhead, [7] adjusts the starting address of the array in ODM to avoid conflicts, while [8] reduces conflicts by filling some blank data. But they are all limited to spatial domain optimization in the data placement stage, and due to the limitations of the continuous placement strategy, the optimization effect on memory access conflicts is very limited. [9] uses data reuse between loop iterations to reduce memory access operations, which reduces memory access conflicts from the source. However, this method relies heavily on GRB and LRF for data caching, and has poor universality.

[0005] Existing CGRA compilers mostly place array elements in different banks to reduce memory access conflicts, without considering the overhead of data communication. Even if the data communication overhead is considered, the optimization effect is limited by reducing memory access conflicts in the spatial domain through data placement. In addition, some strategies use data reuse to reduce memory access times to reduce memory access conflicts, but such methods rely heavily on cache resources such as global registers, and have poor universality.

[0006] Therefore, the skilled in the art is committed to developing a method for eliminating memory access conflicts based on rescheduling and loop transformation. Under the premise of continuous placement strategy, a memory access conflict model is established to accurately predict the memory access conflict situation. Based on this model, a communication-aware memory access optimization method is proposed. By rescheduling and loop transformation, memory access conflicts are reduced in the time domain and the spatial domain, minimizing data communication overhead while effectively reducing memory access conflicts. Rescheduling and loop transformation are two methods that are performed through pure software, do not rely on cache resources, and can be easily applied to a variety of CGRA structures, with better universality.

[0007] [1]Mei B,Vernalde S,Verkest D,et al.Exploiting loop-level parallelisnon coarse-grained reconfigurable architectures using modulo scheduling[J].IEEProceedings-Computers and Digital Techniques,2003,150(5):255-261.

[0008] [2] Rau B R. Iterative module scheduling: An algorithm for software pipelining loops [C] / / Proceedings of MICRO-27. The 27th Annual IEEE / ACM International Symposium on Microarchitecture. IEEE, 1994:63-74.

[0009] [3] Hamzeh M, Shrivastava A, Vrudhula S. EPIMap: Using epimorphism to map applications on CGRAs [C] / / Proceedings of the 49th Annual Design Automation Conference. 2012:1284-1291.

[0010] [4] Wang Y, Li P, Cong J. Theory and algorithm for generalized memory partitioning in high-level synthesis [C] / / Proceedings of the 2014 ACM / SIGDA international symposium on Field-programmable gate arrays. 2014:199-208.

[0011] [5] Yin S, Xie Z, Meng C, et al. Multibank memory optimization for parallel data access in multiple data arrays [C] / / 2016 IEEE / ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2016:1-8.

[0012] [6] Yin S, Yao X, Lu T, et al. Conflict-free loop mapping for coarse-grained reconfigurable architecture with multi-bank memory [J]. IEEE Transactions on Parallel and Distributed Systems, 2017, 28(9): 2471-2485.

[0013] [7] Zhao Z, Liu Y, Sheng W, et al. Optimizing the data placement and transformation for multi-bank CGRA computing system [C] / / 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2018: 1087-1092.

[0014] [8] Li C, Gu J, Yin S, et al. Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs [C] / / Proceedings of the 26th Asia and South Pacific Design Automation Conference. 2021: 204-209.

[0015] [9] Chen Y, Zhao Z, Jiang J, et al. Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture [C] / / 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021: 124-129. SUMMARY

[0016] In view of the above defects of the prior art, the technical problems to be solved by the present application are that the existing CGRA memory optimization technology is only based on continuous data placement and reduces memory conflicts in the spatial domain, and the optimization effect is limited, and the existing method of reducing conflicts by using data reuse seriously depends on cache resources.

[0017] To achieve the above-mentioned purpose, the present application provides a memory conflict elimination method based on rescheduling and cyclic transformation, characterized in that it comprises a memory conflict model establishment process and a rescheduling and cyclic transformation method for reducing memory conflicts.

[0018] Further, the memory conflict model establishment process comprises a strategy of predicting the number of times of memory conflict occurrence of the kernel according to the conflict graph weight.

[0019] Further, the rescheduling and cyclic transformation method for reducing memory conflicts comprises a strategy of cyclic permutation and cyclic block according to the memory model.

[0020] Further, the rescheduling and cyclic transformation method for reducing memory conflicts comprises a heuristic algorithm of moving similar memory references to reduce conflicts.

[0021] Further, it comprises the following steps:

[0022] Step 1, the CGRA compiler converts the loop kernel into an intermediate representation LLVMIR (intermediate representation) through the front-end Clang of the LLVM (Low Level Virtual Machine),

[0023] Step 2, generate the corresponding DFG according to the LLVMIR, perform initial scheduling and continuous data placement on the DFG, and obtain the scheduled DFG,

[0024] Step 3, establish a memory conflict model based on the continuous placement strategy,

[0025] Step 4, communication-aware memory access optimization, including two strategies of rescheduling and cyclic transformation,

[0026] Step 5, map the rescheduled DFG,

[0027] Step 6, generate the configuration information of CGRA.

[0028] Further, the step 3 comprises the following steps:

[0029] Step 3.1, affine reduction is first performed on the affine memory reference to facilitate the generation of the conflict graph,

[0030] Step 3.2, generate a corresponding conflict graph according to the memory references of the same cycle, and establish a memory access conflict model according to the conflict graph.

[0031] Further, the step 4 comprises the following steps:

[0032] Step 4.1, according to the conflict model, performing loop transformation on the multi-layer nested loop to find the optimal loop arrangement and loop blocking to reduce memory access conflict,

[0033] Step 4.2, rescheduling the DFG, reducing memory access conflict in time domain and space domain by changing the execution time of each memory access operator and adjusting the array head address.

[0034] Further, the conflict graph is a directed graph.

[0035] Further, the conflict graph, the node represents the memory reference executed at the same time.

[0036] Further, the conflict graph, the edge represents that the two memory references will conflict.

[0037] In the preferred embodiment of the present application, the existing CGRA memory optimization technology is based on continuous data placement, only reduces memory access conflict in the spatial domain, and the optimization effect is limited. In view of the problem, the present application establishes a memory access conflict model to accurately predict the memory access conflict condition on the premise of the continuous placement strategy. Based on the model, a communication-aware memory access optimization method is proposed. The method reduces memory access conflict in time domain and space domain through rescheduling and loop transformation, minimizes data communication overhead, and effectively reduces memory access conflict.

[0038] In view of the problem that the existing method of reducing conflict by using data reuse seriously depends on cache resources, the rescheduling and loop transformation methods proposed by the present application are performed in a pure software manner and do not depend on cache resources, and can be easily applied to various CGRA structures, and have better universality.

[0039] As Figure 2The proposed compiler is shown in the complete flowchart, 205 to 206 are the memory access conflict model based on the proposed continuous placement strategy of the application, 207 to 208 are the communication-aware memory access optimization proposed by the application, including two strategies of rescheduling and loop transformation. The CGRA compiler in 201 converts the loop kernel into the intermediate representation LLVMIR (intermediate representation) through the front-end Clang of LLVM (Low Level Virtual Machine). Through 202, the corresponding DFG is generated according to the LLVMIR, and then through 203 and 204, the initial scheduling and continuous data placement of the DFG are carried out, so as to obtain the scheduled DFG. 205 will first perform affine reduction on the affine memory reference, which is convenient for the generation of the subsequent conflict graph, and 206 will generate the corresponding conflict graph according to the memory reference accessed in the same period, and establish the memory access conflict model according to the conflict graph. According to this conflict model, 207 performs loop transformation on the multi-layer nested loop to find the optimal loop arrangement and loop blocking to reduce memory access conflict. Then, in 208, the DFG is rescheduled, the execution time of each memory operator is changed, and the array head address is adjusted to reduce the memory access conflict from the time domain and the space domain. 209 maps the rescheduled DFG, according to the mapping result, and finally generates the configuration information of CGRA through 210. The establishment of the memory access conflict model based on the conflict graph and the representation of the execution time required by the CGRA accelerated loop kernel through the calculation of the conflict graph weight are the differences between the application and other researches. In addition, unlike the existing work of reducing memory access conflict, which cannot take into account the data communication overhead and the CGRA acceleration performance, the design adopts the communication-aware memory access optimization method based on rescheduling and loop transformation, which can effectively reduce the memory access conflict from the time domain and the space domain on the basis of minimizing the data communication, greatly improving the acceleration performance of CGRA, which is another difference between the application and other researches. Moreover, rescheduling and loop transformation do not require global registers and other cache resources, and are more versatile.

[0040] In order to minimize the communication overhead between the main memory and the on-chip memory, the design adopts the strategy of continuous placement. Based on this strategy, the application proposes a memory access conflict model for accurately evaluating the memory access conflict of each loop kernel. Definition is the iteration domain of the l-layer nested loop kernel, denoted as I, i k represents the iteration variable of the kth layer. Definition is the data domain of the d-dimensional array, denoted as D, x k represents the array subscript of the kth dimension. Given a d-dimensional array, if can be expressed as , then is called affine memory reference, and the specific expression is as follows:

[0041]

[0042] Among them, A d×l It is a coefficient matrix. It is a constant vector of array indices. This invention mainly targets affine loop kernels, where all memory references are affine and satisfy formula (1). Using these definitions, the contiguous placement strategy can be expressed mathematically:

[0043]

[0044] in, For each memory reference Allocate a bank, I A yes The starting address of array A in on-chip memory, and N b This represents the number of banks. The number of banks allocated to each memory reference under the contiguous placement strategy can be calculated using the modulo operation of formula (2). In the software pipeline, memory references from different iterations will be accessed simultaneously. If the reference... Scheduled in machine cycle t j , quotation Scheduled in machine cycle t k When t k ≡t j If mod II, then both references will be executed together. For memory references that execute together, the iteration distance between them can be expressed as:

[0045]

[0046] Given two one-dimensional affine memory references in nested loops of level l. Let △ i =b i -a i ,i∈[0,l-1],△ c =c k -c j △I represents the distance between the starting addresses of the arrays to which the two references belong in on-chip memory. Two references will not conflict in memory access if and only if:

[0047]

[0048] Where, f(△I) D I) is due to the iteration distance ΔI Dconstant value generated by the iteration domain I. Formula (4) has been proved in [1], by which the tedious array subscript calculation can be avoided, and whether the two references will cause memory conflict can be determined by only one greatest common divisor (gcd) calculation and one modulo calculation. The formula assumes In the i-th iteration of the loop D The array subscript value in the iteration is: Then the value of f (△I D ,I) can be expressed as:

[0049]

[0050] The present application proposes the concept of conflict graph, which is an undirected graph, and the node represents the simultaneously executed memory reference, and the edge represents the conflict of the two references. Since only the simultaneously accessed memory reference can generate the conflict graph, each loop kernel will have II conflict graphs. If formula (4) is not satisfied, the corresponding conflict edge will be generated. The weight of the conflict edge means the probability of memory conflict. Obviously, if formula (4) is satisfied, the weight is 0. If formula (4) is not satisfied, the weight of the edge needs to be discussed in two cases: if the coefficients of each iteration variable of the two references are the same, the probability of memory conflict is 100%, and the weight is 1; the remaining case is that the conflict occurs only in a specific iteration, and it is difficult to give the accurate probability of memory conflict. According to experience, the present application sets the weight of the conflict edge in this case to: The weight of the conflict graph is positively correlated with the number of memory conflicts, because the present design represents the memory conflict situation by generating the conflict graph and calculating its weight. The execution time of CGRA can be divided into the conflict-free execution time and the stall time caused by memory conflict. The present design assumes that each memory conflict will cause a stall time of one machine cycle, and therefore the execution time in the memory conflict model can be expressed as:

[0051]

[0052] Where, N I represents the iteration number, L represents the length of the schedule, S E is the set of conflict edges of all conflict graphs, and the weight corresponding to each edge is w e . The weight multiplied by the iteration number can accurately estimate the number of memory conflicts of the kernel in the whole software pipelining process. According to formula (6), an optimization problem can be formed, that is, under the premise of the continuous placement strategy, trying to minimize T model to effectively reduce memory conflict.

[0053] In Figure 2As shown in Figure 205, this invention proposes affine reduction, which involves taking the modulus N of each term in formula (1). b The operation can simplify the calculation of formula (4). For example, when N b =4, A[5i+4] and A[i] are equivalent when calculating the allocated bank. After performing affine reduction on A[5i+4], it will be simplified to A[i], which facilitates the calculation of subsequent steps. 206 is to generate the conflict graph by calculating formula (4), and finally obtain the CGRA execution time in formula (6).

[0054] Based on the memory access conflict model, this invention proposes a communication-aware memory access optimization method (COMA). COMA mainly includes two methods: rescheduling and cyclic transformation. By changing ΔI and f(ΔI) in formula (4), D (I) to reduce memory access conflicts.

[0055] Previous methods for considering data communication overhead simply spatially distribute concurrently accessed data to different banks. This invention proposes a rescheduling method that combines adjusting the array's starting address to avoid memory access conflicts from both the temporal and spatial domains. Unlike traditional methods, this invention's algorithm modifies ΔI (spatial domain) and ΔI... D (Time domain) attempts to explore a larger search space, thereby effectively reducing memory access conflicts. Figure 3 The optimization process of rescheduling is demonstrated. Figure 3 (a) is a one-dimensional loop kernel. Figure 3 (b) is the DFG after initial scheduling, II = 1. Figure 3 The conflict graph corresponding to the scheduling in (b) is as follows: Figure 3 As shown in (c). Figure 3 In (b), L2 in the i-th iteration will be visited simultaneously with L3 in the (i-1)-th iteration, and the iteration distance ΔI D = 1. In the (i-1)th iteration, L3 becomes: A[i+2] (i-1) =A[(i-1)+2]=A[i+1], so f(△I D I) = -1. Assume N b =4, and the example of cyclic transformation will also be based on this assumption. Calculation formula (4) yields: gcd(0,4)|(1+0-1), corresponding to a weight of 1, so L2 and L3 will always conflict. This invention changes ΔI through rescheduling. D The value of is adjusted to reduce memory access conflicts. Figure 3 In (d), L3 is scheduled to time t = 0, at which point the iteration distance ΔI...D = 0, f(AI D , I) = 0, thus L2 and L3 will not conflict. Similarly, Figure 3 (f) by adding routing nodes to change the value of AI D , the conflict between S1 and L1, L2, L3 is eliminated. Since S1 and L1 belong to different arrays respectively, the conflict can be reduced by changing AI. As Figure 3 (h) shows, the head address of array B is changed from 80 to 83, and at this time Similarly, the conflict between S1 and L1, L2, L3 is eliminated. Compared with Figure 3 (f), the combination of adjusting array head address can reduce the use of routing nodes, which is conducive to improving the success rate of the subsequent mapping step.

[0056] In order to quickly obtain an effective schedule, the present application designs a heuristic scheduling algorithm, Figure 3 (j) shows the process of the algorithm. First, the memory references are classified according to the array to which they belong, and in the figure, they are divided into two categories, which are the node set enclosed by the dashed line and the node set not enclosed by the dashed line. Then, the algorithm will first find the similar set in each node set, and the similar set is the set of memory references whose iteration variable coefficients are all equal. The nodes in the similar set will be merged to generate a new virtual node. Each merge is accompanied by a re-scheduling to reduce the memory access conflict in the similar set. If there is no similar set in the same node set, the algorithm will start to find the similar set in different node sets. Unlike the process inside the node set, the merging of the similar set in different node sets will consider re-scheduling and adjusting the array head address together to reduce the number of routing nodes as much as possible. The pseudo code of re-scheduling is shown in Figure 7 .

[0057] The present application moves the memory access operators in the similar set through the re-scheduling algorithm, thereby reducing the memory access conflict in the time domain. The algorithm will calculate the priority of each node (line 3). The priority is considered from two aspects: 1. The more the number of connected conflict edges of a node, the higher the priority of the node; 2. The node whose execution time will not be lengthened after moving, the higher the priority of the node. Then, the algorithm will select the node with the highest priority in the similar set to move, and the number of moves is set to II x N b (line 10), and each move will advance the load operator by one cycle and delay the store operator by one cycle. Each move will calculate formula (6) to try to find the scheduling with the minimum execution time (lines 11-21).

[0058] In addition to changing AI D by re-scheduling, f(AI DThe value of (f(△I Figure 4 (a) is a two-layer nested loop, Figure 4 (b) is the original schedule of Figure 4 (a), has three parts, which are DFG, iteration domain and conflict graph respectively. L1, L2 in the (i, j) iteration will access S1 in the (i, j)-2 iteration. S1 in the (i, j)-2 iteration has two cases: one is that i does not change, and the other is that i changes to i-1. These two cases are marked by curves in Figure 4 (b). For the first case, the calculation formula (4) is gcd(0, 0, 4) | (0+28+0), so S1 and L1 will have a conflict. Figure 4 (c) shows the method of rescheduling, which changes the iteration distance to 4, and S1 in the (i, j)-4 iteration has only one case: i changes to i-1. According to the calculation formula (4), so S1 and L1 will not conflict. Although rescheduling can reduce memory access conflicts, this method requires two additional routing nodes. As shown in Figure 4 (d), this design uses loop permutation to change the iteration domain to (j, i) T , which reduces memory access conflicts. Under this iteration domain, S1 in the (j, i)-2 iteration has the following two cases: (j, i-2) and (j-1, i+2). At this time, f(△I D , I) are -2 and 2 respectively, and then the array B base address is adjusted to 29, so that Loop permutation also eliminates all memory access conflicts without the need for routing nodes. Figure 4 (e) shows the method of loop blocking, which changes the length of the iteration domain from the original <4, 4> to <4, 2>. At this time, the iteration domain is divided into two blocks, which are marked by different dashed boxes. Within each block, S1 in the (i, j)-2 iteration has only one case: So there is no conflict. For the case of spanning two blocks, there is no conflict by calculation. Therefore, this method can also reduce the conflict between S1 and L1, and does not require a routing node. In fact, even if the conflict occurs between the spanning blocks, it can be basically ignored due to the small proportion. Considering that the loop transformation can reduce the memory conflict while reducing II[2], it can effectively improve the performance. For the loop with the number of nested layers less than or equal to 5, the present application directly adopts the method of traversing all permutations to find the permutation with the minimum execution time. For the loop with the number of nested layers greater than 5, the present application will greedily select the iteration variable with a coefficient of 0 to be placed in the outermost layer. This approach is mainly to find a permutation that can reduce II. As can be seen from formula (6), the performance improvement brought by reducing II is much higher than that brought by reducing memory conflict. As for loop blocking, the present application only performs blocking on the innermost loop, and selects the optimal blocking factor to minimize the execution time of CGRA.

[0059] Based on the LLVM platform, the present application realizes a complete and general compilation process, and uses the simulator of CGRA to evaluate the effect of the compilation process. In order to verify the effectiveness of the design, eight typical compute-intensive applications are selected for testing. The communication-aware memory access method (COMA) proposed by the present application is realized based on the memory conflict model, so the accuracy of the model has a great influence on the final optimization result. Figure 5 The accuracy of the memory conflict model is demonstrated, and the execution time obtained by the model is compared with the execution time obtained by the simulator. The results show that the accuracy of the memory conflict model proposed by the present application is as high as 97%, which can accurately predict the memory conflict of the kernel.

[0060] Figure 6 The comparison of the COMA proposed by the present application and the most advanced compilation technology (denoted as Opt+Thp) based on [3] and [4] and the theoretical minimum value (denoted as Min) on the execution time of CGRA is shown. Through rescheduling, COMA reduces the execution time of the kernels jacobi_1d1 and laplace to the theoretical value, that is, there is no memory conflict. For the three kernels fir3, gauss and gesummv, COMA reduces II through loop permutation, and the performance is improved by 2.48 times, 2.59 times and 3.06 times respectively. The results show that compared with the most advanced compilation technology, the present application can obtain an average performance improvement of 1.99 times.

[0061] [1] Cong J, Jiang W, Liu B, et al. Automatic memory partitioning and scheduling for throughput and power optimization[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2011, 16(2): 1-25.

[0062] [2] Yin S, Liu D, Liu L, et al. Joint affine transformation and loop pipelining for mapping nested loop on CGRAs[C] / / 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2015: 115-120.

[0063] [3] Z. Zhao et al., "Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling," in IEEE Transactions on Parallel and Distributed Systems, vol. 31, no. 9, pp. 2201-2219, 1 Sept. 2020, doi: 10.1109 / TPDS.2020.2989149.

[0064] [4] Z. Zhao, Y. Liu, W. Sheng, T. Krishna, Q. Wang, and Z. Mao, "Optimizing the data placement and transformation for multi-bank cgra computing system," in DATE, 2018, pp. 1087-1092.

[0065] The present application has the following obvious and substantial characteristics and advantages compared with the prior art:

[0066] 1. The present application proposes a memory access conflict model based on conflict graph, which innovatively calculates the weight of conflict graph to quickly and accurately predict the memory access conflict in CGRA.

[0067] 2. Compared with the prior art, the application innovatively utilizes rescheduling and loop transformation to effectively avoid memory access conflicts in both time domain and space domain while minimizing data communication overhead.

[0068] 3. The method does not require cache resources such as global registers and can be easily applied to various types of CGRAs.

[0069] The concept, specific structure and technical effects of the application will be further described below with reference to the accompanying drawings, so as to fully understand the purpose, features and effects of the application. BRIEF DESCRIPTION OF DRAWINGS

[0070] Figure 1 is a typical architecture diagram of a 4x4 CGRA of a preferred embodiment of the application;

[0071] Figure 2 is a compilation flow diagram of a preferred embodiment of the application;

[0072] Figure 3 is a rescheduling diagram of a preferred embodiment of the application;

[0073] Figure 4 is a loop transformation diagram of a preferred embodiment of the application;

[0074] Figure 5 is the accuracy of a memory access conflict model of a preferred embodiment of the application;

[0075] Figure 6 is the running time of 8 kernels on a 4x4 PEA of a preferred embodiment of the application;

[0076] Figure 7 is the pseudo code of rescheduling of a preferred embodiment of the application. DETAILED DESCRIPTION

[0077] The application can be embodied in many different forms and the scope of protection of the application is not limited to the embodiments described herein.

[0078] In the drawings, components of the same structure are denoted by the same reference numerals, and components having similar structures or functions are denoted by similar reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the application is not limited to the size and thickness of each component. In order to make the drawings clearer, the thickness of some components is appropriately exaggerated in some places.

[0079] The application relates to the field of coarse-grained reconfigurable architecture compilers, in particular to a memory access conflict model based on a continuous placement strategy and a communication-aware memory access optimization method including two strategies of rescheduling and loop transformation.

[0080] A method for eliminating memory access conflicts based on rescheduling and loop transformation for coarse-grained reconfigurable architecture, comprising the following steps:

[0081] Step 1, corresponding to 201, the application uses the compilation front end of an LLVM (Low Level Virtual Machine) to compile a loop kernel part into an intermediate representation (IR) form;

[0082] Step 2, corresponding to 202-204, a data flow graph is generated according to the intermediate representation, and an existing scheduling [1] and data partitioning [2] are adopted to obtain an initial scheduled data flow graph;

[0083] Step 3, corresponding to 205 to 206, a conflict relationship between various memory references is analyzed according to the initial scheduled data flow graph, so that a memory access conflict model is established;

[0084] Step 3.1, corresponding to 205, affine reduction is performed on all affine memory references, and the calculation in the subsequent steps is simplified through a modulo operation;

[0085] Step 3.2, corresponding to 206, memory access conflict analysis is performed on the reduced memory references according to the initial scheduled data flow graph, and the memory references accessed at the same time are used to generate a corresponding conflict graph, and then a memory access conflict model is established according to the weight of the conflict graph;

[0086] Step 4, corresponding to 207 to 208, the memory access conflict is reduced from the time domain and the space domain according to the memory access conflict model;

[0087] Step 4.1, corresponding to 207, loop permutation and loop blocking are performed on a multi-layer loop nested loop kernel, and according to the memory access conflict model, an optimal solution is found by changing the execution order of the iteration domain, so that the execution time obtained by the memory access conflict model is minimized;

[0088] Step 4.2, corresponding to 208, rescheduling is performed by moving the nodes in the similar set, and the first address of the array in the on-chip memory is adjusted, so that the memory access conflict is reduced from two dimensions of the time domain and the space domain, and finally an optimal scheduling is found, so that the execution time obtained by the memory access conflict model is minimized;

[0089] Step 5, corresponding to 209, mapping is performed according to the rescheduled data flow graph, and an existing mapping strategy [1] is used.

[0090] Step 6, corresponding to 210, generating a corresponding configuration file according to the mapping result.

[0091] [1] Z. Zhao et al., "Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling," in IEEE Transactions on Parallel and Distributed Systems, vol. 31, no. 9, pp. 2201-2219, 1 Sept. 2020, doi: 10.1109 / TPDS.2020.2989149.

[0092] [2] Z. Zhao, Y. Liu, W. Sheng, T. Krishna, Q. Wang, and Z. Mao, "Optimizing the data placement and transformation for multi-bank cgra computing system," in DATE, 2018, pp. 1087-1092.

[0093] The preferred embodiments of the present application are described in detail above. It should be understood that modifications and variations can be made by those of ordinary skill in the art without departing from the spirit and scope of the present application. Therefore, it is intended that the scope of the present application be defined by the scope of the claims and not by the detailed description.

Claims

1. A method for eliminating memory access conflicts based on rescheduling and cyclic transformation, characterized in that, This includes the process of establishing a memory access conflict model and methods for rescheduling and cyclic transformation to reduce memory access conflicts; A memory access conflict model based on a conflict graph is established, and the execution time required to accelerate the loop kernel in CGRA is characterized by calculating the conflict graph weights. Rescheduling and round-robin transitions do not require global register cache resources; The memory access conflict model establishment process includes a strategy for predicting the number of memory access conflicts that occur in the kernel based on the conflict graph weights; The rescheduling and cyclic transformation method for reducing memory access conflicts includes strategies for cyclic arrangement and cyclic block division based on the memory access model. The rescheduling and cyclic transformation methods for reducing memory access conflicts include heuristic algorithms that move memory references in similar sets to reduce conflicts; Includes the following steps: Step 1: The CGRA compiler uses the LLVM frontend Clang to convert the loop kernel into an intermediate representation, LLVM IR. Step 2: Generate the corresponding DFG based on LLVM IR, perform initial scheduling and continuous data placement on the DFG to obtain the scheduled DFG. Step 3: Establish a memory access conflict model based on a contiguous placement strategy. Step 4: Communication-aware memory access optimization, including two strategies: rescheduling and round-robin transformation. Step 5: Map the rescheduled DFG. Step 6: Generate CGRA configuration information; Step 3 includes the following steps: Step 3.1: First, perform affine reduction on the affine memory references to facilitate the subsequent generation of the conflict graph. Step 3.2: Generate a conflict graph based on memory references accessed in the same cycle, and establish a memory access conflict model accordingly; Step 4 includes the following steps: Step 4.1: Based on the conflict model, perform loop transformation on the multi-level nested loops to find the optimal loop arrangement and loop block division to reduce memory access conflicts. Step 4.2: Reschedule the DFG by changing the execution time of each memory access operator and adjusting the array starting address to reduce memory access conflicts in both the time and space domains.

2. The method for eliminating memory access conflicts based on rescheduling and cyclic transformation as described in claim 1, characterized in that, The conflict graph is an undirected graph.

3. The method for eliminating memory access conflicts based on rescheduling and cyclic transformation as described in claim 1, characterized in that, In the conflict graph, nodes represent concurrently executing memory references.

4. The method for eliminating memory access conflicts based on rescheduling and cyclic transformation as described in claim 1, characterized in that, In the conflict graph, an edge represents a conflict between two memory references.

Images