CGRA compiling method and device based on multistage intermediate representation and polyhedral model

Abstract

The invention provides a CGRA compiling method and device based on multistage intermediate representation and a polyhedral model, and relates to the technical field of compiler design. The method comprises the following steps: performing grammar and semantic analysis on a calculation task code or model to obtain an initial intermediate representation, converting to obtain an affine intermediate representation, and executing hardware-independent optimization; performing cyclic transformation and tensor optimization based on a polyhedral model, and realizing mapping by combining regularized mapping and a search strategy; and generating configuration information and an executable file on the reconfigurable architecture according to a mapping result. According to the method, the end-to-end compiling framework is constructed, and the loop program optimization capability of the polyhedral model and a rule-driven rapid mapping mechanism are combined, so that the execution performance and the compiling efficiency of the artificial intelligence task on a coarse-grained reconfigurable architecture are remarkably improved, the problems of optimization hierarchy splitting and low mapping speed of a traditional compiling method are effectively solved, and the method is suitable for large-scale popularization and application. The method is suitable for high-complexity and large-scale parallel artificial intelligence application deployment requirements.

Description

A method and apparatus for CGRA compilation based on multi-level intermediate representation and polyhedral model Technical Field

[0001] This invention relates to the fields of compiler design and hardware acceleration technology, and in particular to a compilation method and apparatus based on multi-level intermediate representation and polyhedral model CGRA. Background Technology

[0002] With the rapid development of artificial intelligence applications, especially the widespread use of large-scale neural network models, higher demands are being placed on the performance and energy efficiency of computing hardware. CGRA (Coarse-Grained Reconfigurable Array), as a flexible and efficient hardware acceleration platform, offers near-ASIC performance while maintaining flexibility through its configurable processing units and interconnect networks, making it an important choice for accelerating artificial intelligence tasks.

[0003] In CGRA hardware design, the accompanying compilation toolchain is crucial for achieving hardware performance. Most existing CGRA compilers are built on traditional compilation frameworks such as LLVM (Low Level Virtual Machine), primarily employing data flow graph mapping techniques based on cyclic pipelines for optimization. However, this approach has significant limitations: First, the optimization focus is overly concentrated on hardware-related low-level mappings, lacking high-level optimization of the program's global structure; second, the front-end intermediate representation optimization and back-end hardware mapping in the compilation process are disconnected, failing to achieve cross-level collaborative optimization; furthermore, for common artificial intelligence operators, traditional search-based mapping methods are too time-consuming, making it difficult to meet the demands of rapid iterative development.

[0004] Although CGRA compilation frameworks based on multi-level intermediate representations, such as ML-CGRA (Machine Learning Coarse-Grained Reconfigurable Array), have emerged in recent years, their optimization methods are still limited to traditional approaches such as basic operator fusion and loop partitioning, resulting in insufficient optimization of the generated intermediate representations. Polyhedral models, as a powerful program transformation and optimization method, can represent complex loop structures through geometric models, providing systematic theoretical support and automated optimization capabilities for loop transformations. However, they have not yet been fully utilized in existing CGRA compilation frameworks. Summary of the Invention

[0005] To address the technical problems of existing technologies, where coarse-grained constructible architectures are increasingly becoming important hardware acceleration platforms as the complexity of artificial intelligence applications grows, but existing compilation methods mainly focus on low-level hardware mapping optimization, often lacking global-perspective collaborative optimization during compilation and exhibiting low mapping efficiency for common artificial intelligence operators, resulting in limited program execution performance and excessively long compilation times, this invention provides a compilation method and apparatus based on multi-level intermediate representation and polyhedral model CGRA. The technical solution is as follows:

[0006] On the one hand, a compilation method based on multi-level intermediate representation and polyhedral model CGRA is provided. This method is implemented by a coarse-grained reconfigurable architecture compilation device, and includes:

[0007] S1. Obtain the computation task code or model.

[0008] S2. Perform syntactic and semantic analysis on the computation task code or model to obtain an initial intermediate representation. Transform the initial intermediate representation to obtain an affine intermediate representation. Perform hardware-independent optimization on the affine intermediate representation to obtain an optimized affine intermediate representation.

[0009] S3. Based on the polyhedral model, perform cyclic transformation and tensor optimization on the optimized affine intermediate representation to obtain the polyhedral optimized intermediate representation.

[0010] S4. Convert the intermediate representation of the polyhedron after optimization into a data flow graph, and combine regular mapping and search strategy to realize the mapping of the data flow graph to obtain the mapping result.

[0011] S5. Generate configuration information and executable files on the reconfigurable architecture based on the mapping results.

[0012] Optionally, S2 includes:

[0013] S21. Perform syntactic and semantic analysis on the computation task code or model using different front-end tools to obtain a unified initial intermediate representation.

[0014] S22. Transform the initial intermediate representation to obtain the affine intermediate representation.

[0015] S23. Perform hardware-independent optimizations on the affine intermediate representation to obtain the optimized affine intermediate representation; among which, hardware-independent optimizations include: memory optimization, operator fusion, cycle boundary optimization, and model quantization.

[0016] Optionally, S3 includes:

[0017] S31. Perform format conversion on the optimized affine intermediate representation to obtain the format-converted affine intermediate representation.

[0018] S32. Based on the format-converted affine intermediate representation and the polyhedral model, formal modeling is performed to obtain the polyhedral dependency graph; a hierarchical directed acyclic graph structure is generated by self-loop elimination and merging of strongly connected components; the directed acyclic graph structure is automatically optimized by a hierarchical dynamic programming algorithm to obtain the optimized format-converted affine intermediate representation.

[0019] S33. Perform format conversion on the optimized affine intermediate representation to obtain the optimized intermediate representation of the polyhedron.

[0020] Optionally, the loop transformations in S32 include: loop partitioning, loop merging, loop swapping, loop splitting, loop reversal, and / or loop unrolling.

[0021] Optionally, S4 includes:

[0022] S41. Convert the intermediate representation of the polyhedron after optimization into a data flow graph; wherein the data flow graph includes nodes representing computational operations and edges representing data dependencies.

[0023] S42. Determine whether the data flow graph matches the predefined pattern. If it matches, perform regularized mapping on the data flow graph and output the mapping result. If it does not match, perform search-based mapping on the data flow graph and output the mapping result. The predefined patterns include: sequential execution mode and systolic array mode of matrix multiplication, preloaded convolution kernel mode of convolutional layer, and sequential summation and element operation mode of normalized exponential function.

[0024] Optionally, the search-based mapping in S42 includes:

[0025] S421. Calculate the minimum start interval.

[0026] S422. Determine whether the startup interval is greater than the preset threshold. If it is, return that the mapping failed. If it is not, generate a time-extended coarse-grained reconfigurable architecture model, adjust the data flow graph according to the time-extended coarse-grained reconfigurable architecture model, and perform subgraph isomorphic matching according to the adjusted data flow graph.

[0027] S423. Determine whether the subgraph isomorphic matching is complete. If yes, output the mapping result; otherwise, update the startup interval and proceed to step S422.

[0028] Optionally, S5 includes:

[0029] Based on the mapping relationship of nodes in the mapping result, generate processing unit configuration information; based on the mapping relationship of edges, generate interconnection network configuration information; and based on the processing unit configuration information and interconnection network configuration information, generate configuration information and executable files on the reconfigurable architecture.

[0030] On the other hand, a compilation apparatus based on multi-level intermediate representation and polyhedral model CGRA is provided. This apparatus is applied to the compilation method based on multi-level intermediate representation and polyhedral model CGRA. The apparatus includes:

[0031] The data acquisition module is used to acquire the code or model of the computing task.

[0032] The intermediate representation generation module is used to perform syntactic and semantic analysis on the computation task code or model to obtain an initial intermediate representation, transform the initial intermediate representation to obtain an affine intermediate representation, and perform hardware-independent optimization on the affine intermediate representation to obtain an optimized affine intermediate representation.

[0033] The polyhedron optimization module is used to perform cyclic transformations and tensor optimizations on the optimized affine intermediate representation based on the polyhedron model to obtain the polyhedron-optimized intermediate representation.

[0034] The mapping module is used to convert the intermediate representation after polyhedron optimization into a data flow graph. It combines regularized mapping and search strategies to realize the mapping of the data flow graph and obtain the mapping result.

[0035] The output module is used to generate configuration information and executable files on the reconfigurable architecture based on the mapping results.

[0036] Optionally, the middle section represents the generation module, which is further used for:

[0037] S21. Perform syntactic and semantic analysis on the computation task code or model using different front-end tools to obtain a unified initial intermediate representation.

[0038] S22. Transform the initial intermediate representation to obtain the affine intermediate representation.

[0039] S23. Perform hardware-independent optimizations on the affine intermediate representation to obtain the optimized affine intermediate representation; among which, hardware-independent optimizations include: memory optimization, operator fusion, cycle boundary optimization, and model quantization.

[0040] Optionally, the polyhedron optimization module is further used for:

[0041] S31. Perform format conversion on the optimized affine intermediate representation to obtain the format-converted affine intermediate representation.

[0042] S32. Based on the format-converted affine intermediate representation and the polyhedral model, formal modeling is performed to obtain the polyhedral dependency graph; a hierarchical directed acyclic graph structure is generated by self-loop elimination and merging of strongly connected components; the directed acyclic graph structure is automatically optimized by a hierarchical dynamic programming algorithm to obtain the optimized format-converted affine intermediate representation.

[0043] S33. Perform format conversion on the optimized affine intermediate representation to obtain the optimized intermediate representation of the polyhedron.

[0044] Optionally, cyclic transformations include: cyclic block, cyclic merge, cyclic swap, cyclic split, cyclic inversion, and / or cyclic unrolling.

[0045] Optionally, the mapping module is further used for:

[0046] S41. Convert the intermediate representation of the polyhedron after optimization into a data flow graph; wherein the data flow graph includes nodes representing computational operations and edges representing data dependencies.

[0047] S42. Determine whether the data flow graph matches the predefined pattern. If it matches, perform regularized mapping on the data flow graph and output the mapping result. If it does not match, perform search-based mapping on the data flow graph and output the mapping result. The predefined patterns include: sequential execution mode and systolic array mode of matrix multiplication, preloaded convolution kernel mode of convolutional layer, and sequential summation and element operation mode of normalized exponential function.

[0048] Optionally, the search-based mapping includes:

[0049] S421. Calculate the minimum start interval.

[0050] S422. Determine whether the startup interval is greater than the preset threshold. If it is, return that the mapping failed. If it is not, generate a time-extended coarse-grained reconfigurable architecture model, adjust the data flow graph according to the time-extended coarse-grained reconfigurable architecture model, and perform subgraph isomorphic matching according to the adjusted data flow graph.

[0051] S423. Determine whether the subgraph isomorphic matching is complete. If yes, output the mapping result; otherwise, update the startup interval and proceed to step S422.

[0052] Optionally, the output module is further used for:

[0053] Based on the mapping relationship of nodes in the mapping result, generate processing unit configuration information; based on the mapping relationship of edges, generate interconnection network configuration information; and based on the processing unit configuration information and interconnection network configuration information, generate configuration information and executable files on the reconfigurable architecture.

[0054] On the other hand, a coarse-grained reconfigurable architecture compilation device is provided, the coarse-grained reconfigurable architecture compilation device comprising: a processor; and a memory storing computer-readable instructions, wherein when the computer-readable instructions are executed by the processor, any one of the above-described compilation methods based on multi-level intermediate representation and polyhedral model CGRA is implemented.

[0055] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction is stored in the storage medium, the at least one instruction being loaded and executed by a processor to implement any of the above-described methods of the compilation method based on multi-level intermediate representation and polyhedral model CGRA.

[0056] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0057] This invention employs a multi-layered compilation framework based on different optimization requirements, avoiding the disconnect between front-end and back-end optimization in traditional compilation methods. This significantly improves program execution performance and effectively unlocks the potential of hardware parallel computing. By introducing a polyhedral model for global cyclic transformation and tensor optimization, data locality and operational parallelism are systematically optimized, significantly improving the compilation quality for complex artificial intelligence tasks. By constructing a modular compilation framework based on multi-level intermediate representations, program transformation and optimization can be flexibly performed at different levels of abstraction, making the compilation process more comprehensive and accurate. By combining a hybrid strategy of regularized mapping and search-based mapping, fast mapping can be achieved for common artificial intelligence operators while maintaining universality for irregular computation graphs, effectively balancing compilation efficiency and mapping quality. This allows for a balance between performance and development efficiency in the deployment of complex artificial intelligence applications. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 is a flowchart of a CGRA compilation method based on multi-level intermediate representation and polyhedral model provided by an embodiment of the present invention;

[0060] Figure 2 is a schematic diagram of the rule-based mapping process provided in an embodiment of the present invention;

[0061] Figure 3 is a schematic diagram of the framework structure of the coarse-grained reconfigurable architecture compilation method based on multi-level intermediate representation and polyhedral model provided in the embodiment of the present invention.

[0062] Figure 4 is a block diagram of a CGRA compilation device based on multi-level intermediate representation and polyhedral model provided in an embodiment of the present invention;

[0063] Figure 5 is a schematic diagram of the structure of a coarse-grained reconfigurable architecture compilation device provided in an embodiment of the present invention. Detailed Implementation

[0064] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0065] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0066] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0067] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0068] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0069] This invention provides a compilation method based on multi-level intermediate representation and polyhedral model CGRA. This method can be implemented by a coarse-grained reconfigurable architecture compilation device, which can be a terminal or a server. As shown in Figure 1, the flowchart of the compilation method based on multi-level intermediate representation and polyhedral model CGRA includes the following steps:

[0070] S1. Obtain the computation task code or model.

[0071] In one feasible implementation, the acquired computational task code or model includes C / C++ source code, a deep learning model defined based on the PyTorch framework, or other intermediate representations that conform to the target CGRA architecture programming specifications.

[0072] S2. Perform syntactic and semantic analysis on the computation task code or model to obtain an initial intermediate representation. Transform the initial intermediate representation to obtain an affine intermediate representation. Perform hardware-independent optimization on the affine intermediate representation to obtain an optimized affine intermediate representation.

[0073] Among them, the multi-layer intermediate representation is a core data structure in the compilation process. It can save the semantic information of the program at different levels of abstraction, providing a flexible and efficient representation for subsequent optimization and code generation.

[0074] Optionally, step S2 above may include the following steps S21-S23:

[0075] S21. Perform lexical, syntactic and semantic analysis on the computation task code or model using different front-end tools to obtain a unified initial intermediate representation.

[0076] In one feasible implementation, the input code or model is subjected to syntactic and semantic analysis by the Clang or PyTorch compiler tools to generate an initial MLIR SCF (Multi-Level Intermediate Representation Structured Control Flow) intermediate representation.

[0077] Among them, the Clang compiler is used to process traditional programming languages ​​such as C / C++, the PyTorch compiler tool is used to process deep learning models based on the PyTorch framework, and the MLIR SCF intermediate representation is a structured control flow intermediate representation in the MLIR (Multi-Level Intermediate Representation) framework, which can effectively express the control flow structure and basic operations of the program.

[0078] Specifically, by using different front-end tools to perform syntactic and semantic analysis on the input code or model, the logical structure and computational intent of the program can be accurately captured, and a standardized intermediate representation can be generated. This lays the foundation for subsequent unified optimization processing and ensures that programs from different types of input sources can be optimized and transformed under a unified framework.

[0079] This invention, by acquiring diverse computational task code or models, provides a unified and standardized starting point for subsequent compilation processes. This support for multiple input sources not only ensures the versatility and flexibility of the compilation framework but also provides a standardized program representation foundation for subsequent hardware-independent optimization and polyhedral transformations. This ensures that high-level semantic information can be fully utilized during compilation optimization, thereby improving optimization results and the execution performance of the final code.

[0080] S22. Transform the initial intermediate representation to obtain the affine intermediate representation.

[0081] S23. Perform hardware-independent optimizations on the affine intermediate representation to obtain the optimized affine intermediate representation; among which, hardware-independent optimizations include: memory optimization, operator fusion, cycle boundary optimization, and model quantization.

[0082] In one feasible implementation, memory optimization reduces memory access frequency and improves data locality by caching and reorganizing access patterns for contiguous memory accesses such as arrays; operator fusion reduces intermediate access and scheduling overhead by merging adjacent computational operators (such as Conv (Convolution) + ReLU (Rectified Linear Unit) + BN (Bayesian Network) or Add and Mul (Multiplication) into MAC (Multiply Accumulate)); loop boundary optimization eliminates redundant iterations to reduce control flow complexity for special cases where the upper bound of the loop is 0 or 1; and model quantization converts floating-point formats such as Float or Double to int8 or int16 types, which can further improve parallelism on mixed-precision CGRA and significantly reduce computation and storage resource consumption.

[0083] Hardware-independent optimizations are performed on the intermediate representation of MLIR SCF, which can improve program performance without relying on specific hardware architectures. These optimizations can effectively improve program execution efficiency and create favorable conditions for subsequent hardware-related optimizations.

[0084] It should be noted that by performing lexical, syntactic, and semantic analysis on the code, generating intermediate representations, and performing hardware-independent optimizations, a clear and standardized intermediate representation foundation can be established, eliminating redundant operations and inefficient patterns in the source code. This provides high-quality input for subsequent deep optimization based on the polyhedral model, while ensuring the decoupling of the optimization process from the specific hardware implementation. This greatly improves the versatility and portability of the compilation framework, laying a solid foundation for the efficient execution of the program on CGRA.

[0085] S3. Based on the polyhedral model, perform cyclic transformation and tensor optimization on the optimized affine intermediate representation to obtain the polyhedral optimized intermediate representation.

[0086] Among them, the polyhedral model is a mathematical model used for program analysis and optimization. It uses geometric methods to represent the program's iteration space and data dependencies, and can support complex loop transformations and parallel optimization.

[0087] Optionally, step S3 above may include the following steps S31-S33:

[0088] S31. Perform format conversion on the optimized affine intermediate representation to obtain the format-converted affine intermediate representation.

[0089] In one possible implementation, the MLIR Affine intermediate representation is converted to the OpenScop format.

[0090] OpenScop is a standard intermediate representation format used to exchange program information between polyhedral optimization tools, and it can completely preserve the program's loop structure, data dependencies, and iteration space information.

[0091] Specifically, by converting the MLIR Affine intermediate representation into the OpenScop format, a standard geometric representation of the program can be established, providing a unified input format for subsequent polyhedral optimization, ensuring lossless information transfer between different optimization tools, thereby improving the portability and accuracy of the optimization process.

[0092] S32. Based on the format-converted affine intermediate representation and the polyhedral model, formal modeling is performed to obtain the polyhedral dependency graph; a hierarchical directed acyclic graph structure is generated by self-loop elimination and merging of strongly connected components; the directed acyclic graph structure is automatically optimized by a hierarchical dynamic programming algorithm to obtain the optimized format-converted affine intermediate representation.

[0093] Among them, loop transformation includes one or more combinations of loop partitioning, loop merging, loop swapping, loop splitting, loop reversal, and loop expansion.

[0094] In one feasible implementation, the program's loop iteration space, data dependencies, and memory access patterns are first formally modeled based on a polyhedral model to construct a polyhedral dependency graph. A hierarchical directed acyclic graph structure is then generated through self-loop elimination and merging of strongly connected components. On this basis, the system employs a hierarchical dynamic programming algorithm to globally optimize the loop hierarchy from top to bottom. By calculating the cost functions of different loop transformation strategies and combining integer linear programming and parametric integer programming, the system automatically generates the optimal loop transformation sequence that satisfies data dependency constraints. This effectively reduces inter-loop communication overhead, improves data locality, explores instruction-level parallelism, and increases cache utilization while maintaining program semantic equivalence.

[0095] This invention utilizes a hierarchical dynamic programming method for automated loop transformation optimization. It systematically analyzes the global data dependencies of a program and automatically generates various legal transformation sequences, including loop partitioning, loop merging, loop swapping, loop splitting, loop inversion, and loop unrolling. This mathematical model-based optimization method fully considers the mutual influence between different transformations, maximizing data locality, exploiting instruction-level parallelism, and improving cache utilization while preserving program semantics, thereby significantly improving program execution efficiency.

[0096] S33. Perform format conversion on the optimized affine intermediate representation to obtain the optimized intermediate representation of the polyhedron.

[0097] In one possible implementation, the optimized OpenScop format is converted back to the MLIR Affine intermediate representation.

[0098] Converting the optimized OpenScop format back to the MLIR Affine intermediate representation allows the polyhedral optimization results to be reintegrated into the MLIR compilation framework, ensuring that the optimized program can continue to participate in subsequent compilation processes. This bidirectional conversion mechanism establishes a bridge between high-level program transformation and specific hardware implementation, fully leveraging both the theoretical advantages of the polyhedral model in program optimization and the engineering advantages of the MLIR framework in hardware code generation.

[0099] This invention performs cyclic transformations and tensor optimizations on intermediate representations based on polyhedral models, which can reconstruct the computation and data access patterns of programs from a global perspective, systematically eliminate performance bottlenecks, and generate highly optimized and hardware-friendly computation graph representations. This lays a solid foundation for efficient mapping on CGRA and significantly improves the execution performance of complex computation tasks on reconfigurable architectures.

[0100] S4. Convert the intermediate representation of the polyhedron after optimization into a data flow graph, and combine regular mapping and search strategy to realize the mapping of the data flow graph to obtain the mapping result.

[0101] Figure 2 shows a schematic diagram of the rule-based mapping process provided by an embodiment of the present invention.

[0102] The processing unit array is the core computing component in CGRA, consisting of multiple processing units connected by a configurable interconnect network, capable of executing multiple computing tasks in parallel; the regularized mapping is a fast mapping based on predefined efficient computing patterns, while the search strategy is to find feasible mapping schemes through systematic spatial exploration.

[0103] Optionally, step S4 above may include the following steps S41-S42:

[0104] S41. Convert the optimized intermediate representation of the polyhedron into a data flow graph.

[0105] In one feasible implementation, a data flow graph is a graphical representation of a program, where nodes represent computational operations and edges represent data dependencies, clearly showing the data flow and operation sequence in a computational task.

[0106] Specifically, by converting the optimized intermediate representation into a data flow graph, the correspondence between computing tasks and hardware resources can be established, providing an intuitive and structured input for subsequent hardware mapping, ensuring that each operation in the computing task can find a corresponding execution unit in CGRA, and that each data dependency can be effectively transmitted through the interconnect network.

[0107] S42. A hybrid mapping strategy is adopted, which performs rule-based mapping on data flow graphs that match predefined patterns and performs search-based mapping on data flow graphs that do not match.

[0108] Specifically, it determines whether the data flow graph matches a predefined pattern; if they match, it performs a regularized mapping on the data flow graph and outputs the mapping result; if they do not match, it performs a search-based mapping on the data flow graph and outputs the mapping result. The predefined patterns include: the sequential execution pattern and systolic array pattern of matrix multiplication, the preloaded convolution kernel pattern of convolutional layers, and the sequential summation and element-wise operation pattern of normalized exponential functions.

[0109] The search-based mapping is achieved by incrementally initializing the interval and finding subgraph isomorphisms on the time-extended CGRA, including:

[0110] S421. Calculate the minimum start interval.

[0111] S422. Determine whether the startup interval is greater than the preset threshold. If it is, return that the mapping failed. If it is not, generate a time-extended coarse-grained reconfigurable architecture model, adjust the data flow graph according to the time-extended coarse-grained reconfigurable architecture model, and perform subgraph isomorphic matching according to the adjusted data flow graph.

[0112] S423. Determine whether the subgraph isomorphic matching is complete. If yes, output the mapping result; otherwise, update the startup interval and proceed to step S422.

[0113] In one feasible implementation, the present invention employs a hybrid mapping strategy combining rule-based and search-based approaches during the mapping phase. At the start of the process, it first determines whether the target data flow graph matches a predefined pattern. If it matches, rule-based mapping is directly executed, and the mapping result M is output. If it does not match, the search path is entered, the minimum initiation interval II is calculated, and compared with a set threshold. When II is greater than the threshold, mapping failure is returned; when II is less than or equal to the threshold, a time-extended CGRA model T is generated, the data flow graph D′ is adjusted accordingly, and subgraph isomorphic matching is performed to attempt to complete the mapping. If the match is incomplete, the initiation interval II is incremented, and matching is re-executed until a fully matched mapping result M is obtained.

[0114] This process effectively combines the efficiency of pattern mapping with the universality of search-based mapping. By dynamically adjusting the start interval in the time extension dimension, it achieves flexible mapping and performance optimization of data flow graphs with different structures.

[0115] This invention employs a hybrid mapping strategy that fully leverages the high efficiency of regularized mapping and the high adaptability of search-based mapping. For data flow graphs matching predefined patterns, such as common computational patterns like matrix multiplication and convolution, a carefully designed regularized mapping scheme is directly invoked to quickly obtain high-performance mapping results. For irregular data flow graphs that do not match predefined patterns, a search-based mapping method is initiated, systematically exploring the mapping space to ensure the discovery of feasible mapping schemes. This hybrid strategy significantly improves compilation efficiency while maintaining mapping quality.

[0116] By combining regularized mapping with search strategies to achieve efficient mapping of processing unit arrays, the most suitable mapping method can be adopted for computing tasks with different characteristics. This ensures that common computing patterns can achieve optimal performance and that special computing patterns can be successfully mapped, greatly improving the practicality and applicability of the compilation framework and providing a reliable guarantee for the efficient execution of various computing tasks on CGRA.

[0117] S5. Generate configuration information and executable files on the reconfigurable architecture based on the mapping results.

[0118] The configuration information and executable files on the reconfigurable architecture are a specific set of binary instructions and data used to configure the functions of the CGRA processing unit and the connection relationships of the interconnection network, enabling CGRA to execute the target computation task according to the mapping results.

[0119] Optionally, step S5 above may include the following steps S51-S53:

[0120] S51. Generate processing unit configuration information based on the mapping relationship of nodes in the mapping result.

[0121] The node mapping relationship determines the allocation scheme of each computation operation in the data flow graph to the specific processing unit. The processing unit configuration information includes the operation type to be performed by each processing unit, the source of operands, and the target of computation result output.

[0122] Specifically, by generating processing unit configuration information based on node mapping relationships, abstract computational operations can be transformed into specific hardware instructions, ensuring that each processing unit obtains the correct operation configuration, thereby accurately executing the assigned computational tasks and providing a fundamental guarantee for the correct execution of the entire computational process.

[0123] S52. Generate interconnection network configuration information based on the edge mapping relationship.

[0124] In one feasible implementation, interconnection network configuration information is generated based on edge mapping relationships, enabling the establishment of data transmission paths between processing units. This interconnection network configuration information includes routing switch settings, data transmission path selection, and timing synchronization mechanisms, ensuring that data flows correctly and efficiently between processing units according to the dependencies in the data flow graph. This precise interconnection configuration effectively reduces data transmission latency, avoids resource conflicts, and fully leverages the parallel computing capabilities of CGRA.

[0125] S53. Integrate configuration information to generate configuration information and executable files on a reconfigurable architecture.

[0126] In one feasible implementation, integrating configuration information to generate a final hardware configuration file can organize the distributed processing unit configurations and interconnection network configurations into a unified format recognizable by the CGRA controller. The hardware configuration file contains a complete hardware state description and can be directly loaded into the CGRA to implement the hardware implementation of computing tasks, providing an end-to-end solution for task execution.

[0127] It should be noted that by generating configuration information and executable files on the reconfigurable architecture based on the mapping results, the optimized software computation graph can be transformed into an efficient hardware implementation scheme, establishing a key bridge from high-level program description to low-level hardware execution. This ensures that all previous optimization results are ultimately transformed into actual performance improvements, significantly improving the execution efficiency and energy efficiency of computing tasks on CGRA, while greatly reducing the complexity and error risk of manual hardware configuration.

[0128] Figure 3 shows a schematic diagram of the framework structure of the coarse-grained reconfigurable architecture compilation method based on multi-level intermediate representation and polyhedral model provided in the embodiment of the present invention.

[0129] As shown in Figure 3, the compilation method of the present invention mainly includes two parts: the compiler front-end and the back-end.

[0130] In the front-end stage, the system can select the appropriate compilation channel based on the input source language: Python code is processed by the Torch-MLIR front-end, while C / C++ code is parsed by the Clang compiler front-end, both of which are converted into a unified MLIR front-end representation. After semantic analysis, an MLIR affine intermediate representation (Affine IR) is generated, and hardware-independent optimization operations are performed on this basis, including memory optimization, operator fusion, loop boundary optimization, and model quantization operations.

[0131] In the compiler backend stage, the system converts the MLIR affine IR into an OpenSCoP polyhedral model and performs hardware-specific optimizations using polyhedral optimization tools, primarily including automated iterative transformations based on polyhedra. Subsequent intermediate representation transformations and further optimizations generate the LLVM IR and the corresponding DFG (Data Flow Diagram). A rule-based data flow graph mapping module is responsible for mapping the optimized computation graph to the target hardware architecture. Finally, the compiler generates a configuration file for CGRA, including operation unit configuration and interconnect configuration, realizing a complete compilation chain from high-level code to hardware executable configuration.

[0132] In this invention, a multi-layered compilation framework is adopted according to different optimization requirements, avoiding the problem of fragmented front-end and back-end optimization in traditional compilation methods, significantly improving program execution performance, and effectively tapping the potential of hardware parallel computing. By introducing a polyhedral model for global cyclic transformation and tensor optimization, data locality and operational parallelism can be systematically optimized, significantly improving the compilation quality for complex artificial intelligence tasks. By constructing a modular compilation framework based on multi-level intermediate representations, program transformation and optimization can be flexibly performed at different levels of abstraction, making the compilation process more comprehensive and accurate. By combining a hybrid strategy of regularized mapping and search-based mapping, fast mapping can be achieved for common artificial intelligence operators while maintaining universality for irregular computation graphs, effectively balancing compilation efficiency and mapping quality, thereby achieving a balance between performance and development efficiency in the deployment of complex artificial intelligence applications.

[0133] Figure 4 is a block diagram of a CGRA compilation apparatus based on multi-level intermediate representation and polyhedral model according to an exemplary embodiment. This apparatus is used for a CGRA compilation method based on multi-level intermediate representation and polyhedral model. Referring to Figure 4, the apparatus includes a data acquisition module 310, an intermediate representation generation module 320, a polyhedral optimization module 330, a mapping module 340, and an output module 350. Wherein:

[0134] The data acquisition module 310 is used to acquire the computation task code or model.

[0135] The intermediate representation generation module 320 is used to perform syntactic and semantic analysis on the computation task code or model to obtain an initial intermediate representation, transform the initial intermediate representation to obtain an affine intermediate representation, and perform hardware-independent optimization on the affine intermediate representation to obtain an optimized affine intermediate representation.

[0136] The polyhedral optimization module 330 is used to perform cyclic transformation and tensor optimization on the optimized affine intermediate representation based on the polyhedral model to obtain the polyhedral optimized intermediate representation.

[0137] The mapping module 340 is used to convert the intermediate representation after polyhedron optimization into a data flow graph. It combines regularized mapping and search strategy to realize the mapping of the data flow graph and obtain the mapping result.

[0138] Output module 350 is used to generate configuration information and executable files on the reconfigurable architecture based on the mapping results.

[0139] In this invention, a multi-layered compilation framework is adopted according to different optimization requirements, avoiding the problem of fragmented front-end and back-end optimization in traditional compilation methods, significantly improving program execution performance, and effectively tapping the potential of hardware parallel computing. By introducing a polyhedral model for global cyclic transformation and tensor optimization, data locality and operational parallelism can be systematically optimized, significantly improving the compilation quality for complex artificial intelligence tasks. By constructing a modular compilation framework based on multi-level intermediate representations, program transformation and optimization can be flexibly performed at different levels of abstraction, making the compilation process more comprehensive and accurate. By combining a hybrid strategy of regularized mapping and search-based mapping, fast mapping can be achieved for common artificial intelligence operators while maintaining universality for irregular computation graphs, effectively balancing compilation efficiency and mapping quality, thereby achieving a balance between performance and development efficiency in the deployment of complex artificial intelligence applications.

[0140] Figure 5 is a schematic diagram of a coarse-grained reconfigurable architecture compilation device provided in an embodiment of the present invention. As shown in Figure 5, the coarse-grained reconfigurable architecture compilation device may include the CGRA compilation device based on multi-level intermediate representation and polyhedral model shown in Figure 4 above. Optionally, the coarse-grained reconfigurable architecture compilation device 410 may include a first processor 2001.

[0141] Optionally, the coarse-grained reconfigurable architecture compilation device 410 may also include a memory 2002 and a transceiver 2003.

[0142] The first processor 2001, memory 2002, and transceiver 2003 can be connected via a communication bus.

[0143] The following section, with reference to Figure 5, provides a detailed description of each component of the coarse-grained reconfigurable architecture compilation device 410:

[0144] The first processor 2001 is the control center of the coarse-grained reconfigurable architecture compilation device 410. It can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0145] Optionally, the first processor 2001 can perform various functions of the coarse-grained reconfigurable architecture compilation device 410 by running or executing software programs stored in the memory 2002 and calling data stored in the memory 2002.

[0146] In a specific implementation, as one example, the first processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG5.

[0147] In a specific implementation, as one example, the coarse-grained reconfigurable architecture compilation device 410 may also include multiple processors, such as the first processor 2001 and the second processor 2004 shown in FIG. 5. Each of these processors may be a single-core processor or a multi-core processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0148] The memory 2002 is used to store the software program that executes the present invention, and is controlled by the first processor 2001 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.

[0149] Optionally, the memory 2002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 2002 may be integrated with the first processor 2001 or may exist independently and be coupled to the first processor 2001 through the interface circuit of the coarse-grained reconfigurable architecture compilation device 410 (not shown in FIG. 5). This embodiment of the invention does not specifically limit this.

[0150] The transceiver 2003 is used to communicate with network devices or with terminal devices.

[0151] Optionally, transceiver 2003 may include a receiver and a transmitter (not shown separately in Figure 5). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.

[0152] Optionally, the transceiver 2003 can be integrated with the first processor 2001 or exist independently and be coupled to the first processor 2001 through the interface circuit of the coarse-grained reconfigurable architecture compilation device 410 (not shown in FIG. 5). This embodiment of the invention does not specifically limit this.

[0153] It should be noted that the structure of the coarse-grained reconfigurable architecture compilation device 410 shown in Figure 5 does not constitute a limitation on the router. The actual knowledge structure identification device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0154] Furthermore, the technical effects of the coarse-grained reconfigurable architecture compilation device 410 can be referenced from the technical effects of the CGRA compilation method based on multi-level intermediate representation and polyhedral model described in the above method embodiments, and will not be repeated here.

[0155] It should be understood that the first processor 2001 in the embodiments of the present invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0156] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0157] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0158] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0159] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0160] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0161] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0162] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0163] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0164] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0165] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0166] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0167] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A compilation method based on multi-level intermediate representation and polyhedral model CGRA, characterized in that, The method includes: S1, obtaining computation task code or model; S2, performing syntactic and semantic analysis on the computation task code or model to obtain an initial intermediate representation, transforming the initial intermediate representation to obtain an affine intermediate representation, performing hardware-independent optimization on the affine intermediate representation to obtain an optimized affine intermediate representation; S3, performing cyclic transformation and tensor optimization on the optimized affine intermediate representation based on a polyhedral model to obtain a polyhedral optimized intermediate representation; S4, converting the polyhedral optimized intermediate representation into a data flow graph, combining regularized mapping and search strategies to map the data flow graph, and obtaining a mapping result; S5, generating configuration information and executable files on a reconfigurable architecture based on the mapping result.

2. The compilation method based on multi-level intermediate representation and polyhedral model CGRA according to claim 1, characterized in that, S2 includes: S21, performing syntactic and semantic analysis on the computation task code or model using different front-end tools to obtain a unified initial intermediate representation; S22, transforming the initial intermediate representation to obtain an affine intermediate representation; S23, performing hardware-independent optimization on the affine intermediate representation to obtain an optimized affine intermediate representation; wherein, hardware-independent optimization includes: memory optimization, operator fusion, loop boundary optimization, and model quantization.

3. The compilation method based on multi-level intermediate representation and polyhedral model CGRA according to claim 1, characterized in that, S3 includes: S31, performing format conversion on the optimized affine intermediate representation to obtain a format-converted affine intermediate representation; S32, performing formal modeling based on the format-converted affine intermediate representation and the polyhedral model to obtain a polyhedral dependency graph; generating a hierarchical directed acyclic graph structure through self-loop elimination and merging of strongly connected components; performing automated iterative transformation optimization on the directed acyclic graph structure using a hierarchical dynamic programming algorithm to obtain the optimized format-converted affine intermediate representation; S33, performing format conversion on the optimized format-converted affine intermediate representation to obtain a polyhedral optimized intermediate representation.

4. The compilation method based on multi-level intermediate representation and polyhedral model CGRA according to claim 3, characterized in that, The cyclic transformation in S32 includes: cyclic segmentation, cyclic fusion, cyclic exchange, cyclic splitting, cyclic reversal, and / or cyclic expansion.

5. The compilation method based on multi-level intermediate representation and polyhedral model CGRA according to claim 1, characterized in that, S4 includes: S41, converting the intermediate representation after polyhedron optimization into a data flow graph; wherein the data flow graph includes nodes representing computational operations and edges representing data dependencies; S42, determining whether the data flow graph matches a predefined pattern; if it matches, performing a regularized mapping on the data flow graph and outputting the mapping result; if it does not match, performing a search-based mapping on the data flow graph and outputting the mapping result; wherein the predefined patterns include: sequential execution mode and systolic array mode of matrix multiplication, preloaded convolution kernel mode of convolutional layers, and sequential summation and element-wise operation mode of normalized exponential functions.

6. The compilation method based on multi-level intermediate representation and polyhedral model CGRA according to claim 5, characterized in that, The search-based mapping in S42 includes: S421, calculating the minimum startup interval; S422, determining whether the startup interval is greater than a preset threshold. If it is, the mapping fails; if it is not, a time-extended coarse-grained reconfigurable architecture model is generated, the data flow graph is adjusted according to the time-extended coarse-grained reconfigurable architecture model, and subgraph isomorphic matching is performed according to the adjusted data flow graph; S423, determining whether the subgraph isomorphic matching is complete. If yes, the mapping result is output; if no, the startup interval is updated, and the process proceeds to step S422.

7. The compilation method based on multi-level intermediate representation and polyhedral model CGRA according to claim 1, characterized in that, S5 includes: generating processing unit configuration information based on the mapping relationship of nodes in the mapping result, generating interconnection network configuration information based on the mapping relationship of edges, and generating configuration information and executable files on the reconfigurable architecture based on the processing unit configuration information and the interconnection network configuration information.

8. A compilation apparatus based on multi-level intermediate representation and polyhedral model CGRA, wherein the compilation apparatus is used to implement the compilation method based on multi-level intermediate representation and polyhedral model CGRA as described in any one of claims 1-7, characterized in that, The device includes: a data acquisition module for acquiring computation task code or a model; an intermediate representation generation module for performing syntactic and semantic analysis on the computation task code or model to obtain an initial intermediate representation, transforming the initial intermediate representation to obtain an affine intermediate representation, performing hardware-independent optimization on the affine intermediate representation to obtain an optimized affine intermediate representation; a polyhedral optimization module for performing cyclic transformation and tensor optimization on the optimized affine intermediate representation based on a polyhedral model to obtain a polyhedral optimized intermediate representation; a mapping module for converting the polyhedral optimized intermediate representation into a data flow graph, combining regularized mapping and search strategies to map the data flow graph, and obtaining a mapping result; and an output module for generating configuration information and an executable file on a reconfigurable architecture based on the mapping result.

9. A coarse-grained reconfigurable architecture compilation device, characterized in that, The coarse-grained reconfigurable architecture compilation device includes: a processor; and a memory storing computer-readable instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

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