A process mapping method and system based on a priority cut set
By employing a priority cut-set iterative mapping method and timing analysis, the computational complexity and resource consumption issues of traditional process mapping methods in large-scale circuit design are resolved, enabling efficient and optimized circuit design and improving circuit performance and frequency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU DIANZI UNIV
- Filing Date
- 2026-04-09
- Publication Date
- 2026-07-10
AI Technical Summary
Traditional process mapping methods have high computational complexity and consume huge amounts of memory resources in large-scale integrated circuit design, making them difficult to apply to modern FPGA design.
An iterative mapping method based on priority cut sets is adopted. By iterating multiple times and dynamically adjusting the priority ranking criteria, a limited number of priority cut sets are selected for circuit mapping. Combined with timing analysis, the circuit performance is optimized.
It significantly reduces computational complexity and resource consumption, improves circuit design efficiency, optimizes circuit depth and area, increases operating frequency, and has good scalability and timing co-optimization capabilities.
Smart Images
Figure CN122366291A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic design automation (EDA) technology, specifically a circuit logic synthesis method for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and particularly relates to an efficient process mapping method. Background Technology
[0002] With the continuous expansion of VLSI design scale, logic synthesis, as a key step in electronic design automation (EDA), has a significant impact on chip performance and resource utilization. Process mapping is one of the core components of logic synthesis. Its main goal is to transform a technology-independent logic network, such as an AIG (Internal NAND graph), into a gate-level netlist composed of process-specific library cells (such as K-LUTs in FPGAs), and to optimize its area, delay, and other performance metrics.
[0003] In process mapping, existing methods often employ a cut enumeration-based strategy. This strategy exhaustively computes all K-input cut sets that can implement the logic function of each logic node in the circuit network. Subsequently, algorithms such as dynamic programming are used to traverse the network from the main input to the main output, selecting an optimal cut set for each node. However, the computational and storage requirements of this method increase exponentially with the LUT input size K and the circuit size. When dealing with 6-input or even larger LUTs and circuits with millions of gates commonly found in modern FPGA designs, exhaustively enumerating all cut sets becomes impractical, resulting in extremely long algorithm execution times and excessive memory consumption, severely limiting its application in large-scale circuit designs.
[0004] Therefore, it is of great significance to find a suitable method that can efficiently perform process mapping when dealing with new, large-scale circuits and achieve better performance than traditional methods. Summary of the Invention
[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a process mapping method and system based on priority cut sets, thereby solving the problems of high computational complexity, huge memory resource consumption, and difficulty in application to large-scale integrated circuit design caused by the use of exhaustive cut enumeration strategies in traditional process mapping methods.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] In a first aspect, the present invention provides a process mapping method based on priority cut sets, the method comprising:
[0008] S1. Obtain the logical network to be mapped by the process and set the process mapping parameters; the process mapping parameters include the upper limit K of the lookup table input of the target process library, and the upper limit C of the number of priority cut sets stored at each node of the logical network.
[0009] S2. Perform multiple iterative mappings on the logic network, and stop the iterative mapping when a preset convergence condition is met; wherein, the convergence condition includes at least one of the following:
[0010] (a) The representative cut set selected by each node remains unchanged during two adjacent mapping processes;
[0011] (b) In two consecutive mapping processes, the circuit performance index corresponding to the mapping result no longer improves, and the circuit performance index is logic depth or circuit area;
[0012] (c) The number of mapping iterations reaches the preset maximum number of iterations;
[0013] In each mapping process, each node in the logical network is traversed according to the topological order of the logical network, and the cut set of the current node is filtered based on the upper limit K of the lookup table input and the upper limit C of the number of priority cut sets.
[0014] S3. Based on the cut set filtering results after the last mapping process, construct and output the logical network after process mapping.
[0015] Furthermore, the multiple iterations of the mapping include one depth-optimized mapping and at least one area recovery mapping.
[0016] Furthermore, the cut set filtering specifically involves:
[0017] For the currently traversed node, if the node is the main input node or there is no fan-in node, then the trivial cut set containing only the node itself is taken as the initial priority cut set of the node; if the node has one or more fan-in nodes, then a candidate cut set is generated based on the priority cut sets already stored in the fan-in nodes.
[0018] The process of generating candidate cut sets includes:
[0019] The priority cut sets of the fan-in nodes are selected one by one, and the input node sets of the selected cut sets are merged to form corresponding candidate cut sets. During the merging process, if the number of input nodes of the merged candidate cut set exceeds the upper limit K of the lookup table input, the candidate cut set is discarded. The candidate cut sets that meet the input node number constraint are retained to form a set of candidate cut sets for the current node selection.
[0020] According to the priority sorting criteria preset for the current mapping pass, the candidate cut sets are sorted, and a set of cut sets with the highest ranking and a number not exceeding the upper limit C are selected in descending order of the sorting results and stored as the new priority cut sets of the current node; from the new priority cut sets, the cut set with the best sorting result is selected as the representative cut set of the node in this mapping process, and added to the candidate cut set in the next mapping process.
[0021] Furthermore, in the depth-optimized mapping, the priority ranking criterion adopts the depth-optimized criterion, and the ranking priority is as follows: logical depth of the cut set, input size of the cut set, and area flow of the cut set;
[0022] In the area recovery mapping, the priority ranking criterion adopts the area optimization criterion, and the ranking priority is as follows: area flow of the cut set, logical depth of the cut set.
[0023] Furthermore, the logic network is a sequential logic network including registers, and the method further includes:
[0024] Before performing process mapping, timing analysis is first performed to determine the optimal clock period. The timing analysis treats register boundaries as timing transparent and iteratively calculates the signal arrival time of each node in the network under the constraint of a given clock period φ. The minimum feasible clock period φ that enables the circuit to meet timing convergence is determined by methods such as binary search.
[0025] When performing process mapping, the minimum feasible clock cycle φ and the timing information of each node calculated under that cycle are used as timing constraints to guide the selection of cut sets in each mapping pass.
[0026] In a second aspect, the present invention provides a process mapping system, comprising:
[0027] The logic network input module is used to receive the technology-independent logic network to be mapped and initialize the mapping parameters.
[0028] The iterative mapping control module is used to control the execution of multiple mapping processes and configure corresponding priority sorting criteria for each mapping process.
[0029] The priority cut set calculation module is used to calculate and select priority cut sets for network nodes during the mapping process. Specifically, it includes:
[0030] The candidate cut set generation unit is used to generate candidate cut sets based on the priority cut sets of the fan-in nodes;
[0031] Priority sorting unit, used to sort and filter candidate cut sets according to dynamic sorting criteria;
[0032] The network generation module is used to construct the mapped network based on the final representative cut set.
[0033] Thirdly, the present invention provides a machine-readable storage medium, characterized in that the machine-readable storage medium stores machine-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the method described in the first aspect.
[0034] Fourthly, the present invention provides an electronic device including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the instructions to implement the method described in the present invention.
[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0036] This invention avoids the exhaustive enumeration of traditional methods by calculating and storing only a very limited number of priority cut sets. This makes the algorithm's time and space complexity linearly related to the circuit size, significantly reducing computational complexity and resource overhead. Its efficiency is far superior to existing technologies when processing large-scale circuits. Furthermore, by designing a multi-pass iterative mapping process and dynamically adjusting priority ranking criteria, this invention enables intelligent searching within a limited solution space, ensuring high-quality mapping results. Its optimization performance on key indicators such as circuit depth and area is comparable to or even better than traditional optimal algorithms. In addition, this invention has good scalability; its performance is insensitive to the size K of the lookup table input and the total number of circuit nodes, enabling efficient processing of large-scale, complex integrated circuit designs using modern processes. For sequential circuits, this invention integrates timing analysis and mapping processes, achieving synergistic optimization of mapping and retiming. This unlocks performance potential unattainable by traditional separate methods, significantly improving the operating frequency of the final circuit. Attached Figure Description
[0037] Figure 1 This is a flowchart of the process mapping method based on priority cut sets provided by the present invention.
[0038] Figure 2 This is a flowchart illustrating the timing mapping method provided by the present invention. Detailed Implementation
[0039] The following figures further describe in detail the principle and features of the priority cut set-based process mapping method proposed in this invention. The examples given are for illustrative purposes only and are not intended to limit the scope of the invention. It should be noted that the figures are all in a very simplified form and use non-precise scales, solely for the purpose of conveniently and clearly illustrating the embodiments of the invention. Furthermore, the structures shown in the figures are often part of the actual structures. In particular, different figures may use different scales to illustrate different aspects.
[0040] This invention provides a process mapping method based on priority cut sets, the flowchart of which is shown below. Figure 1 As shown, the process mapping environment is first constructed to preprocess the input data; then an iterative mapping process based on priority cut sets is executed; finally, the mapped netlist is generated based on the optimization results.
[0041] Specifically, the method of the present invention includes:
[0042] S1: Construct a process mapping environment to preprocess the input data;
[0043] S101: Utilize the open-source logic synthesis tool ABC to build a process mapping environment and transform Verilog-described circuits into technology-independent NAND graph (AIG) format circuits;
[0044] S102: Set the target process library parameters for process mapping; in this embodiment, the target process is a 6-input lookup table (6-LUT) of a field-programmable gate array (FPGA), so the upper limit of the lookup table input is set to K=6. At the same time, the upper limit of the number of preferred cut sets stored by each network node is set to C=8.
[0045] In a preferred embodiment of the present invention, the logic network is a sequential logic network containing registers. Therefore, before performing process mapping, timing analysis is first performed to determine the optimal clock period. The timing analysis treats the register boundaries as timing transparent and iteratively calculates the signal arrival time of each node in the network under the constraint of a given clock period φ. The minimum feasible clock period φ that enables the circuit to meet timing convergence is determined by methods such as binary search.
[0046] During the process mapping, the minimum feasible clock cycle φ and the corresponding timing information of each node are passed as timing constraints to each mapping pass. Specifically, in each mapping pass, the priority ranking criteria for cut sets are dynamically adjusted by combining the timing information with parameters such as the logic depth and input size of the cut sets. Cut sets that satisfy the timing constraints and have smaller estimated signal arrival times under the current timing information are preferentially selected to ensure the timing stability of the circuit at each mapping stage. Meanwhile, if some cut sets cannot meet the minimum clock cycle φ constraint, they will be automatically eliminated. This method ensures that cut set selection is not only based on area or depth criteria but also considers timing constraints, thereby optimizing the mapping effect of sequential circuits.
[0047] S2: Execute the iterative mapping process based on the priority cut set;
[0048] The iterative mapping process includes a deep optimization mapping module and an area recovery mapping module, which comprehensively optimizes the circuit through multiple passes.
[0049] S201: Construct a depth optimization mapping module; the depth optimization mapping module aims to minimize the circuit logic depth, traverses each node in the circuit in topological order, and calculates and filters the priority cut sets of the nodes according to the "depth-first" criterion; the sorting priority of the "depth-first" criterion is as follows: cut set depth, cut set input size, cut set area flow;
[0050] S202: Construct an area recovery mapping module; the area recovery mapping module aims to minimize the number of lookup tables (LUTs) and updates the priority cut sets of each node according to the "area priority" criterion without increasing the minimum logical depth already reached; the sorting priority of the "area priority" criterion is as follows: cut set area flow, cut set depth; the cut set depth does not exceed the optimal value already reached.
[0051] S203: Perform iterative mapping; first, perform the depth optimization mapping described in S201 to obtain the initial mapping result with the optimal depth; then perform the area recovery mapping described in S202 once or multiple times to iteratively optimize the circuit area while maintaining the depth;
[0052] Preferably, when generating candidate cut sets for a node in step S202, the representative cut set of the node determined in the depth optimization mapping in S201 is also added to the candidate set to prevent the loss of high-quality depth-optimal solutions.
[0053] S3: Generate the final mapping network;
[0054] After completing all mapping passes, the representative cut sets of each node determined by the mapping are recovered based on the area of the last pass, and the final lookup table netlist is constructed. The number of iterations in the mapping process can be manually set according to the circuit size and specific requirements (e.g., setting the maximum number of mapping passes N=3), or it can be automatically determined based on the convergence conditions in the mapping process: when the representative cut sets of all nodes no longer change, or the circuit area reaches a preset minimum value, the mapping process will end early, thereby avoiding invalid further iterations. Specifically, in each mapping pass, if the change in the cut sets is less than a set threshold, or the circuit area of the mapping result no longer changes significantly, the mapping is considered to have converged, and the iteration process is terminated early. If the number of iterations reaches the set maximum number and the convergence condition is not met, the mapping is forcibly terminated.
[0055] S4: Verification of experimental results;
[0056] To verify the effectiveness of the method described in this invention, 13 circuit designs of different scales and functions were selected for experiments. The method of this invention (labeled "this invention") was compared with a benchmark method (labeled "base", i.e., the standard mapping process in the ABC tool). Evaluation metrics included: cost, maximum logic depth, number of LUTs, total number of pins, and runtime. The experimental environment is shown in Table 1 below:
[0057] Table 1: Experimental Environment Configuration
[0058] category Configuration operating system Linux CPU Intel(R) Xeon(R) Gold 6348 CPU @ 2.6GHz GPU NVIDIA GeForce RTX 4090 RAM 500GB Comprehensive tools ABC
[0059] The performance comparison between the method of this invention and the benchmark method is shown in Table 2 below:
[0060] Table 2: Performance Comparison of the Invention Method and the Benchmark Method
[0061]
[0062] As can be seen from the experimental results in Table 2, the method of this invention achieves significant optimization effects on both circuit area and logic depth, two key indicators. In terms of average performance, compared to the benchmark method, it reduces the number of LUTs used by 42.17% while optimizing the logic depth by 12.82%. This fully demonstrates that the multi-pass iterative mapping method based on priority cut sets proposed in this invention, through a depth-first-area optimization strategy, can effectively improve performance while reducing circuit size, providing a highly efficient technical solution for the design of large-scale integrated circuits that balances area and speed.
[0063] The present invention provides an electronic device including a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the method.
[0064] The memory configuration involved in this invention may include fast random access memory (RAM) and non-volatile storage media, such as disk storage devices like hard disks. The system establishes a communication connection with at least one external network element through at least one communication interface (which may be wired or wireless), supporting data exchange through various network environments such as the Internet, wide area network, local area network, or metropolitan area network.
[0065] The bus can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc.
[0066] The memory is used to store program code. When the processor receives instructions to execute these programs, it runs the programs stored in the memory. The method flows defined in any embodiment described in this invention can be integrated into the processor's operation or implemented by the processor itself. In short, after receiving an execution command, the processor executes the programs in the memory to implement the methods disclosed in this invention.
[0067] The processor can be an integrated circuit chip with signal processing capabilities. In implementing the method of this invention, each step can be implemented through the processor's internal hardware logic circuits or software instructions. The processor may be a general-purpose processor, such as a central processing unit (CPU) or a network processor (NP), or it may be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate and transistor logic devices, or discrete hardware components. These processors are capable of implementing or executing the various methods, steps, and logical flows disclosed in this invention.
[0068] The general-purpose processor can be a microprocessor or any standard processor. The method steps of this invention can be executed directly by a hardware decoding processor, or by a combination of hardware and software modules within the decoding processor. The software modules can be stored in established storage media such as random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), or electrically erasable programmable memory (EEPROM). These storage media reside within memory, from which the processor reads information and, in conjunction with its hardware, completes the steps of the method described above.
[0069] One embodiment of the present invention provides a computer program product stored in a readable storage medium and comprising a series of program codes. These codes contain instructions capable of implementing the processes described in the foregoing method embodiments. Specific implementation details have been described in detail in the previous method embodiments and will not be repeated here. In short, this computer program product enables a storage medium to be used to execute the methods disclosed in this invention.
Claims
1. A process mapping method based on priority cut sets, characterized in that, The method includes: Obtain the logical network to be mapped by the process and set the process mapping parameters; the process mapping parameters include the upper limit K of the lookup table input of the target process library, and the upper limit C of the number of priority cut sets stored at each node of the logical network. The logical network is iterated and mapped multiple times until the convergence condition is met. In each mapping process, each node in the logical network is traversed according to the topological order of the logical network, and the cut set of the current node is filtered based on the upper limit K of the lookup table input and the upper limit C of the number of priority cut sets. Based on the cut set filtering results after the last mapping process, construct and output the logical network after process mapping.
2. The process mapping method based on priority cut sets according to claim 1, characterized in that, The multiple iterative mappings include one depth optimization mapping and at least one area recovery mapping.
3. The process mapping method based on priority cut sets according to claim 2, characterized in that, The cut set filtering specifically involves: For the currently traversed node, if the node is the main input node or there is no fan-in node, then the trivial cut set containing only the node itself is taken as the initial priority cut set of the node; if the node has one or more fan-in nodes, then the priority cut sets of the fan-in nodes are selected one by one, and the input node sets of the selected cut sets are merged to form the corresponding candidate cut sets. During the merging process, if the number of input nodes in the merged candidate cut set exceeds the upper limit K of the lookup table input, the candidate cut set is discarded; candidate cut sets that satisfy the input node number constraint are retained to form a set of candidate cut sets for the current node selection. According to the preset priority sorting criteria of the current mapping pass, the candidate cut sets are sorted, and the top-ranked cut sets with a number not exceeding the upper limit C are selected in descending order of sorting results and stored as the new priority cut sets of the current node. The cut set with the best sorting result is selected from the new priority cut set as the representative cut set of the node in this mapping process and added to the candidate cut set in the next mapping process.
4. The process mapping method based on priority cut sets according to claim 3, characterized in that, In the depth-optimized mapping, the priority ranking criterion adopts the depth-optimized criterion, and the ranking priority is as follows: logical depth of the cut set, input size of the cut set, and area flow of the cut set; In the area recovery mapping, the priority ranking criterion adopts the area optimization criterion, and the ranking priority is as follows: area flow of the cut set, logical depth of the cut set.
5. The process mapping method based on priority cut sets according to claim 4, characterized in that, The convergence condition includes at least one of the following: (a) The representative cut set selected by each node remains unchanged during two adjacent mapping processes; (b) In two consecutive mapping processes, the circuit performance index corresponding to the mapping result no longer improves, and the circuit performance index is logic depth or circuit area; (c) The number of mappings reaches the preset maximum number of iterations.
6. The process mapping method based on priority cut sets according to claim 1, characterized in that, The logic network is a sequential logic network that includes registers.
7. The method according to claim 6, characterized in that, Before performing process mapping, a target clock cycle is set, and register boundaries are treated as timing transparent. The signal arrival time of each node in the network is calculated iteratively. The calculated signal arrival time is used as a timing constraint to perform the iterative mapping process.
8. A process mapping system for implementing the method as described in any one of claims 1-7, characterized in that, include: The logic network input module is used to receive the technology-independent logic network to be mapped and initialize the mapping parameters. The iterative mapping control module is used to control the execution of multiple mapping processes and configure corresponding priority sorting criteria for each mapping process. The priority cut set calculation module is used to calculate and select priority cut sets for network nodes during the mapping process. Specifically, it includes: The candidate cut set generation unit is used to generate candidate cut sets based on the priority cut sets of the fan-in nodes; Priority sorting unit, used to sort and filter candidate cut sets according to dynamic sorting criteria; The network generation module is used to construct the mapped network based on the final representative cut set.
9. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to perform the method as described in any one of claims 1-7.
10. An electronic device, characterized in that, The method includes a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the instructions to implement the method as described in any one of claims 1-7.