Logic rewriting acceleration method based on GPU

Abstract

The present invention discloses a logic rewriting acceleration method based on GPU. The present invention parallelizes the subprocess of AIG rewriting. The recursive subprocess of AIG rewriting is redesigned to be non-recursive so as to provide sufficient parallelism for GPU. Secondly, in order to parallelize the replacement step on GPU, the present invention uses locks to ensure that mutually exclusive access will inevitably destroy the scalability of inter-node parallelism. In order to make full use of large-scale inter-node parallelism, the present invention proposes a work scheduler, which groups non-overlapping nodes of MFFC into a group so that nodes in MFFC can be deleted simultaneously without conflict. In order to create and delete the same node at the same time, the present invention also proposes a GPU-friendly graph data structure to support these concurrent operations.

Description

Technical Field

[0001] The invention relates to a logic rewriting acceleration algorithm. Background Art

[0002] Logic synthesis plays an important role in optimizing multi-level logic networks in automated design flows. Logic synthesis is often applied to networks derived from compiled HDLs (such as VHDL or Verilog) before technology mapping to standard cells or programmable devices. Other uses of logic synthesis include hardware simulation, design complexity estimation, fast preprocessing of circuits before software synthesis and equivalence checking [3]. Logic rewriting is an effective technique for optimizing multi-level logic networks and plays an increasingly important role in logic synthesis flows. Modern integrated circuits (ICs) and systems on chips (SoCs) typically contain millions to trillions of logic gates. In addition, due to the locality and greediness of logic rewriting, multiple rounds of rewriting operations are often required to reduce the total number of circuit gates. The time required to optimize these logic networks becomes increasingly expensive with modern serial logic rewriting algorithms. Therefore, parallelizing logic rewriting is essential to speed up logic synthesis for large designs.

[0003] In the past few decades, many logic rewriting algorithms based on different logic network representations, such as And-Inverter Graph (AIG), Majority-Inverter Graph (MIG) and Xor-Majority Graph (MIG) have been proposed. And according to the conclusions drawn in [1], logic rewriting algorithms based on different logic representations share similar computational patterns. Therefore, parallel rewriting algorithms based on AIG can be easily converted to algorithms based on other logic network representations. The logic rewriting serial algorithm based on AIG representation was proposed in [2] and has been well implemented in the industrial-grade logic synthesis tool ABC. Currently, there are parallel algorithms based on AIG based on CPU and GPU. The CPU-based parallel logic rewriting algorithm [3] exploits inter-node parallelism, but uses locks to ensure mutual exclusive access between threads. The GPU-based parallel logic rewriting algorithm [4] accelerates part of the algorithm through node-level parallelism. It also proposes a concept of logical cut that can be used for replacement and is proven to be correct.

[0004] However, the state-of-the-art CPU-parallel logic rewriting algorithm [3] fails to exploit more parallelism at the intra-node level. Specifically, for each node, the assigned threads still execute all the internal processes of the logic rewriting algorithm sequentially. If all these sub-processes are parallelized and different nodes are still processed in parallel, more parallelism can be extracted. In addition, in order to parallelize the replacement step in the logic rewriting, [3] uses a large number of locks to ensure the mutual exclusivity of threads when changing the same node, which greatly reduces the effectiveness of inter-node parallelism. The GPU-parallel logic rewriting algorithm [4] only accelerates the cut enumeration and evaluation steps through node-level parallelism. These two steps are only run once on the original logic network and are not re-executed when the logic network is updated. Therefore, in order to ensure that the replacement of each node still has benefits, they leave the replacement step of updating the logic network to be executed serially on the CPU. This causes a lot of unnecessary communication between the CPU and GPU, greatly reducing the efficiency of parallelization.

[0005] References

[0006] [1]H.Riener,E.Testa,W.Haaswijk,A.Mishchenko,L.Amaru,G.DeMicheli,andM.Soeken.Scalable generic logic synthesis:One approach to rule themall.In2019 56th ACM / IEEE Design Automation Conference(DAC),pages 1–6,2019.

[0007] [2] A. Mishchenko, S. Chatterjee, and R. Brayton. Dag-aware aig rewriting: afresh look at combinational logic synthesis. In 2006 43rd ACM / IEEE DesignAutomation Conference, pages 532–535, 2006.

[0008] [3] V. Possan, Y.-S Lu, A. Mishchenko, K. Pingali, R. Ribas, and A. Reis. Unlocking fine-grain parallelism for aig rewriting. In 2018 IEEE / ACM International Conference on Computer-Aided Design (ICCAD), pages 1–8, 2018.

[0009] [4] S.Lin, J.Liu, T.Liu, MDFWong, and EFYYoung. Novelrewrite: Node-level parallel aig rewriting. In Proceedings of the 59th ACM / IEEE DesignAutomation Conference, DAC'22, page 427–432, New York, NY, USA, 2022. Association for Computing Machinery. Summary of the invention

[0010] The technical problem to be solved by the present invention is that the existing CPU parallel logic rewriting algorithm fails to utilize more parallelism at the intra-node level and has low parallelization efficiency.

[0011] In order to solve the above technical problems, the technical solution of the present invention is to provide a GPU-based logic rewriting acceleration method, characterized in that the sub-process of AIG rewriting is parallelized, and the parallel AIG logic rewriting includes the following steps:

[0012] On the CPU side, the scheduler asynchronously selects a group of nodes with the same level from the input AIG logic network; then, these nodes are copied to the GPU memory, and the GPU sequentially launches kernels to rewrite these nodes in parallel. At the same time, the CPU also starts to select another group of nodes for the GPU to rewrite, completely overlapping the scheduling and rewriting processes; the GPU uses cut enumeration, MFFC calculation, evaluation and replacement to complete the parallel rewriting of nodes, where:

[0013] The cut enumeration adopts a parallel cut enumeration algorithm designed based on the level of the subgraph. The parallel cut enumeration algorithm is used to process nodes with the same level at the same time, from the lower level to the higher level: the nodes in the subgraph used for replacement in the previous scheduling cycle are divided into different lists LAN[slevel] according to the level of the subgraph. slevel is the local level of the node in the subgraph used for replacement. The cut of the nodes in the same list LAN[slevel] is calculated in parallel, and then the Boolean function corresponding to the cut is calculated;

[0014] MFFC calculation uses a top-down calculation mode to parallelize the recursive mffc calculation algorithm: starting with the list of cuts that need to calculate mffc, each mffc calculation of a cut is assigned to a thread block, and the threads in the same thread block collaborate to calculate the mffc of the cut. When the thread block gets the corresponding cut:

[0015] Step 1: The root node of the current cut is added to the MFFC set corresponding to this node. MFFC is the set that stores all the last MFFC nodes.

[0016] Step 2: The left and right children of the root node are added to the buffer F1. Each thread extracts a node n from the buffer F1. If all the fan-outs of node n are in the current MFFC set, the function IS_MFFC_NODE(n) will be evaluated as true. At this time, all the fan-outs of node n are added to the buffer F2, and node n is added to the MFFC set.

[0017] Step 3: Repeat step 2 until all nodes in buffer F1 are processed, and then swap the roles of F1 and F2;

[0018] Step 4: Use the same method from step 2 to step 3 to process a leaf node of the current cut until all leaf nodes of the current cut are processed;

[0019] In the replacement phase, a lock-free replacement algorithm is used to solve the large amount of data contention that exists in the frequent modification of the logic graph, where: To solve the conflict that different threads holding overlapping MFFCs may delete the same node, a node scheduler is used to group nodes that do not overlap MFFCs;

[0020] To resolve the conflict that the MFFCs held by different threads do not overlap, but one thread may want to share the node that other threads will delete, the replacement process is divided into two stages: in the first stage, each block of the GPU deletes the MFFC and builds a new subgraph; in the second stage, each block of the GPU combines all equivalent nodes into a supernode, which supports concurrent deletion / creation operations of a node without introducing locks between different threads.

[0021] Preferably, the node scheduler is a level-based node scheduler that simulates the topological order of sequential node scheduling, starting from a primary level and incrementing the level after selecting all nodes in the level.

[0022] Preferably, the number of nodes scheduled by the node scheduler in a scheduling cycle is a user-defined value, which determines the degree of parallelism.

[0023] Preferably, the fan-out number of the supernode is the sum of the fan-out numbers of all the equivalent nodes. After the supernode is generated, the fan-out value of each equivalent node becomes invalid.

[0024] Preferably, the following method is used to determine whether any two nodes n0 and n1 are equivalent:

[0025] If all fan-in nodes of nodes n0 and n1 point to the same supernode and the polarity of the inputs is the same, then nodes n0 and n1 are equivalent.

[0026] First, in order to exploit intra-node parallelism, the present invention parallelizes the sub-processes rewritten by AIG. Given the limited parallelism of recursive processes, directly mapping the recursive sub-processes rewritten by AIG (such as cut and MFFC (maximum fanout-freecone) calculation algorithms) to the GPU is extremely inefficient. Therefore, these sub-routines are redesigned to be non-recursive in order to provide sufficient parallelism for the GPU. In addition, other logic optimization or logic verification algorithms can also utilize the proposed parallel cut and MFFC calculation algorithms to accelerate their running time. Secondly, in order to parallelize the replacement step on the GPU, the present invention uses locks to ensure that mutually exclusive access will inevitably destroy the scalability of inter-node parallelism. In order to fully exploit large-scale inter-node parallelism, the present invention proposes a work scheduler that groups non-overlapping nodes of MFFC into a group so that nodes in MFFC can be deleted simultaneously without conflict. In order to create and delete the same node at the same time, we also propose a GPU-friendly graph data structure to support these concurrent operations.

[0027] Compared with the prior art solutions, the innovation of the present invention lies in:

[0028] (1) The present invention proposes a recursion-free parallelization algorithm that can effectively exploit the parallelism within the rewritten nodes, which is difficult to achieve due to the highly recursive nature of the original rewriting algorithm.

[0029] (2) The present invention proposes a parallel lock-free replacement algorithm, which includes a work scheduler that can schedule mutually exclusive nodes and a GPU-friendly data structure that can support efficient concurrent operations. Therefore, our lock-free algorithm is highly scalable and can effectively achieve more inter-node parallelism.

[0030] (3) Compared with the most advanced GPU parallel method [4], our method can achieve an average speedup of 3.81 times with the same quality of results. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The AIG rewrite example is shown [2];

[0032] Figure 2 The basic process of parallel AIG logic rewriting is illustrated;

[0033] Figure 3 A supernode is indicated;

[0034] Figure 4 The parallel cut enumeration algorithm proposed in the present invention is illustrated;

[0035] Figure 5 A top-down computational model is illustrated to parallelize the recursive MFFC computation algorithm. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0037] AIG is a directed acyclic graph that represents the structural implementation of the logical functions of a circuit or network in the logic synthesis process. Each node in AIG has a level attribute. It is defined as the number of nodes on the longest path from any input to this node. Our parallel algorithm is based on level. The process of AIG logic rewriting is to replace the n-input subgraph in AIG with a logically equivalent and structurally different n-input subgraph. The replacement subgraph has fewer nodes or can reuse other nodes in AIG, so the final AIG can have fewer nodes. For example Figure 1 As shown, Figure 1 Kazuko Figure 2 The logical functions of Figure 2 The number of nodes is smaller, so we will Figure 1 Replace with sub Figure 2 .

[0038] The basic process of parallel AIG logic rewriting is as follows Figure 2As shown: On the CPU side, the scheduler asynchronously selects a group of nodes with the same level from the input AIG logic network. Then, these nodes are copied to the GPU memory, and the GPU sequentially launches kernels to rewrite these nodes in parallel. At the same time, the CPU also starts to select another group of nodes for the GPU to rewrite, completely overlapping the scheduling and rewriting process. The process running on the GPU includes four steps, namely cut enumeration, MFFC (Maximum Fanout FreeCone) calculation, evaluation and replacement.

[0039] Generally, rewriting algorithms have two kinds of parallelism. One is coarse-grained parallelism, i.e., the inter-node level. Different nodes are processed in parallel, but the processing of each node is serial. The other is fine-grained, i.e., the intra-node level. In this parallel granularity, operations on each node are processed in parallel. In the above steps, cut enumeration and MFFC calculation are highly recursive and difficult to parallelize on GPU, so these two parts are the most challenging. We redesigned the algorithms of these two parts to explore more intra-node parallelism. The purpose of inter-node parallelism is to be able to rewrite multiple AIG nodes at the same time. Due to the dependencies between nodes, it is not easy to effectively utilize inter-node parallelism. Node replacement is the core step of logic rewriting and the only step that changes AIG. Its role is to replace a subgraph with another equivalent subgraph with fewer nodes, or share the same node with other subgraphs. This step frequently modifies the logic graph, so there is a lot of data contention, which hinders inter-node parallelism. Therefore, we proposed a lock-free replacement algorithm to effectively resolve these data conflicts. Since the intra-node parallelism of the node evaluation step is a common parallel paradigm, and this step does not delete or create new nodes, the parallelization of this step is relatively easy to implement and will not be described in detail here.

[0040] 1) Lock-free inter-node parallelization (node ​​replacement)

[0041] Two types of conflicts between threads may arise in the replacement step. First, different threads may delete the same node if the MFFCs held by these threads overlap. Second, a thread may want to share a node that will be deleted by other threads even if the MFFCs do not overlap. The existence of these two types of conflicts can greatly limit the scalability of the parallel rewriting algorithm. To resolve the first type of conflict, we propose a node scheduler that groups nodes whose MFFCs do not overlap. Then, to resolve the second type of conflict, we divide the replacement process into two phases. In the first phase, each block of the GPU deletes MFFCs and builds a new subgraph. Specifically, each block creates a new node for the subgraph even if equivalent nodes exist outside the new subgraph. In the second phase, each block combines all equivalent nodes into a supernode. This data structure supports concurrent deletion / creation operations of a node without introducing locks between different threads. This delayed equivalence lookup pattern eliminates locks and ensures correctness when exploiting inter-node parallelism.

[0042] 1) Node Scheduler:

[0043] Node scheduling is crucial as it directly affects the result quality and parallelism level. There are two issues to consider: 1) The behavior of the proposed parallel work scheduler should be similar to the sequential ABC-based node scheduling (nodes are processed in topological order) to ensure quality. 2) The selected nodes for parallel rewriting should not interfere with each other (lock-free). If the work scheduler selects incorrect nodes, locks will be required between thousands of threads, significantly reducing the parallelism. The main goal of the scheduler is to schedule nodes with non-overlapping MFFCs so that each thread block can remove MFFC nodes without synchronization.

[0044] We find that a group of nodes at the same level can be guaranteed to have independent MFFCs. The scheduler starts with the primary input (level = 0) and increments the level after selecting all the nodes in that level. The number of nodes scheduled in a scheduling cycle is a user-defined value, which determines the number of nodes rewritten in parallel (i.e., parallelism). In addition, the proposed level-based node scheduler also simulates the topological order of sequential node scheduling, thereby ensuring the quality of the rewriting results. At the same time, it still provides enough parallel work for parallel logic rewriting.

[0045] 2) Supernode:

[0046] The first step of node replacement is to delete the MFFC node. Considering the level-based node scheduler, this step can be performed without conflict. The second step is to build a new subgraph. In this step, there will be many opportunities for sharing between nodes. Whether to share a node is determined in the node evaluation step, so in this step, the node to be shared may have been deleted or will be deleted as an MFFC node. Therefore, in this process, in order to prevent some threads from reusing nodes that other threads may have deleted or will delete, these threads will create duplicate nodes for the node regardless of whether there is an opportunity for reuse.

[0047] In order to delete these redundant nodes and remove the inefficiency of equivalent nodes on the GPU at the same time, we propose a supernode graph data structure. Specifically, all equivalent nodes in the AIG form a new supernode, and the fan-out number of the supernode is the sum of the fan-out numbers of all equivalent nodes. After the supernode is generated, the fan-out value of each equivalent node is invalid, so that it looks like those equivalent nodes are just one node. Figure 3 shows how to detect all equivalent nodes. To determine whether n0 and n1 are equivalent, we will query their fan-in nodes and corresponding supernodes. In this example, the left fan-in of n0 and n1 are n2 and n3 respectively. It can be observed that n2 and n3 point to the same supernode h0, and the same is true for the right fan-in. Then if the polarity of the input is also the same, n0 and n1 are equivalent. After the entire rewriting process, we scan the entire AIG and replace the fan-in of each node with the corresponding equivalent node, which saves the explicit deletion process of the node on the GPU.

[0048] 2) Intra-node parallelization without recursion

[0049] 1) Parallel cut enumeration:

[0050] The k-feasible cut serial process for a given node is recursive. Specifically, let C1 and C2 be two sets of cuts, then the cut merge operation is defined as:

[0051] C1◇C2={u∪v|u∈C1,v∈C2,|u∪v|≤k} (1)

[0052] In the formula, ◇ represents the symbol of the merge operation of two groups of cuts, and k represents the number of leaf nodes of the cut (“k-feasible” means that the cut has k leaf nodes).

[0053] The set of k-feasible cuts Φ(n) for node n is defined by the following recursive function:

[0054]

[0055] Where PI represents primary input, n.left represents the left child of node n, and n.right represents the right child of node n.

[0056] This recursive process is not suitable for GPU platforms, so we propose a parallel cut enumeration algorithm. When calculating the cut of a node, in order to avoid recursion, it is necessary to ensure that the cuts of the left and right children have been calculated. According to the node scheduler used in the replacement step, only nodes of the same level will be scheduled together. That is, for a new scheduling cycle, the cuts of the newly scheduled nodes at the same level need to be calculated for further processing. In addition, after the replacement, some new nodes are added to the AIG. These added nodes may change the cut set of higher-level nodes. Therefore, the cut sets of these newly added nodes should be calculated before the newly scheduled nodes to ensure the correctness of the cut enumeration function. These added nodes come from different subgraphs at different levels. Therefore, calculating the cuts of these nodes at the same time will lead to dependency problems between nodes. To solve this problem, we propose a bottom-up parallel computing kernel that utilizes sufficient parallelism while ensuring the computational dependencies between nodes.

[0057] like Figure 4 As shown, the parallel cut enumeration algorithm disclosed in the present invention is designed based on the level of the subgraph. CUT_ENUMERATION_KERNEL is the top-level function, which is used to calculate the cut set of a given node. In the previous scheduling cycle, the previous set of scheduled nodes has completed the replacement step. The subgraph used for replacement is recorded, and the nodes in the subgraph are stored in list_nodes. These newly added nodes are divided into different lists LAN[slevel] according to the level of the subgraph (slevel is the local level of the node in the newly added subgraph). The maximum level (ML) of the subgraph is the maximum level of all subgraphs dynamically obtained after the previous set of nodes are replaced. Then, these newly added nodes LAN[slevel] of the same slevel are used as parameters of the PARALLELCUTENUM_ONELEVEL function. PARALLEL_MERGE is to parallelly calculate the cut of these nodes (the implementation of the function is defined in equation (2)). Then the calculated cut is passed to PARALLEL_COMPUTE_BOOLEAN_FUNCTION to calculate the Boolean function corresponding to the cut (used to find equivalent subgraphs in subsequent steps). Since the number of cuts for each node is fixed, the number of cuts will double after merging the cuts, so these cuts will not be retained. The retained cuts are selected by PARALLEL_SELECT_CUTS.

[0058] The core idea of ​​parallel cut enumeration is to process nodes with the same level simultaneously, from lower level to higher level (line 2). This computation mode breaks the dependencies between added nodes. For example, if node n with slevel=4 is being processed, it can safely merge the cut sets of its child nodes, because all nodes with slevel<4 are guaranteed to have a calculated cut set. It also extends sufficient parallelism because all nodes with the same slevel are processed simultaneously. After calculating the cuts of the newly added nodes, the cuts of the next scheduled nodes can be calculated, and these calculated cuts will be used in the following steps.

[0059] 2) Parallel MFCC calculation:

[0060] This paper proposes a top-down computational model to parallelize the recursive MFCC computation algorithm. To unlock parallelism, the proposed method should process multiple nodes simultaneously and efficiently check whether these nodes are in the MFCC. Based on the definition of MFCC, it can be concluded that if all fan-outs of a node (except the root node) are in the MFCC, then this node is also in the MFCC. The core idea of ​​our proposed method is to maintain a subset of the MFCC and the nodes to be processed in the correct order so that the node can be checked whether it is in the MFCC by only looking at the subset of the MFCC.

[0061] like Figure 5As shown, the MFFC algorithm disclosed in the present invention requires three data structures, namely, two lists F1 and F2 for temporarily storing the nodes processed in the middle, and MFFC for storing the set of all the final mffc nodes. The algorithm starts with the cut list that needs to calculate the mffc. Each mffc calculation of a cut is assigned to a thread block, and the threads in the same block collaborate to calculate the mffc of the cut. When the thread block gets the corresponding cut (LC[block_id]), the root node of this cut is first added to the MFFC set corresponding to this node (row 4). The algorithm allocates two buffers F1 and F2 to store the boundaries of the current search. First, the left and right children of the root node are added to F1 (rows 5-6). Each thread extracts a node n from F1 (row 10). If all fan-outs of n are in the current MFFC set, the function IS_MFFC_NODE(n) will be evaluated as true (row 11). Then all children of n (i.e., all fan-outs) are added to F2, and node n is added to MFFC (rows 12-14). After processing all nodes in F1, the for loop ends (line 9), and the roles of F1 and F2 are swapped (lines 17-19). Finally, when all leaf nodes of this cut are processed, FIND_ALL_CUT_LEAVES will be evaluated as true, and the while loop ends (line 7). Since a node may have multiple parents, this node is repeatedly added to F2 (F1 after the role swap), and F1.REMOVE_DUPLICATED_NODES is used to remove duplicate nodes (line 8).

[0062] As mentioned above, based on the definition of mffc, if all the fan-outs of a node (except the root node) are in mffc, then this node is also in mffc. By processing the nodes in PBFS (parallel breadth search) order, all the fan-outs of the node are judged before judging whether the node is in mffc. If the fan-out is an mffc node, it is added to MFFC, so it is sufficient to check whether the node is MFFC only from MFFC. Since all the fan-outs of the current boundary nodes in mffc have been pushed into mffc, nodes from the same boundary will never become each other's fan-outs. Therefore, it is always safe to process these nodes in parallel for mffc calculation.

[0063] The above algorithm is implemented on a computer system with a GPU to achieve rapid synthesis of the circuit.

Claims

1. A logic rewrite acceleration method based on GPU, characterized in that: Parallelize the sub-process of AIG rewriting. Parallel AIG logic rewriting includes the following steps: On the CPU side, the scheduler asynchronously selects a group of nodes with the same level from the input AIG logic network; then, these nodes are copied to the GPU memory, and the GPU sequentially launches kernels to rewrite these nodes in parallel. At the same time, the CPU also starts to select another group of nodes for the GPU to rewrite, completely overlapping the scheduling and rewriting processes; the GPU uses cut enumeration, MFFC calculation, evaluation and replacement to complete the parallel rewriting of nodes, where: The cut enumeration adopts a parallel cut enumeration algorithm designed based on the level of the subgraph. The parallel cut enumeration algorithm is used to process nodes with the same level at the same time, from the lower level to the higher level: the nodes in the subgraph used for replacement in the previous scheduling cycle are divided into different lists LAN[slevel] according to the level of the subgraph. slevel is the local level of the node in the subgraph used for replacement. The cut of the nodes in the same list LAN[slevel] is calculated in parallel, and then the Boolean function corresponding to the cut is calculated; MFFC calculation uses a top-down calculation mode to parallelize the recursive mffc calculation algorithm: starting with the list of cuts that need to calculate mffc, each mffc calculation of a cut is assigned to a thread block, and the threads in the same thread block collaborate to calculate the mffc of the cut. When the thread block gets the corresponding cut: Step 1: The root node of the current cut is added to the MFFC set corresponding to this node. MFFC is the set that stores all the last MFFC nodes. Step 2: The left and right children of the root node are added to the buffer F1. Each thread extracts a node n from the buffer F1. If all the fan-outs of node n are in the current MFFC set, the function IS_MFFC_NODE(n) will be evaluated as true. At this time, all the fan-outs of node n are added to the buffer F2, and node n is added to the MFFC set. Step 3: Repeat step 2 until all nodes in buffer F1 are processed, and then swap the roles of F1 and F2; Step 4: Use the same method from step 2 to step 3 to process a leaf node of the current cut until all leaf nodes of the current cut are processed; In the replacement phase, a lock-free replacement algorithm is used to solve the large amount of data contention that exists in the frequent modification of the logic graph, where: To solve the conflict that different threads holding overlapping MFFCs may delete the same node, a node scheduler is used to group nodes that do not overlap MFFCs; To resolve the conflict that the MFFCs held by different threads do not overlap, but one thread may want to share the node that other threads will delete, the replacement process is divided into two stages: in the first stage, each block of the GPU deletes the MFFC and builds a new subgraph; in the second stage, each block of the GPU combines all equivalent nodes into a supernode, which supports concurrent deletion / creation operations of a node without introducing locks between different threads.

2. A GPU-based logic rewrite acceleration method as claimed in claim 1, characterized in that: The node scheduler is a level-based node scheduler that simulates the topological order of sequential node scheduling, starting from the primary level and increasing the level after selecting all nodes in the level.

3. A GPU-based logic rewrite acceleration method as claimed in claim 2, characterized in that: The number of nodes scheduled by the node scheduler in a scheduling cycle is a user-defined value that determines the degree of parallelism.

4. The GPU-based logic rewrite acceleration method according to claim 1, characterized in that: The fan-out number of the super node is the sum of the fan-out numbers of all the equivalent nodes. After the super node is generated, the fan-out value of each equivalent node becomes invalid.

5. The GPU-based logic rewrite acceleration method according to claim 1, characterized in that: The following method is used to determine whether any two nodes n0 and n1 are equivalent: If all fan-in nodes of nodes n0 and n1 point to the same supernode and the polarity of the inputs is the same, then nodes n0 and n1 are equivalent.

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