Pixel circuit and driving method thereof, display panel and display device

Abstract

The embodiment of the present invention discloses a pixel circuit and its driving method, a display panel and a display device. The pixel circuit includes a driving module and a voltage writing module. The driving method of the pixel circuit includes: in the first stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first end or the control end of the driving module through the voltage writing module; in the second stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first end of the driving module through the voltage writing module. Wherein, the interval length of at least one second stage and its adjacent first stage or second stage is the first duration, and the interval length of any second stage and its adjacent first stage or second stage is the second duration. In at least part of the display cycle: the first duration is different from the total duration of the writing frame, and the absolute value of the difference between the second duration and the total duration of the writing frame is less than or equal to the preset duration. The technical solution of the present invention helps to improve the flicker problem of the display panel.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] With the continuous development of display technology, people have higher and higher requirements for the performance of display panels. Existing display panels can use different refresh rates for display in different display modes. Currently, when display panels display at a low refresh rate, the display screen is prone to flickering. Summary of the Invention

[0003] Embodiments of the present invention provide a pixel circuit and a driving method thereof, a display panel, and a display device to improve the flicker problem of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a method for driving a pixel circuit, the pixel circuit comprising: a driving module and a voltage writing module; the driving module is configured to drive a light-emitting element during a display period, the display period comprising a writing frame and a holding frame; the voltage writing module is connected to a first end of the driving module, and an operating phase of the voltage writing module comprises at least one first phase and at least one second phase, the first phase being in the writing frame, and the second phase being in the holding frame;

[0005] The driving method of the pixel circuit includes:

[0006] In the first stage, the voltage writing module is controlled to be turned on, so as to transmit the reset voltage to the first terminal or the control terminal of the driving module through the voltage writing module;

[0007] In the second stage, the voltage writing module is controlled to be turned on, so as to transmit the reset voltage to the first terminal of the driving module through the voltage writing module;

[0008] Among them, the interval length between at least one of the second stages and its adjacent first stage or second stage is the first length, and the interval length between any one of the second stages and its adjacent first stage or second stage is the second length, and in at least part of the display cycle: the first length is different from the total length of the written frame, and the absolute value of the difference between the second length and the total length of the written frame is less than or equal to the preset length.

[0009] Optionally, the first stage includes a data writing stage, the second stage includes a biasing stage, and the reset voltage includes a data voltage and a bias voltage; the control end of the voltage writing module is connected to the first scanning signal, the first end of the voltage writing module is connected to the reset voltage end, and the second end of the voltage writing module is connected to the first end of the driving module;

[0010] In the first stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal or the control terminal of the driving module through the voltage writing module includes:

[0011] In the data writing phase, a data voltage is provided to the reset voltage terminal to control the voltage writing module to be turned on in response to the first scanning signal and transmit the data voltage to the control terminal of the driving module;

[0012] In the second stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal of the driving module through the voltage writing module includes:

[0013] In the bias phase, a bias voltage is provided to the reset voltage terminal to control the voltage writing module to be turned on in response to the first scanning signal and transmit the bias voltage to the first terminal of the driving module.

[0014] Optionally, the first stage includes a first bias stage, the second stage includes a second bias stage, and the reset voltage includes a bias voltage; the control end of the voltage writing module is connected to the first scan signal, the first end of the voltage writing module is connected to the bias voltage, and the second end of the voltage writing module is connected to the first end of the driving module;

[0015] In the first stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal or the control terminal of the driving module through the voltage writing module includes:

[0016] In the first bias phase, controlling the voltage writing module to be turned on in response to the first scanning signal to transmit the bias voltage to the first end of the driving module;

[0017] In the second stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal of the driving module through the voltage writing module includes:

[0018] In the second bias phase, the voltage writing module is controlled to be turned on in response to the first scanning signal, so as to transmit the bias voltage to the first end of the driving module in the second bias phase.

[0019] Optionally, the control end of the voltage writing module is connected to a first scanning signal, the first scanning signal includes at least two first conduction levels, and the first conduction levels are used to control the voltage writing module to be turned on;

[0020] In at least part of the display period: the interval duration of at least one of the first conduction levels in the first scanning signal and its adjacent first conduction levels is different from the total duration of the write frame, and the absolute value of the difference between the interval duration of any one of the first conduction levels in the first scanning signal and its adjacent first conduction levels and the total duration of the write frame is less than or equal to the preset duration.

[0021] Optionally, the writing frame in each display period is located before the holding frame, at least one of the first conduction levels is located in the writing frame, and at least one of the first conduction levels is located in the holding frame;

[0022] In at least part of the display period: a duration of an interval between at least one of the first conduction level in the hold frame and its previous first conduction level is different from a total duration of the write frame.

[0023] Optionally, at least part of the display period includes the display period having a refresh rate of a target low frequency;

[0024] The refresh rate corresponding to the display period includes a preset low frequency, the target low frequency is a refresh rate lower than the preset low frequency, and in the display period corresponding to the target low frequency, the total duration of the maintained frame is a non-integer multiple of the total duration of the written frame.

[0025] Optionally, the pixel circuit further includes a light emitting control module, wherein the light emitting control module, the driving module, and the light emitting element are connected in series between the first power supply terminal and the second power supply terminal, a control terminal of the light emitting control module receives a light emitting control signal, and the light emitting control module is turned on or off in response to the light emitting control signal;

[0026] The light-emitting control signal includes multiple second conduction levels, and the second conduction levels are used to control the conduction of the light-emitting control module. In the display period corresponding to the target low frequency: the number of the second conduction levels located in the writing frame is n, and the number of the second conduction levels located in the holding frame is m, where n is a positive integer greater than or equal to 2, and m is a non-integer multiple of n.

[0027] Optionally, during at least part of the display period:

[0028] The light emitting control signal includes n level groups located in the write frame and m level groups located in the hold frame, each of the level groups includes a second on-level and an off-level, and the off-level is used to control the light emitting control module to turn off;

[0029] The timing of the first on-level in the first scanning signal overlaps with the timing of the off-level in the light-emitting control signal, and the interval duration between at least one of the first on-levels in the holding frame and its previous first on-level is different from the total duration of the second on-level and the off-level in the n level groups. The absolute value of the difference between the interval duration of any first on-level and its adjacent first on-level and the total duration of the second on-level and the off-level in the n level groups is less than or equal to the preset duration.

[0030] Optionally, the preset duration satisfies: a flickering degree caused by an interval duration between adjacent first conduction levels in the first scanning signal is a flickering degree that cannot be recognized by human eyes.

[0031] Optionally, n includes 2 and positive integer multiples of 2, and the preset duration includes 0.25 times the total duration of the written frame.

[0032] Optionally, the preset low frequency includes 60 Hz, the target low frequency includes 24 Hz, and the light emitting control signal includes the four level groups located in the writing frame and the six level groups located in the holding frame;

[0033] In the display period corresponding to the target low frequency:

[0034] The first scanning signal includes a first on-level located in the write frame and a first on-level located in the hold frame, the first on-level located in the write frame overlaps with the timing of the off-level in the first level group located in the write frame, and the first on-level located in the hold frame overlaps with the timing of the off-level in the second level group located in the hold frame.

[0035] Optionally, the preset low frequency includes 60 Hz, the target low frequency includes 17 Hz, and the light emitting control signal includes the 4 level groups located in the writing frame and the 10 level groups located in the holding frame;

[0036] In the display period corresponding to the target low frequency:

[0037] The first scanning signal includes one first conduction level located in the write frame and two first conduction levels located in the hold frame. The first conduction level located in the write frame overlaps with the timing of the off level in the first level group located in the write frame, the first first conduction level located in the hold frame overlaps with the timing of the off level in the first level group located in the hold frame, and the second first conduction level located in the hold frame overlaps with the timing of the off level in the sixth level group located in the hold frame.

[0038] In a second aspect, based on the same inventive concept, an embodiment of the present invention provides a pixel circuit, including:

[0039] A driving module, configured to drive the light emitting element during a display period, wherein the display period includes a writing frame and a holding frame;

[0040] a voltage writing module connected to the first terminal of the driving module, wherein the working phase of the voltage writing module includes at least one first phase and at least one second phase, the first phase is in the writing frame, and the second phase is in the holding frame, the voltage writing module is configured to transmit a reset voltage to the first terminal or the control terminal of the driving module in the first phase, and transmit the reset voltage to the first terminal of the driving module in the second phase;

[0041] Among them, the interval length between at least one of the second stages and its adjacent first stage or second stage is the first length, and the interval length between any one of the second stages and its adjacent first stage or second stage is the second length, and in at least part of the display cycle: the first length is different from the total length of the written frame, and the absolute value of the difference between the second length and the total length of the written frame is less than or equal to the preset length.

[0042] Optionally, the first stage includes a data writing stage, the second stage includes a biasing stage, and the reset voltage includes a data voltage and a bias voltage;

[0043] The control end of the voltage writing module receives the first scanning signal, the first end of the voltage writing module is connected to the reset voltage end, the reset voltage end receives the data voltage during the data writing phase, the reset voltage end receives the bias voltage during the bias phase, and the second end of the voltage writing module is connected to the first end of the driving module;

[0044] The voltage writing module is configured to respond to the first scanning signal and be turned on during the data writing phase to transmit the data voltage to the control end of the driving module, and to respond to the first scanning signal and be turned on during the bias phase to transmit the bias voltage to the first end of the driving module.

[0045] Optionally, the first stage includes a first bias stage, the second stage includes a second bias stage, and the reset voltage includes a bias voltage;

[0046] The control end of the voltage writing module is connected to the first scanning signal, the first end of the voltage writing module is connected to the bias voltage, and the second end of the voltage writing module is connected to the first end of the driving module;

[0047] The voltage writing module is configured to be turned on in the first bias phase and the second bias phase in response to the first scanning signal, so as to transmit the bias voltage to the first end of the driving module in the first bias phase and the second bias phase respectively.

[0048] In a third aspect, based on the same inventive concept, an embodiment of the present invention provides a display panel comprising the pixel circuit described in the second aspect.

[0049] In a fourth aspect, based on the same inventive concept, an embodiment of the present invention provides a display device comprising the display panel described in the third aspect.

[0050] In a pixel circuit and a driving method thereof, a display panel, and a display device provided by embodiments of the present invention, in a first phase of a write frame of each display cycle, a control voltage write module transmits a reset voltage to a first terminal or a control terminal of a driver module to adjust a voltage state of the driver module. In a second phase of a hold frame of each display cycle, the control voltage write module transmits a reset voltage to the first terminal of the driver module to adjust the voltage state of the driver module. In at least a portion of the display cycle, the interval between at least one second phase and an adjacent first phase or second phase, i.e., a first interval, is set to be different from the total duration of the write frame, and the absolute value of the difference between the interval between each second phase and an adjacent first phase or second phase, i.e., a second interval, and the total duration of the write frame is less than or equal to a preset interval. When the preset interval is short, the intervals between adjacent first phases and second phases, as well as the intervals between two adjacent second phases, in at least a portion of the display cycle are similar or even identical. That is, the intervals at which the voltage write module adjusts the voltage state of the driver module are similar or even identical each time. This helps avoid flickering caused by excessively large time differences in the voltage state changes of the driver module, thereby optimizing the display effect.

[0051] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 This is a schematic structural diagram of a pixel circuit in the related art;

[0054] Figure 2 yes Figure 1 Schematic diagram of driving timing of the pixel circuit in FIG.

[0055] Figure 3 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0056] Figure 4 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0057] Figure 5 is a schematic flow chart of a driving method for a pixel circuit provided by an embodiment of the present invention;

[0058] Figure 6 is a flow chart of another method for driving a pixel circuit provided by an embodiment of the present invention;

[0059] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0060] Figure 8 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0061] Figure 9 is a flow chart of another method for driving a pixel circuit provided by an embodiment of the present invention;

[0062] Figure 10 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0063] Figure 11 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0064] Figure 12is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0065] Figure 13 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0066] Figure 14 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0067] Figure 15 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0069] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products, or devices. Various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention, which will be apparent to those skilled in the art. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present invention can be combined with each other without contradiction.

[0070] As described in the background art, when a display panel displays at a low refresh rate, the display screen is prone to flickering. The inventors have found that the reasons for the above problem are as follows:

[0071] Existing display panels typically use frame skipping to reduce the frequency when performing low-frequency display. For example, when the display panel operates at a low refresh rate, each display frame is set to include a write frame and a hold frame after the write frame. The write frame duration is the same at different refresh rates. By adjusting the hold frame duration, the actual display effect meets the corresponding refresh rate. Generally, when frequency-reducing and interpolating frames, the hold frame duration is set to an integer multiple of the write frame duration. However, at some refresh rates, the hold frame duration is a non-integer multiple of the write frame duration, causing the display to flicker.

[0072] Figure 1 This is a schematic structural diagram of a pixel circuit in the related art; Figure 2 yes Figure 1 The driving timing diagram of the pixel circuit in FIG. Figure 1 and Figure 2 , taking the case where the display panel operates at a 24Hz refresh rate as an example. Each display period P includes a write frame P1 and a hold frame P2. When the duration of the write frame P1 is the duration of each display frame at 60Hz, the duration of the hold frame P2 at 24Hz is a non-integer multiple of the duration of the write frame P1, that is, 1.5 times. The pixel circuit includes a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3 and a light-emitting element D0. The first transistor M1 adjusts the voltage state of the driving transistor M0 in the write frame P1 and the hold frame P2 respectively: in the write frame P1, the first transistor M1 responds to the signal of the scan signal terminal sp and writes the data voltage V1 connected to the first voltage terminal Source into the driving transistor M0; in the hold frame P2, the first transistor M1 responds to the signal of the scan signal terminal sp and writes the bias voltage V2 connected to the first voltage terminal Source into the driving transistor M0 to adjust its bias state.

[0073] Figure 2 The figure shows two groups of signals that can be connected to the scanning signal terminal sp and the light-emitting control signal terminal em in the pixel circuit. In the first working condition of the display panel, the scanning signal terminal sp is connected to the scanning signal sp1, and the light-emitting control signal terminal em is connected to the light-emitting control signal em1. The low-level pulse interval of the scanning signal sp1 in the writing frame P1 and the holding frame P2 of the previous display cycle P is the duration of the four level groups of the light-emitting control signal em1 (a level group is composed of one adjacent high level and one adjacent low level); the low-level pulse interval of the scanning signal sp1 in the holding frame P2 of the previous display cycle P and the writing frame P1 of the next display cycle P is the duration of the six level groups of the light-emitting control signal em1. It can be seen that the time intervals at which the first transistor M1 adjusts the voltage state of the driving transistor M0 are different, and the voltage state of the driving transistor M0 determines the brightness of the light-emitting element D0, which will cause flickering problems.

[0074] In the second operating condition of the display panel, the scan signal terminal sp is connected to the scan signal sp2, and the light-emission control signal terminal em is connected to the light-emission control signal em2. The time interval between the two low-level pulses of the scan signal sp2 in the holding frame P2 is the duration of the four level groups of the light-emission control signal em2; the time interval between the second low-level pulse of the scan signal sp2 in the holding frame P2 and the first low-level pulse of the next display period P is the duration of the two level groups of the light-emission control signal em2. As can be seen, the time intervals at which the first transistor M1 adjusts the voltage state of the driving transistor M0 are different, and the voltage state of the driving transistor M0 determines the brightness of the light-emitting element D0, thus also causing flicker.

[0075] In response to the above problems, an embodiment of the present invention provides a driving method for a pixel circuit, which is used to drive the pixel circuit to operate. The method can be executed by the pixel circuit in any embodiment of the present invention. Figure 3 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention; Figure 4 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention; Figure 5 FIG. 1 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present invention. Figure 3 and Figure 4 The pixel circuit includes: a driving module 10 and a voltage writing module 20. The driving module 10 is used to drive the light-emitting element D1 during a display period F. The display period F includes a writing frame F1 and a holding frame F2. The voltage writing module 20 is connected to the first terminal of the driving module 10. The working phase of the voltage writing module 20 includes at least one first phase t1 and at least one second phase t2. The first phase t1 is in the writing frame F1, and the second phase t2 is in the holding frame F2. Figure 5 , the driving method of the pixel circuit specifically includes the following steps:

[0076] S110 , in the first stage, controlling the voltage writing module to be turned on, so as to transmit the reset voltage to the first terminal or the control terminal of the driving module through the voltage writing module.

[0077] S120 , in the second stage, controlling the voltage writing module to be turned on, so as to transmit the reset voltage to the first terminal of the driving module through the voltage writing module.

[0078] Among them, the interval length between at least one second stage t2 and its adjacent first stage t1 or second stage t2 is the first duration N1, and the interval length between any second stage t2 and its adjacent first stage t1 or second stage t2 is the second duration N2. In at least part of the display period F: the first duration N1 is different from the total duration of the written frame F1, and the absolute value of the difference between the second duration N2 and the total duration of the written frame F1 is less than or equal to the preset duration.

[0079] Combine Figure 3 and Figure 4 Specifically, the light-emitting element D1 can be an organic light-emitting diode (OLED) or a micron-sized light-emitting diode (Micro-LED), etc. Each display cycle F can be understood as a display frame. At some refresh rates of the display panel, each display cycle F includes a write frame F1 and a hold frame F2. The write frame F1 is also called a "refresh frame" or a "data frame". In the write frame F1, the voltage of the control terminal G of the driving module 10 changes, and the driving module 10 generates a driving current according to the voltage of its own control terminal G to drive the light-emitting element D1 to emit light. In the hold frame F2, the voltage of the control terminal G of the driving module 10 remains unchanged, and the driving module 10 can still generate a driving current according to the voltage of its own control terminal G to drive the light-emitting element D1 to emit light.

[0080] Both the write frame F1 and the hold frame F2 include a light-emitting phase and a non-light-emitting phase. The first phase t1 is located in the non-light-emitting phase of the write frame F1, and the second phase t2 is located in the non-light-emitting phase of the hold frame F2. During the first phase t1 of the write frame F1 and the second phase t2 of the hold frame F2 of each display cycle F, the voltage state of the driver module 10 is adjusted by the voltage write module 20. Specifically, during the first phase t1, the voltage write module 20 is controlled to be turned on so that a reset voltage is transmitted to the first terminal of the driver module 10 or the control terminal G of the driver module 10 via the voltage write module 20, thereby resetting the voltage at the first terminal of the driver module 10 or the control terminal G of the driver module 10 to adjust the voltage state of the driver module 10. During the second phase t2, the voltage write module 20 is controlled to be turned on so that a reset voltage is transmitted to the first terminal of the driver module 10 via the voltage write module 20, thereby resetting the voltage at the first terminal of the driver module 10 to adjust the voltage state of the driver module 10.

[0081] The holding frame F2 may include multiple second phases t2, Figure 4The case where the frame F2 includes one second stage t2 is only schematically shown. The first stage t1 adjacent to the second stage t2 may be the first stage t1 in the same display cycle F as the second stage t2, or the first stage t1 in the next display cycle F. The second stage t2 adjacent to the second stage t2 may be two second stages t2 in the same display cycle F. In at least part of the display cycle F, there is at least one second stage t2 with an adjacent first stage t1 or second stage t2, i.e., a first duration N1, which is different from the total duration of the written frame F1, and the absolute value of the difference between the interval between each second stage t2 and the adjacent first stage t1 or second stage t2, i.e., a second duration N2, and the total duration of the written frame F1 is less than or equal to a preset duration. The size of the preset duration can be set according to specific needs.

[0082] For example, in Figure 4 In the two display cycles F shown, the interval between each second stage t2 and its adjacent first stage t1 is the same, that is, the first duration N1 is the same as the second duration N2, and both the first duration N1 and the second duration N2 are different from the total duration of the write frame F1. The absolute value of the difference between the first duration N1 and the total duration of the write frame F1 is less than or equal to the preset duration, and the absolute value of the difference between the second duration N2 and the total duration of the write frame F1 is less than or equal to the preset duration. The advantage of this setting is that it can make the time interval for the voltage writing module 20 to adjust the voltage state of the driving module 10 each time similar or even the same, that is, Figure 4 The time intervals between each two adjacent first stages t1 and second stages t2 are the same, and the voltage state of the driving module 10 determines the brightness of the light-emitting element D1. Therefore, the technical solution of this embodiment helps to avoid flickering caused by excessive time intervals between changes in the voltage state of the driving module 10.

[0083] In summary, according to the technical solution of the embodiments of the present invention, in the first phase of the write frame of each display cycle, the control voltage write module transmits a reset voltage to the first terminal or the control terminal of the driver module to adjust the voltage state of the driver module. In the second phase of the hold frame of each display cycle, the control voltage write module transmits the reset voltage to the first terminal of the driver module to adjust the voltage state of the driver module. By setting the interval length (i.e., the first interval length) between at least one second phase and its adjacent first phase or second phase in at least a portion of the display cycle to be different from the total duration of the write frame, and the absolute value of the difference between the interval length (i.e., the second interval length) between each second phase and its adjacent first phase or second phase and the total duration of the write frame is less than or equal to the preset interval length, when the preset interval length is short, the time intervals between adjacent first phases and second phases, as well as the time intervals between two adjacent second phases, in at least a portion of the display cycle can be similar or even the same. That is, the time intervals at which the voltage write module adjusts the voltage state of the driver module each time are similar or even the same, which helps to avoid flickering caused by excessive time interval differences in the voltage state of the driver module, thereby optimizing the display effect.

[0084] There are many pixel circuit structures applicable to the present invention, and several of them are used as examples for detailed description. Figure 3 The control terminal of the voltage writing module 20 receives the first scanning signal S1, the first terminal of the voltage writing module 20 is connected to the reset voltage terminal, and the reset voltage received by the reset voltage terminal includes the data voltage Data and the bias voltage DVH. The second terminal of the voltage writing module 20 is connected to the first terminal of the driving module 10. Accordingly, the first phase includes the data writing phase, and the second phase includes the biasing phase. Figure 6 FIG is a flow chart of another method for driving a pixel circuit provided by an embodiment of the present invention. Figure 6 , the method specifically comprises the following steps:

[0085] S210 , in a data writing phase, providing a data voltage to the reset voltage terminal to control the voltage writing module to be turned on in response to a first scanning signal and transmit the data voltage to the control terminal of the driving module.

[0086] Combine Figure 3 and Figure 4 Optionally, the pixel circuit further includes a compensation module 30 and a storage module 40. The control terminal of the compensation module 30 is connected to the second scanning signal S2 ( Figure 4 The compensation module 30 is connected between the second terminal of the driving module 10 and the control terminal G. The compensation module 30 is used to compensate for the threshold voltage of the driving module 10. The storage module 40 is connected to the control terminal G of the driving module 10 and is used to store the voltage of the control terminal G of the driving module 10.

[0087] The first stage t1 can be a data writing stage. In the first stage t1 before the light-emitting stage of the writing frame F1, the reset voltage connected to the reset voltage terminal S0 is the data voltage Data, the voltage writing module 20 is turned on in response to the first scanning signal S1, and the compensation module 30 is turned on in response to the second scanning signal S2, so as to transmit the data voltage Data to the control terminal G of the driving module 10 through the voltage writing module 20 and the compensation module 30. At the same time, the threshold voltage of the driving module 10 is compensated by the compensation module 30, and the voltage of the control terminal G of the driving module 10 is stored by the storage module 40, so that the driving module 10 can drive the light-emitting element D1 to emit light according to the voltage stored in the storage module 40 during the light-emitting stage.

[0088] S220 , in a bias phase, providing a bias voltage to the reset voltage terminal to control the voltage writing module to be turned on in response to the first scanning signal and transmit the bias voltage to the first terminal of the driving module.

[0089] The second stage t2 can be a bias stage. In the second stage t2 before the light-emitting stage of the frame F2 is maintained, the reset voltage connected to the reset voltage terminal S0 is the bias voltage DVH. The voltage writing module 20 is turned on in response to the first scanning signal S1, and transmits the bias voltage DVH to the first end of the driving module 10, thereby resetting the voltage of the first end of the driving module 10 to adjust the bias state of the driving module 10, so that the driving module 10 is in the on-bias (OBS) state, which helps to improve display uniformity.

[0090] In the technical solution of this embodiment, the first phase t1 is set as the data writing phase, and the second phase t2 is set as the biasing phase. In the first phase t1, the data voltage Data is transmitted to the control terminal G of the driving module 10 by the voltage writing module 20, and in the second phase t2, the bias voltage DVH is transmitted to the first terminal of the driving module 10 by the voltage writing module 20. Because the interval between at least one second phase t2 and its adjacent first phase t1 or second phase t2, i.e., the first interval N1, is different from the total duration of the writing frame F1, and the absolute value of the difference between the interval between each second phase t2 and its adjacent first phase t1 or second phase t2, i.e., the second interval N2, and the total duration of the writing frame F1 is less than or equal to a preset interval, when the preset interval is short, the interval between adjacent first phases t1 and second phases t2, as well as the interval between two adjacent second phases t2, in at least part of the display period F can be close. In other words, the interval between each adjustment of the voltage state of the driving module 10 by the voltage writing module 20 is close. In particular, in the technical solution of this embodiment, the time intervals between each two adjacent first stages t1 and second stages t2 are the same, and the time intervals for the voltage writing module 20 to adjust the voltage state of the driving module 10 each time are also the same. This helps to avoid flickering caused by excessive time interval differences in the voltage state changes of the driving module 10.

[0091] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention; Figure 8 FIG. 1 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention. Figure 7 and Figure 8 Optionally, the reset voltage includes a bias voltage DVH; the control terminal of the voltage writing module 20 is connected to the first scanning signal S1, the first terminal of the voltage writing module 20 is connected to the bias voltage DVH, and the second terminal of the voltage writing module 20 is connected to the first terminal of the driving module 10. Accordingly, the first phase t1 includes a first bias phase, and the second phase t2 includes a second bias phase. Figure 9 FIG is a flow chart of another method for driving a pixel circuit provided by an embodiment of the present invention. Figure 9 , the method specifically comprises the following steps:

[0092] S310 , in a first bias phase, controlling the voltage writing module to be turned on in response to a first scan signal to transmit the bias voltage to a first terminal of the driving module.

[0093] Combine Figure 7 and Figure 8Optionally, the pixel circuit further includes a data writing module 50, the control end of the data writing module 50 is connected to the third scanning signal S3, and the data writing module 50 is connected to the driving module 10 for writing the data voltage Data into the control end G of the driving module 10.

[0094] The first phase t1 can be a first bias phase. The writing frame F1 also includes a data writing phase, which precedes the first phase t1. Both the data writing phase and the first phase t1 precede the light-emitting phase of the writing frame F1. During the data writing phase, the data writing module 50 is controlled to be turned on in response to the third scanning signal S3, and the compensation module 30 is controlled to be turned on in response to the second scanning signal S2. This allows the data voltage Data to be transmitted to the control terminal G of the driving module 10 via the data writing module 50 and the compensation module 30. During the first phase t1, the voltage writing module 20 is controlled to be turned on in response to the first scanning signal S1. This allows the bias voltage DVH to be transmitted to the first terminal of the driving module 20, thereby resetting the voltage at the first terminal of the driving module 10 and adjusting the bias state of the driving module 10. This allows the driving module 10 to be in the OBS state, thereby improving display uniformity.

[0095] S320 , in the second bias phase, controlling the voltage writing module to be turned on in response to the first scan signal, so as to transmit the bias voltage to the first end of the driving module in the second bias phase.

[0096] The second stage t2 may be a second bias stage. In the second stage t2 before maintaining the light-emitting stage of the frame F2, the control voltage writing module 20 is turned on in response to the first scanning signal S1, and the bias voltage DVH is transmitted to the first end of the driving module 10, so as to reset the voltage of the first end of the driving module 10 to adjust the bias state of the driving module 10, so that the driving module 10 is in the OBS state, which helps to improve display uniformity.

[0097] In the technical solution of this embodiment, the first stage t1 is set as the first bias stage, and the second stage t2 is set as the second bias stage. In the first stage t1 and the second stage t2, the bias voltage DVH is transmitted to the first end of the driving module 10 by the voltage writing module 20, respectively. Because the interval length between at least one second stage t2 and its adjacent first stage t1 or second stage t2, i.e., the first interval length N1, is different from the total duration of the writing frame F1, and the absolute value of the difference between the interval length between each second stage t2 and its adjacent first stage t1 or second stage t2, i.e., the second interval length N2, and the total duration of the writing frame F1 is less than or equal to the preset interval length, when the preset interval length is short, the intervals between adjacent first stages t1 and second stages t2, as well as the intervals between two adjacent second stages t2, in at least part of the display period F, can be similar. In other words, the intervals between each adjustment of the bias state of the driving module 10 by the voltage writing module 20 are similar. In particular, in the technical solution of this embodiment, the time interval between each two adjacent first stages t1 and second stages t2 is the same, and the time interval for the voltage writing module 20 to adjust the bias state of the driving module 10 each time is also the same. This helps to avoid the flicker phenomenon caused by the time interval difference between the changes in the bias state of the driving module 10 being too large.

[0098] Combine Figure 3 and Figure 4 ,or Figure 7 and Figure 8 Based on the above embodiments, the first scanning signal S1 includes at least two first conduction levels, and the first conduction levels are used to control the conduction of the voltage writing module 20. During at least a portion of the display period F, the duration of at least one first conduction level in the first scanning signal S1 and the interval between adjacent first conduction levels are different from the total duration of the writing frame F1, and the absolute value of the difference between the duration of any first conduction level in the first scanning signal S1 and the interval between adjacent first conduction levels and the total duration of the writing frame F1 is less than or equal to a predetermined duration.

[0099] Specifically, the voltage writing module 20 can be composed of a thin film transistor. When the voltage writing module 20 is composed of a P-type transistor, the first conduction level is a low level. When the voltage writing module 20 is composed of an N-type transistor, the first conduction level is a high level. Figure 4 and Figure 8In the example where the first conduction level in the first scanning signal S1 is a low level, when the control terminal of the voltage writing module 20 is connected to the first conduction level, the voltage writing module 20 is turned on, and the data voltage Data is transmitted to the control terminal of the driving module 10 through the voltage writing module 20 to adjust the voltage state of the driving module 10, or the bias voltage DVH is transmitted to the first terminal of the driving module 10 through the voltage writing module 20 to adjust the voltage state of the driving module 10.

[0100] The duration of the interval between the first conduction level and its adjacent first conduction levels in the first scanning signal S1 determines the time interval for each adjustment of the voltage state of the driving module 10 by the voltage writing module 20. By setting the duration of the interval between at least one first conduction level and its adjacent first conduction levels in the first scanning signal S1 to be different from the total duration of the writing frame F1, and the absolute value of the difference between the duration of the interval between each first conduction level and its adjacent first conduction levels and the total duration of the writing frame F1 to be less than or equal to the preset duration, when the preset duration is short, the duration of the interval between at least some adjacent first conduction levels in the first scanning signal S1 can be similar, that is, the time interval for each adjustment of the voltage state of the driving module 10 by the voltage writing module 20 is similar. Figure 4 and Figure 8 Both figures show the case where the intervals between each two adjacent first conduction levels in the first scanning signal S1 are the same, so that the time intervals for the voltage writing module 20 to adjust the voltage state of the driving module 10 each time are also the same. This helps to avoid flickering caused by excessive time intervals between changes in the voltage state of the driving module 10.

[0101] Combine Figure 3 and Figure 4 ,or Figure 7 and Figure 8 Furthermore, in each display period F, the write frame F1 precedes the hold frame F2, at least one first conduction level is in the write frame F1, and at least one first conduction level is in the hold frame F2. In at least a portion of the display period F, the duration of the interval between at least one first conduction level in the hold frame F2 and the preceding first conduction level is different from the total duration of the write frame F1.

[0102] Specifically, in practical applications, the number of first conduction levels in the first scanning signal S1 can be set according to the total duration of the writing frame F1 and the total duration of the holding frame F2 in each display period F, and the timing of holding the first conduction level in the frame F2 can be adjusted. For example, Figure 4 or Figure 8As shown, when the total duration of the holding frame F2 is 1.5 times the total duration of the writing frame F1, the first scanning signal S1 can be set to include a first conduction level located in the writing frame F1 and a first conduction level located in the holding frame F2. By adjusting the timing of the first conduction level of the holding frame F2, the interval length between the first conduction level of the holding frame F2 and the first conduction level of the writing frame F1 in the same display period F is made to be 1.5 times the total duration of the writing frame F1, that is, different from the total duration of the writing frame F1. The interval length between each two adjacent first conduction levels in the first scanning signal S1 can be made the same, so that the time interval for the voltage writing module 20 to adjust the voltage state of the driving module 10 each time is also the same, thereby helping to avoid the flicker phenomenon caused by excessive time interval difference in the voltage state change of the driving module 10.

[0103] See also Figure 4 or Figure 8 Optionally, at least part of the display cycle F includes a display cycle F with a refresh rate of a target low frequency, the refresh rate corresponding to the display cycle F includes a preset low frequency, the target low frequency is a refresh rate lower than the preset low frequency, and in the display cycle F corresponding to the target low frequency, the total duration of the frame F2 is maintained as a non-integer multiple of the total duration of the written frame F1.

[0104] In one embodiment, the preset low frequency includes 60 Hz, the target low frequency is a refresh rate lower than 60 Hz, and in a display period F corresponding to the target low frequency, the total duration of the maintained frame F2 is a non-integer multiple of the total duration of the written frame F1. For example, when the preset low frequency is 60 Hz, the total duration of the written frame F1 at the target low frequency is the total duration of each display frame at 60 Hz, and the total duration of the maintained frame F2 at the target low frequency is a non-integer multiple of the total duration of the written frame F1. Figure 4 and Figure 8 The refresh rates corresponding to the driving timings shown are all at the target low frequency, which is 24 Hz. When the refresh rate of the display panel is 24 Hz, the total duration of the 24 Hz write frame F1 can be set to the total duration of each display frame at 60 Hz, and the total duration of the frame F2 can be kept 1.5 times the total duration of the write frame F1, so that the total duration of each display cycle F can meet the total duration of each display frame at 24 Hz.

[0105] In other embodiments, the preset low frequency is not limited to 60 Hz, and the target low frequency is not limited to 24 Hz. The target low frequency satisfies a refresh rate lower than the preset low frequency, and the total duration of the write frame F1 of the target low frequency is the total duration of each display frame under the preset low frequency, and the total duration of the frame F2 is kept as a non-integer multiple of the total duration of the write frame F1.

[0106] Combine Figure 3 and Figure 4 ,or Figure 7 and Figure 8 Optionally, the pixel circuit further includes a light-emission control module 60. The light-emission control module 60, the driving module 10, and the light-emitting element D1 are connected in series between the first power supply terminal and the second power supply terminal. The control terminal of the light-emission control module 60 receives a light-emission control signal EM, and the light-emission control module 60 is turned on or off in response to the light-emission control signal EM. The light-emission control signal EM includes a plurality of second conduction levels, which are used to control the conduction of the light-emission control module 60. In a display period F corresponding to the target low frequency, the number of second conduction levels in the write frame F1 is n, and the number of second conduction levels in the hold frame F2 is m, where n is a positive integer greater than or equal to 2, and m is a non-integer multiple of n.

[0107] Specifically, the first power supply terminal is connected to the first power supply voltage PVDD, and the second power supply terminal is connected to the second power supply voltage PVEE. During the light-emitting phase of writing frame F1 and holding frame F2, the light-emitting control module 60 is turned on in response to the light-emitting control signal EM, forming a conductive path between the first power supply terminal and the second power supply terminal. The driver module 10 generates a driving current based on the voltage at its control terminal G, thereby driving the light-emitting element D1 to emit light. During the non-light-emitting phase of writing frame F1 and holding frame F2, the light-emitting control module 60 is turned off in response to the light-emitting control signal EM, preventing the conductive path from being formed between the first power supply terminal and the second power supply terminal, and the driver module 10 stops driving the light-emitting element D1 to emit light.

[0108] The light emitting control module 60 may be composed of a thin film transistor. When the light emitting control module 60 is composed of a P-type transistor, the second conduction level is a low level. When the light emitting control module 60 is composed of an N-type transistor, the second conduction level is a high level. Figure 4 and Figure 8 The following examples illustrate the case where the second conduction level in the light-emitting control signal EM is a low level. The number of second conduction levels in the light-emitting control signal EM during each display period F determines the duration of light-emitting element D1's illumination. When the preset low frequency is 60 Hz, the number n of second conduction levels in the light-emitting control signal EM written into frame F1 during display period F corresponding to the target low frequency is consistent with the number of second conduction levels in the light-emitting control signal EM in each display frame at 60 Hz. Furthermore, the number of second conduction levels in the light-emitting control signal EM in hold frame F2 is m, which is a non-integer multiple of n. For example, the number of second conduction levels in the light-emitting control signal EM per display frame at 60 Hz is four. For display period F corresponding to the target low frequency of 24 Hz, n = 4 and m = 1.5.

[0109] Combine Figure 3 and Figure 4 ,or Figure 7 and Figure 8Furthermore, during at least a portion of the display period F, the light-emission control signal EM includes n level groups in the write frame F1 and m level groups in the hold frame F2. Each level group includes a second on-level and an off-level, with the off-level being used to control the light-emission control module 60 to turn off. The timing of the first on-level in the first scanning signal S1 overlaps with the timing of the off-level in the light-emission control signal EM. The duration of the interval between at least one first on-level in the hold frame F2 and its preceding first on-level is different from the total duration of the second on-level and the off-level in the n level groups. The absolute value of the difference between the duration of the interval between any first on-level and its adjacent first on-level and the total duration of the second on-level and the off-level in the n level groups is less than or equal to a predetermined duration.

[0110] One of the second on-level and the off-level is a high level, and the other is a low level. The total duration of the writing frame F1 in a display cycle F is equal to the total duration of the second on-level and the off-level in the n level groups.

[0111] When the display panel displays at a refresh rate lower than the preset low frequency, it uses frame insertion to reduce the frequency. That is, a hold frame is inserted after the write frame in each display cycle. For refresh rates below the preset low frequency, the duration of the inserted hold frame is an integer multiple of the duration of the write frame. For example, if the preset low frequency is 60Hz and the current refresh rate of the display panel is 15Hz, the total duration of the write frame in each display cycle is the total duration of each display cycle at 60Hz. If a hold frame is inserted after the write frame, the total duration of the hold frame is three times the total duration of the write frame.

[0112] When the display panel displays at a target low frequency lower than the preset low frequency, the duration of the hold frame F2 inserted in each display period F is a non-integer multiple of the duration of the write frame F1. For example, the light-emitting control signal EM in each display period F at the preset low frequency includes n level groups, and the duration of each display period is the duration corresponding to the n level groups. If the current refresh rate of the display panel is the target low frequency, the light-emitting control signal EM in the write frame F1 of each display period F includes n level groups. Based on the write frame F1, the number of level groups in the light-emitting control signal EM is increased by longV, that is, the hold frame F2 is inserted after the write frame F1, and the light-emitting control signal EM in the hold frame F2 is set to include m level groups, where m is a non-integer multiple of n. In other words, the duration corresponding to the hold frame F2 is a non-integer multiple of the duration corresponding to the write frame F1.

[0113] For example, see Figure 4 or Figure 8The current refresh rate of the display panel is a target low frequency, which is 24 Hz, and the preset low frequency is 60 Hz. If the light-emission control signal EM in each display period F at 60 Hz includes four level groups, then the light-emission control signal EM in the write frame F1 of each display period F at 24 Hz includes four level groups, and the light-emission control signal EM in the hold frame F2 includes six level groups. The duration of the hold frame F2 is a non-integer multiple of the duration of the write frame F1. On this basis, by setting the timing of the first on-level in the first scanning signal S1 and the off-level in the light-emitting control signal EM to overlap, the first stage t1 and the second stage t2 can both be carried out in the non-light-emitting stage, and by setting the interval duration of at least one first on-level in the first scanning signal S1 and its previous first on-level in the holding frame F2 to be different from the total duration of the second on-level and the off-level in the n level groups, that is, the first duration N1 is different from the total duration of the write frame F1, and by setting the absolute value of the difference between any first on-level in the first scanning signal S1 and its adjacent first on-level and the total duration of the second on-level and the off-level in the n level groups is less than or equal to the preset duration, that is, the absolute value of the difference between the second duration N2 and the total duration of the write frame F1 is less than or equal to the preset duration.

[0114] Based on the above embodiments, optionally, the preset duration satisfies: the flickering degree caused by the interval duration of adjacent first conduction levels in the first scanning signal S1 is a flickering degree that cannot be recognized by human eyes.

[0115] In the prior art, combined Figure 1 and Figure 2 The durations of adjacent low-level pulses in the scanning signal sp include the durations of the two-level group, the four-level group, and the six-level group of the light-emitting control signal em. This results in significant differences in the durations of adjacent low-level pulses, causing different time intervals for the first transistor M1 to adjust the voltage state of the driving transistor M0, thereby causing flicker. Compared to the prior art, the technical solution of this embodiment sets the absolute value of the difference between the duration of the interval between any first conduction level in the first scanning signal S1 and its adjacent first conduction levels and the total duration of the write frame F1 to be less than or equal to a preset duration. The preset duration satisfies the requirement that the flicker caused by the duration of the interval between adjacent first conduction levels in the first scanning signal S1 is not perceptible to the human eye. This ensures that the time intervals for each adjustment of the voltage state of the driving module 10 by the voltage writing module 20 are similar or even identical, thereby alleviating the flickering phenomenon caused by the large time interval difference between the voltage state changes of the driving module 10.

[0116] Optionally, n includes 2 and positive integer multiples of 2, and the preset duration includes 0.25 times the total duration of the write frame F1. Exemplarily, when n=2, the light-emitting control signal EM in each display cycle F at the preset low frequency includes 2 level groups, and the total duration of the write frame F1 in each display cycle F at the target low frequency corresponds to the total duration of the 2 level groups, and the preset duration is 0.25 times the total duration of the 2 level groups, that is, the total duration of 0.5 level groups; when n=4, the light-emitting control signal EM in each display cycle F at the preset low frequency includes 4 level groups, and the total duration of the write frame F1 in each display cycle F at the target low frequency corresponds to the total duration of the 4 level groups, and the preset duration is 0.25 times the total duration of the 4 level groups, that is, the total duration of 1 level group. When n takes other values, the calculation method of the preset duration can be deduced by analogy.

[0117] Combine Figure 3 and Figure 4 ,or Figure 7 and Figure 8 In one embodiment, the preset low frequency is 60 Hz, the target low frequency is 24 Hz, and the light-emitting control signal EM includes four level groups in the write frame F1 and six level groups in the hold frame F2. During a display period F corresponding to the target low frequency, the first scanning signal S1 includes a first on-level in the write frame F1 and a first on-level in the hold frame F2. The first on-level in the write frame F1 overlaps with the timing of the off-level in the first level group in the write frame F1, and the first on-level in the hold frame F2 overlaps with the timing of the off-level in the second level group in the hold frame F2.

[0118] In this embodiment, based on a preset low frequency of 60 Hz, interpolation and downsampling are performed using a longV method to meet the target low frequency display requirement of 24 Hz. The total duration of the write frame F1 corresponds to the total duration of the four level groups of the light-emission control signal EM. In the hold frame F2, the timing of the first on-level of the first scanning signal S1 and the off-level in the second level group of the light-emission control signal EM are set to overlap. This ensures that the interval between each adjacent first on-level of the first scanning signal S1 is the total duration of the five level groups of the light-emission control signal EM, and the difference between the interval between each adjacent first on-level of the first scanning signal S1 and the total duration of the write frame F1 is the total duration of one level group, i.e., the preset duration is the total duration of one level group. This allows the voltage write module 20 to alternately adjust the voltage state of the driver module 10 in the first phase t1 and the second phase t2, with the time interval for each adjustment of the voltage state of the driver module 10 being the same. This alleviates the flickering phenomenon caused by the large time interval difference between the voltage state changes of the driver module 10.

[0119] Figure 10 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention, which is suitable for driving Figure 3 The pixel circuit shown; Figure 11 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention, which is suitable for driving Figure 7 The pixel circuit shown in FIG. Figure 3 and Figure 10 ,or Figure 7 and Figure 11 In another embodiment, the preset low frequency is 60 Hz, the target low frequency is 17 Hz, and the light-emitting control signal EM includes four level groups in the write frame F1 and ten level groups in the hold frame F2. In a display period F corresponding to the target low frequency, the first scanning signal S1 includes a first on-level in the write frame F1 and two first on-levels in the hold frame F2. The first on-level in the write frame F1 overlaps with the timing of the off-level in the first level group in the write frame F1, the first on-level in the hold frame F2 overlaps with the timing of the off-level in the first level group in the hold frame F2, and the second on-level in the hold frame F2 overlaps with the timing of the off-level in the sixth level group in the hold frame F2.

[0120] For example, based on the preset low frequency of 60 Hz, frame insertion and frequency reduction are performed in a longV manner to meet the display requirement of the target low frequency of 17 Hz. The total duration of each display period F at 60 Hz corresponds to the total duration of the four level groups of the light-emitting control signal EM. The total duration of the write frame F1 of each display period F at 17 Hz corresponds to the total duration of the four level groups of the light-emitting control signal EM. The total duration of the hold frame F2 corresponds to the total duration of the 10 level groups of the light-emitting control signal EM. The total duration of the hold frame F2 is a non-integer multiple of the total duration of the write frame F1. In the hold frame F2, by setting the timing of the first first on-level of the first scanning signal S1 to overlap with the timing of the off-level in the first level group of the light-emitting control signal EM, and the timing of the second first on-level of the first scanning signal S1 to overlap with the timing of the off-level in the sixth level group of the light-emitting control signal EM, the interval durations of a portion of adjacent first on-levels in the first scanning signal S1 are equal to the total duration of the five level groups of the light-emitting control signal EM, and the interval durations of another portion of adjacent first on-levels are equal to the total duration of the four level groups of the light-emitting control signal EM. When the preset duration is the total duration of one level group, the difference between the interval durations of each two adjacent first on-levels in the first scanning signal S1 and the total duration of the write frame F1 is less than or equal to the total duration of one level group. This ensures that the time intervals for each adjustment of the voltage state of the driving module 10 by the voltage writing module 20 are similar, thereby improving the flicker phenomenon caused by the large time interval difference between changes in the voltage state of the driving module 10.

[0121] It should be noted that Figure 4 、 Figure 8 、 Figure 10 and Figure 11 The refresh rates of the display panel are 24Hz and 17Hz as examples for illustration. In actual applications, the refresh rates applicable to the technical solution of the present invention may include multiple ones, including but not limited to any target low frequency lower than the preset low frequency, and a target low frequency that keeps the total duration of the frame as a non-integer multiple of the total duration of the written frame.

[0122] The embodiment of the present invention further provides a pixel circuit, which can be driven by the driving method of the pixel circuit provided by any embodiment of the present invention. Figure 3 and Figure 4 , the pixel circuit comprises:

[0123] A driving module 10 is configured to drive the light emitting element D1 during a display period F, wherein the display period F includes a writing frame F1 and a holding frame F2;

[0124] The voltage writing module 20 is connected to the first end of the driving module 10. The working phase of the voltage writing module 20 includes at least one first phase t1 and at least one second phase t2. The first phase t1 is in the writing frame F1, and the second phase t2 is in the holding frame F2. The voltage writing module 20 is used to transmit the reset voltage to the first end or the control end G of the driving module 10 in the first phase t1, and transmit the reset voltage to the first end of the driving module 10 in the second phase t2.

[0125] Among them, the interval length between at least one second stage t2 and its adjacent first stage t1 or second stage t2 is the first duration N1, and the interval length between any second stage t2 and its adjacent first stage t1 or second stage t2 is the second duration N2. In at least part of the display period F: the first duration N1 is different from the total duration of the written frame F1, and the absolute value of the difference between the second duration N2 and the total duration of the written frame F1 is less than or equal to the preset duration.

[0126] According to a technical solution of an embodiment of the present invention, in a first phase of a write frame of each display cycle, a control voltage write module transmits a reset voltage to a first terminal or a control terminal of a driver module to adjust a voltage state of the driver module. In a second phase of a hold frame of each display cycle, the control voltage write module transmits a reset voltage to the first terminal of the driver module to adjust the voltage state of the driver module. By setting an interval length (i.e., a first interval length) between at least one second phase and an adjacent first phase or second phase in at least a portion of the display cycle, which is different from the total duration of the write frame, and the absolute value of the difference between the interval length (i.e., a second interval length) between each second phase and its adjacent first phase or second phase and the total duration of the write frame is less than or equal to a preset interval length, when the preset interval length is short, the intervals between adjacent first phases and second phases, as well as the intervals between two adjacent second phases, in at least a portion of the display cycle can be similar or even the same. That is, the intervals at which the voltage write module adjusts the voltage state of the driver module each time are similar or even the same, which helps to avoid flickering caused by excessive time differences in the voltage state changes of the driver module, thereby optimizing the display effect.

[0127] Combine Figure 3 and Figure 4In one embodiment, optionally, the first phase t1 includes a data writing phase, the second phase t2 includes a biasing phase, and the reset voltage includes a data voltage Data and a bias voltage DVH. The control terminal of the voltage writing module 20 receives the first scanning signal S1, the first terminal of the voltage writing module 20 is connected to the reset voltage terminal, the reset voltage terminal receives the data voltage Data during the data writing phase, the reset voltage terminal S0 receives the bias voltage DVH during the biasing phase, and the second terminal of the voltage writing module 20 is connected to the first terminal of the driving module 10. The voltage writing module 20 is configured to turn on in response to the first scanning signal S1 during the data writing phase to transmit the data voltage Data to the control terminal G of the driving module 10, and to turn on in response to the first scanning signal S1 during the biasing phase to transmit the bias voltage DVH to the first terminal of the driving module 10.

[0128] Figure 12 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 12 On the basis of the above embodiment, optionally, the pixel circuit further includes a compensation module 30 , a storage module 40 , a light emitting control module 60 , a first initialization module 70 and a second initialization module 80 .

[0129] The control terminal of the compensation module 30 receives the second scan signal S2. The compensation module 30 is connected between the second terminal of the driver module 10 and the control terminal G, and is used to compensate for the threshold voltage of the driver module 10. The first terminal of the storage module 40 is connected to the control terminal G of the driver module 10, and the second terminal of the storage module 40 is connected to a fixed voltage. The storage module 40 is used to store the voltage at the control terminal G of the driver module 10. The light control module 60, the driver module 10, and the light-emitting element D1 are connected in series between the first power terminal and the second power terminal. The control terminal of the light control module 60 receives the light control signal EM, and the light control module 60 is turned on or off in response to the light control signal EM. The control terminal of the first initialization module 70 receives the fourth scan signal S4. The first terminal of the first initialization module 70 receives the first initialization voltage Vref1, and the second terminal of the first initialization module 70 is connected to the control terminal G of the driver module 10. The first initialization module 70 is used to write the first initialization voltage Vref1 to the control terminal G of the driver module 10. The control end of the second initialization module 80 is connected to the third scanning signal S3, the first end of the second initialization module 80 is connected to the second initialization voltage Vref2, and the second end of the second initialization module 80 is connected to the first electrode of the light-emitting element D1. The second initialization module 80 is used to write the second initialization voltage Vref2 into the first electrode of the light-emitting element D1.

[0130] Furthermore, the driving module 10 includes a driving transistor DT, the voltage writing module 20 includes a first transistor T1, the compensation module 30 includes a second transistor T2, the light control module 60 includes a third transistor T3 and a fourth transistor T4, the first initialization module 70 includes a fifth transistor T5, the second initialization module 80 includes a sixth transistor T6, and the storage module 40 includes a storage capacitor Cst. The gate of the first transistor T1 is connected to the first scanning signal S1, the first electrode of the first transistor T1 is connected to the reset voltage terminal, and the second electrode of the first transistor T1 is connected to the first electrode of the driving transistor DT. The gate of the second transistor T2 is connected to the second scanning signal S2, the first electrode of the second transistor T2 is connected to the second electrode of the driving transistor DT, and the second electrode of the second transistor T2 is connected to the gate of the driving transistor DT. The gates of the third transistor T3 and the fourth transistor T4 are both connected to the light control signal EM, the third transistor T3 is connected between the first power supply terminal and the first electrode of the driving transistor DT, and the fourth transistor T4 is connected between the second electrode of the driving transistor DT and the first electrode of the light-emitting element D1. The gate of the fifth transistor T5 is connected to the fourth scan signal S4, the first electrode of the fifth transistor T5 is connected to the first initialization voltage Vref1, and the second electrode of the fifth transistor T5 is connected to the gate of the driving transistor DT. The gate of the sixth transistor T6 is connected to the third scan signal S3, the first electrode of the sixth transistor T6 is connected to the second initialization voltage Vref2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element D1. The first electrode of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the second electrode of the storage capacitor Cst is connected to a fixed voltage, for example, the second electrode of the storage capacitor Cst is connected to the first power supply terminal to receive the first power supply voltage PVDD.

[0131] Combine Figure 7 and Figure 8 In another embodiment, optionally, the first phase t1 includes a first bias phase, the second phase t2 includes a second bias phase, and the reset voltage includes a bias voltage DVH. The control terminal of the voltage writing module 20 is connected to the first scan signal S1, the first terminal of the voltage writing module 20 is connected to the bias voltage DVH, and the second terminal of the voltage writing module 20 is connected to the first terminal of the driver module 10. The voltage writing module 20 is configured to be turned on in response to the first scan signal S1 during the first bias phase and the second bias phase, thereby transmitting the bias voltage DVH to the first terminal of the driver module 10 in the first bias phase and the second bias phase, respectively.

[0132] Furthermore, the pixel circuit also includes a data writing module 50, the control end of the data writing module 50 is connected to the third scanning signal S3, the first end of the data writing module 50 is connected to the data voltage Data, the second end of the data writing module 50 is connected to the driving module 10, and the data writing module 50 is used to write the data voltage Data to the control end G of the driving module 10. Figure 7 The figure shows a case where the second end of the data writing module 50 is connected to the first end of the driving module 10 so that the data voltage Data is written into the control end G of the driving module 10 through the data writing module 50 and the compensation module 30. In other embodiments, the second end of the data writing module 50 can also be connected to the control end G of the driving module 10 so that the data voltage Data is directly written into the control end G of the driving module 10 through the data writing module 50.

[0133] Figure 13 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 13 Based on the above embodiment, optionally, the driving module 10 includes a driving transistor DT, the voltage writing module 20 includes a first transistor T1, and the data writing module 50 includes a seventh transistor T7. The gate of the first transistor T1 is connected to the first scan signal S1, the first electrode of the first transistor T1 is connected to the bias voltage DVH, and the second electrode of the first transistor T1 is connected to the first electrode of the driving transistor DT. The gate of the seventh transistor T7 is connected to the third scan signal S3, the first electrode of the seventh transistor T7 is connected to the data voltage Data, and the second electrode of the seventh transistor T7 is connected to the first electrode or gate of the driving transistor DT. Figure 13 The structures of other modules and transistors in the pixel circuit shown are similar to those in FIG. Figure 12 The pixel circuits shown are similar, and may be understood with reference to the above embodiments for details.

[0134] An embodiment of the present invention further provides a display panel, comprising the pixel circuit in any embodiment of the present invention. Figure 14 Schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 14 The display panel may include multiple rows of pixel circuits 100. The display panel may be an OLED display panel or a Micro-LED display panel. The display panel provided by the embodiments of the present invention includes the pixel circuits of any embodiment of the present invention and has the corresponding functional modules and beneficial effects of the pixel circuits, which will not be described in detail here.

[0135] An embodiment of the present invention further provides a display device. Figure 15 Schematic diagram of a display device according to an embodiment of the present invention. Figure 15The display device 200 provided in an embodiment of the present invention includes the display panel of any of the above embodiments, and thus has the corresponding functional structure and beneficial effects of the display panel, which will not be described in detail here. The display device 200 can be a mobile phone, or it can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., which are not particularly limited in the embodiment of the present invention.

[0136] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0137] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for driving a pixel circuit, characterized in that: The pixel circuit includes: a driving module and a voltage writing module; the driving module is used to drive the light-emitting element in a display period, and the display period includes a writing frame and a holding frame; the voltage writing module is connected to the first end of the driving module, and the working phase of the voltage writing module includes at least one first phase and at least one second phase, the first phase is in the writing frame, and the second phase is in the holding frame; The driving method of the pixel circuit includes: In the first stage, the voltage writing module is controlled to be turned on, so as to transmit the reset voltage to the first terminal or the control terminal of the driving module through the voltage writing module; In the second stage, the voltage writing module is controlled to be turned on, so as to transmit the reset voltage to the first terminal of the driving module through the voltage writing module; The interval between at least one of the second stages and its adjacent first stage or second stage is a first duration, and the interval between any one of the second stages and its adjacent first stage or second stage is a second duration. In at least part of the display period: the first duration is different from the total duration of the written frame, and the second duration is the same as or tends to be the same as the total duration of the written frame. When the first duration and the second duration are not the same interval duration, the first duration and the second duration are the same or tend to be the same; At least part of the display period includes the display period having a target low frequency refresh rate; The refresh rate corresponding to the display period includes a preset low frequency, the target low frequency is a refresh rate lower than the preset low frequency, and in the display period corresponding to the target low frequency, the total duration of the maintained frame is a non-integer multiple of the total duration of the written frame.

2. The driving method of the pixel circuit according to claim 1, wherein: The first stage includes a data writing stage, the second stage includes a biasing stage, and the reset voltage includes a data voltage and a bias voltage; the control end of the voltage writing module is connected to the first scanning signal, the first end of the voltage writing module is connected to the reset voltage end, and the second end of the voltage writing module is connected to the first end of the driving module; In the first stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal or the control terminal of the driving module through the voltage writing module includes: In the data writing phase, a data voltage is provided to the reset voltage terminal to control the voltage writing module to be turned on in response to the first scanning signal and transmit the data voltage to the control terminal of the driving module; In the second stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal of the driving module through the voltage writing module includes: In the bias phase, a bias voltage is provided to the reset voltage terminal to control the voltage writing module to be turned on in response to the first scanning signal and transmit the bias voltage to the first terminal of the driving module.

3. The driving method of the pixel circuit according to claim 1, wherein: The first stage includes a first bias stage, the second stage includes a second bias stage, and the reset voltage includes a bias voltage; the control end of the voltage writing module is connected to the first scan signal, the first end of the voltage writing module is connected to the bias voltage, and the second end of the voltage writing module is connected to the first end of the driving module; In the first stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal or the control terminal of the driving module through the voltage writing module includes: In the first bias phase, controlling the voltage writing module to be turned on in response to the first scanning signal to transmit the bias voltage to the first end of the driving module; In the second stage, controlling the voltage writing module to be turned on so as to transmit the reset voltage to the first terminal of the driving module through the voltage writing module includes: In the second bias phase, the voltage writing module is controlled to be turned on in response to the first scanning signal, so as to transmit the bias voltage to the first end of the driving module in the second bias phase.

4. The driving method of the pixel circuit according to claim 1, wherein: The control end of the voltage writing module is connected to a first scanning signal, wherein the first scanning signal includes at least two first conduction levels, and the first conduction levels are used to control the conduction of the voltage writing module; In at least part of the display period: the interval duration of at least one of the first conduction levels in the first scanning signal and its adjacent first conduction levels is different from the total duration of the write frame, and the absolute value of the difference between the interval duration of any one of the first conduction levels in the first scanning signal and its adjacent first conduction levels and the total duration of the write frame is less than or equal to the preset duration.

5. The driving method of the pixel circuit according to claim 4, wherein: The writing frame in each of the display cycles is located before the holding frame, at least one of the first conduction levels is located in the writing frame, and at least one of the first conduction levels is located in the holding frame; In at least part of the display period: a duration of an interval between at least one of the first conduction level in the hold frame and its previous first conduction level is different from a total duration of the write frame.

6. The driving method of the pixel circuit according to claim 1, wherein: The pixel circuit further includes a light emitting control module, wherein the light emitting control module, the driving module, and the light emitting element are connected in series between a first power supply terminal and a second power supply terminal, a control terminal of the light emitting control module receives a light emitting control signal, and the light emitting control module is turned on or off in response to the light emitting control signal; The light-emitting control signal includes multiple second conduction levels, and the second conduction levels are used to control the conduction of the light-emitting control module. In the display period corresponding to the target low frequency: the number of the second conduction levels located in the writing frame is n, and the number of the second conduction levels located in the holding frame is m, where n is a positive integer greater than or equal to 2, and m is a non-integer multiple of n.

7. The driving method of a pixel circuit according to any one of claims 1 to 6, characterized in that: During at least part of said display period: The light emitting control signal includes n level groups located in the write frame and m level groups located in the hold frame, each of the level groups includes a second on-level and an off-level, and the off-level is used to control the light emitting control module to turn off; The timing of the first on-level in the first scanning signal overlaps with the timing of the off-level in the light-emitting control signal, and the interval duration between at least one of the first on-levels in the holding frame and its previous first on-level is different from the total duration of the second on-level and the off-level in the n level groups. The absolute value of the difference between the interval duration of any first on-level and its adjacent first on-level and the total duration of the second on-level and the off-level in the n level groups is less than or equal to the preset duration.

8. The driving method of the pixel circuit according to claim 7, wherein: The preset duration satisfies that: the flickering degree caused by the interval duration of adjacent first conduction levels in the first scanning signal is a flickering degree that cannot be recognized by human eyes.

9. The driving method of the pixel circuit according to claim 8, wherein: n includes 2 and positive integer multiples of 2, and the preset duration includes 0.25 times the total duration of the written frame.

10. The driving method of the pixel circuit according to claim 7, wherein: The preset low frequency includes 60 Hz, the target low frequency includes 24 Hz, and the light emitting control signal includes the four level groups located in the writing frame and the six level groups located in the holding frame; In the display period corresponding to the target low frequency: The first scanning signal includes a first on-level located in the write frame and a first on-level located in the hold frame, the first on-level located in the write frame overlaps with the timing of the off-level in the first level group located in the write frame, and the first on-level located in the hold frame overlaps with the timing of the off-level in the second level group located in the hold frame.

11. The driving method of the pixel circuit according to claim 7, wherein: The preset low frequency includes 60 Hz, the target low frequency includes 17 Hz, and the light emitting control signal includes the 4 level groups located in the writing frame and the 10 level groups located in the holding frame; In the display period corresponding to the target low frequency: The first scanning signal includes one first conduction level located in the write frame and two first conduction levels located in the hold frame. The first conduction level located in the write frame overlaps with the timing of the off level in the first level group located in the write frame, the first first conduction level located in the hold frame overlaps with the timing of the off level in the first level group located in the hold frame, and the second first conduction level located in the hold frame overlaps with the timing of the off level in the sixth level group located in the hold frame.

12. A pixel circuit, characterized in that: include: A driving module, configured to drive the light emitting element during a display period, wherein the display period includes a writing frame and a holding frame; a voltage writing module connected to the first terminal of the driving module, wherein the working phase of the voltage writing module includes at least one first phase and at least one second phase, the first phase is in the writing frame, and the second phase is in the holding frame, the voltage writing module is configured to transmit a reset voltage to the first terminal or the control terminal of the driving module in the first phase, and transmit the reset voltage to the first terminal of the driving module in the second phase; The interval between at least one of the second stages and its adjacent first stage or second stage is a first interval, and the interval between any one of the second stages and its adjacent first stage or second stage is a second interval. In at least part of the display period: the first interval is different from the total interval of the written frame, and the second interval is the same as or tends to be the same as the total interval of the written frame; when the first interval and the second interval are not the same interval, the first interval is the same as or tends to be the same as the second interval. At least part of the display period includes the display period having a target low frequency refresh rate; The refresh rate corresponding to the display period includes a preset low frequency, the target low frequency is a refresh rate lower than the preset low frequency, and in the display period corresponding to the target low frequency, the total duration of the maintained frame is a non-integer multiple of the total duration of the written frame.

13. The pixel circuit according to claim 12, wherein: The first phase includes a data writing phase, the second phase includes a bias phase, and the reset voltage includes a data voltage and a bias voltage; The control end of the voltage writing module receives the first scanning signal, the first end of the voltage writing module is connected to the reset voltage end, the reset voltage end receives the data voltage during the data writing phase, the reset voltage end receives the bias voltage during the bias phase, and the second end of the voltage writing module is connected to the first end of the driving module; The voltage writing module is configured to respond to the first scanning signal and be turned on during the data writing phase to transmit the data voltage to the control end of the driving module, and to respond to the first scanning signal and be turned on during the bias phase to transmit the bias voltage to the first end of the driving module.

14. The pixel circuit according to claim 12, wherein: The first phase includes a first bias phase, the second phase includes a second bias phase, and the reset voltage includes a bias voltage; The control end of the voltage writing module is connected to the first scanning signal, the first end of the voltage writing module is connected to the bias voltage, and the second end of the voltage writing module is connected to the first end of the driving module; The voltage writing module is configured to be turned on in the first bias phase and the second bias phase in response to the first scanning signal, so as to transmit the bias voltage to the first end of the driving module in the first bias phase and the second bias phase respectively.

15. A display panel, characterized in that: The pixel circuit comprises any one of claims 12 to 14.

16. A display device, characterized in that: Includes the display panel according to claim 15.

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