Semiconductor device and erase method

Abstract

A semiconductor device and an erase method capable of slowing down deterioration of a memory cell caused by ISPE are provided. A NAND-type flash memory of the present invention includes a memory cell array, and an erase means that erases a selected block of the memory cell array. The erase means performs a first erase verification (EV1) and a second erase verification (EV2) on the selected block, applies an erase pulse of the same erase voltage as the last time in a case where the first erase verification (EV1) is passed and the second erase verification (EV2) is not passed, and applies an erase pulse of a higher step voltage than the last time in a case where the first erase verification (EV1) is not passed.

Description

Technical Field

[0001] This invention relates to a NAND flash memory, particularly to the control of erase pulses during the erasure of memory cells, and more particularly to a semiconductor device and erasure method. Background Technology

[0002] In NAND flash memory, incremental step pulse erase (ISPE) is used to control the threshold distribution of memory cells during erasure. For example... Figure 1 As shown, ISPE applies an erase pulse Vers0 to the P-well of the selected block. If the erase test fails, an erase pulse Vers1, which has a higher voltage step than Vers0, is applied. Erasure is performed by increasing the voltage of the erase pulses until the erasure of all memory cells within the block is deemed successful. Furthermore, if the number of erase pulses applied reaches the maximum allowed number, the block is treated as a bad block, and the erasure process ends. Summary of the Invention

[0003] In NAND flash memory, repeated programming / erasing cycles degrade the transconductance (Gm), making it difficult for current to flow to the memory cells, and causing the threshold of the memory cells to gradually shift in the positive direction. Since erasing a memory cell reduces the threshold in the negative direction, as the number of cycles increases, erasing becomes more difficult and the erasing speed slows down.

[0004] In previous ISPE (Intense Specialized Erasure) tests, memory cells deteriorated due to repeated programming / erasing, and the erasure speed slowed down. Increasing the erase pulse voltage could shorten the erasure time, but this also contributed to cell degradation. Since block-by-block erase verification is performed on a block-by-block basis, if a block contains both fully erased and partially erased NAND strings, the erase verification fails, and an erase pulse with a higher step voltage is applied to the selected block. Therefore, for memory cells with fully erased NAND strings, excessive voltage stress is applied, accelerating cell degradation. Consequently, durability characteristics also deteriorate.

[0005] The purpose of this invention is to solve this existing phenomenon and provide a semiconductor device and erasure method that can mitigate the degradation rate of memory cells caused by ISPE.

[0006] The erasure method of the NAND flash memory of the present invention includes: applying an erasure pulse to a selected block of a memory cell array; performing a first erasure verification on the selected block with a first read voltage; performing a second erasure verification on the selected block with a second read voltage lower than the first read voltage; and controlling the next erasure pulse to be applied based on the first erasure verification and the second erasure verification, wherein the control step includes applying an erasure pulse with the same erasure voltage as the previous one.

[0007] In one embodiment, the control step includes applying an erase pulse with the same erase voltage as the previous one between a threshold defined by a first erase verification and a second erase verification. In one embodiment, the control step applies an erase pulse with the same erase voltage as the previous one if the first erase verification is successful and the second erase verification is unsuccessful; and applies an erase pulse with a higher step voltage than the previous one if the first erase verification is unsuccessful. In one embodiment, the control step is configured such that if the number of erase pulses with the same erase voltage as the previous one applied reaches a predetermined number Q, the erase voltage of the erase pulse applied to the selected block during the next erase after programming is increased by a step voltage. In one embodiment, the control step sets the predetermined number Q such that the threshold offset when an erase pulse with the predetermined number Q is applied is equal to the threshold offset when an erase pulse with a higher step voltage is applied. In one embodiment, when the allowed erasure time is set to Tmax and the application time of the next erasure pulse is set to Tp, the allowed number of erasure pulse applications Nmax is Nmax = Tmax / Tp, and the control step sets a predetermined number Q based on the allowed number of applications Nmax. In one embodiment, the application step includes applying an initial erasure pulse to form a state in which the threshold of the memory cell shifts in the negative direction at a slow speed and approximately linearly, and the control step controls the next erasure pulse after the initial erasure pulse is applied.

[0008] The semiconductor device of the present invention includes: a NAND-type memory cell array; and an erasure member for erasing selected blocks of the memory cell array, wherein the erasure member performs a first erasure verification on the selected blocks with a first readout voltage and a second erasure verification with a second readout voltage lower than the first readout voltage, and controls the next erasure pulse to be applied based on the first erasure verification and the second erasure verification, and applies an erasure pulse with the same erasure voltage as the previous one between a threshold defined by the first erasure verification and the second erasure verification.

[0009] In one embodiment, if the first erase verification passes and the second erase verification fails, the eraser applies an erase pulse with the same erase voltage as the previous one; if the first erase verification fails, it applies an erase pulse with a higher step voltage than the previous one. In one embodiment, the eraser is configured such that if the number of erase pulses with the same erase voltage as the previous one reaches a predetermined number Q, the erase voltage of the erase pulse applied to the selected block during the next erase after programming is increased by a step voltage. In one embodiment, the eraser sets the predetermined number Q such that the threshold offset when the predetermined number Q of erase pulses is applied is equal to the threshold offset when the higher step voltage erase pulse is applied. In one embodiment, when the allowed erase time is set to Tmax and the application time of the next erase pulse is set to Tp, the allowed number of erase pulse applications Nmax is Nmax = Tmax / Tp, and the eraser sets the predetermined number Q based on the allowed number of applications Nmax. In one embodiment, the erasure member applies an initial erasure pulse to form a state in which the threshold of the memory cell is shifted in the negative direction at a slow speed and approximately linearly, and controls the next erasure pulse after the initial erasure pulse is applied.

[0010] According to the present invention, the next erase pulse to be applied is controlled based on the first erase verification and the second erase verification. Therefore, the erase voltage of the next erase pulse to be applied can be set to the same erase voltage as the previous one, thereby suppressing the acceleration of the degradation rate of the memory cell. Attached Figure Description

[0011] Figure 1 This is a voltage step diagram illustrating the erasure process of flash memory using ISPE in the prior art;

[0012] Figure 2 This is a structural block diagram illustrating a NAND flash memory according to an embodiment of the present invention;

[0013] Figure 3 It is a graph showing the relationship between the threshold of storage units and the erasure time;

[0014] Figure 4 This is a flowchart illustrating the erasure operation of the flash memory according to an embodiment of the present invention;

[0015] Figure 5 (A) is a graph representing the relationship between the threshold distribution and the erasure verification EV1. Figure 5 (B) is a graph showing the relationship between the threshold distribution and the erasure verification EV2;

[0016] Figure 6 This is a table showing the relationship between the erasure pulses and the number of applications of ISPE based on embodiments of the present invention;

[0017] Figure 7 (A) Figure 7 (B) is a diagram illustrating an example of the application of an ISPE-based erasure pulse according to an embodiment of the present invention.

[0018] [Explanation of Symbols]

[0019] 100: Flash Memory

[0020] 110: Memory cell array

[0021] 120: Input / output buffer

[0022] 130: Address Register

[0023] 140: Controller

[0024] 150: Setting up an information storage unit

[0025] 160: Word line selection circuit

[0026] 170: Page buffer / read circuit

[0027] 180: Column Selection Circuit

[0028] 190: Internal voltage generation circuit

[0029] A, A1, A2, B1, B2: Threshold distribution

[0030] Ax: Row address information

[0031] Ay: Column address information

[0032] BLK(m-1), BLK(1), BLK(0): Blocks

[0033] EV1: First Erasure Validation / Erasure Validation

[0034] EV2: Second Erasure Validation / Erase Validation

[0035] P1, P2, P3, P4, P5, P6, P7, P8: Erasure Pulse

[0036] S100, S110, S120, S130, S140, S150, S160, S170: Steps

[0037] Vers0, Vers1, Vers(n): Erasure pulse

[0038] Vers: Erasure voltage

[0039] Vg1, Vg2: Verify the readout voltage

[0040] Vpgm: Programming Voltage

[0041] Vpass: Through voltage

[0042] Vread: Readout voltage Detailed Implementation

[0043] Figure 2 This is a block diagram illustrating the structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 structure of this embodiment includes: a memory cell array 110, which arranges multiple memory cells in a matrix; an input / output buffer 120, which outputs read data to the outside or imports data input from the outside; an address register 130, which holds address data input via the input / output buffer 120; a controller 140, which controls each part based on command data received via the input / output buffer 120 or control signals applied to external terminals; a setting information storage unit 150, which stores setting information such as ISPE; and a word line selection circuit 160, which selects word lines based on the row and ground planes from the address register 130. Address information Ax is used for block selection and word line selection, etc.; page buffer / read circuit 170 holds data read from the page selected by the memory cell array 110, or holds data for programming in the selected page; column selection circuit 180 selects columns in the page buffer / read circuit 170 based on column address information Ay from address register 130, etc.; and internal voltage generation circuit 190 generates various voltages required for reading, programming and erasing (programming voltage Vpgm, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.).

[0044] The memory cell array 110, for example, has m blocks (BLK) arranged along the column direction. Each block includes multiple NAND strings, and a NAND string includes multiple memory cells, bit-line select transistors (BSTs), and source-line select transistors (SSTs) connected in series. The BSTs are connected to a corresponding global bit line, and the SSTs are connected to a common source line. The gate of each memory cell is connected to a word line, and the gates of the BSTs and SSTs are connected to a select gate line. The word line (WL) and the select gate line are driven by a word line select circuit 160. Additionally, each bit line is connected to the page buffer / readout circuit 170 via a bit line select circuit for selecting even or odd bit lines.

[0045] The setting information storage unit 150 stores the initial value of the erase pulse, the step voltage, the maximum number of erase pulses applied, and the specified number Q as setting information about ISPE. In one embodiment, when the power is turned on, the setting information read from the fuse unit of the storage unit array 110 is loaded into the setting information storage unit 150.

[0046] The word line selection circuit 160 drives the memory cell via the word line WL based on the row address Ax. Additionally, it selects blocks and pages by driving bit line-side selection transistors and source line-side selection transistors via the selected gate line. The column selection circuit 180 selects the global bit line according to the column address Ay, for example, selecting the start position for reading data within a page.

[0047] The controller 140 is configured using a microcontroller or state machine, including read-only memory (ROM) / random access memory (RAM), to control the operation of the flash memory 100. During the read operation, a positive voltage is applied to the bit lines, a voltage (e.g., 0V) is applied to the select word lines, and a pass voltage (e.g., 4.5V) is applied to the non-select word lines. The bit line-side select transistor and the source line-side select transistor are turned on, and 0V is applied to the common source line. During the programming operation, a high programming voltage Vpgm (e.g., 15V to 20V) is applied to the select word lines, and an intermediate potential (e.g., 10V) is applied to the non-select word lines. The bit line-side select transistor is turned on, and the source line-side select transistor is turned off, supplying the potential corresponding to the data "0" or "1" to the bit lines.

[0048] During the erase operation, 0V is applied to the select word line within the block, and an erase voltage Vers is applied to the P-well, drawing electrons from the floating gate to the substrate. This erases data block by block. The erase voltage is determined according to the ISPE algorithm.

[0049] Next, the ISPE-based erasure method of this embodiment will be described. In conventional ISPE, if the erasure verification fails, the erasure voltage of the next erasure pulse to be applied is increased by a step. However, this method is overstressing for memory cells with fast erasure speeds and may accelerate the degradation of the memory cells.

[0050] On the other hand, regarding the allowable erasure time, durability characteristics are taken into consideration, and the erasure speed is slowed down when the P / E cycle number is 100K, for example, as a benchmark. In previous ISPE, if the erasure verification failed, the allowable erasure time was not considered, that is, the voltage of the erasure pulse was increased even though the allowable erasure time was still sufficiently long.

[0051] In this embodiment of ISPE, when the erase verification fails, the voltage of the erase pulse is not increased indiscriminately. Instead, the allowable erase time is effectively utilized, and erase pulses with the same erase voltage as the previous one are repeatedly applied. This prevents overstress from being applied to memory cells with fast erase speeds, thereby slowing down the degradation rate of such memory cells.

[0052] Figure 3This is a graph showing the relationship between erase pulses with various erase voltages applied at regular time intervals, the threshold of the memory cell, and the erase time (horizontal axis is logarithmic). Here, the application of erase pulses with erase voltages of 18V, 19V, 20V, and 21V is shown. Figure 3 As shown, when the same erasure voltage is repeatedly applied as an erasure pulse, approximately 5 × 10⁻⁶ ohms are observed from the start of the erasure. -6 At that point, the threshold shifts roughly linearly in the negative direction, erasing approximately 10 from the initial value. -1 At this point, the threshold offset becomes approximately constant due to saturation. When the erase voltage is higher (21V compared to 18V), the negative threshold voltage at saturation is larger.

[0053] according to Figure 3 The period from the start of erasure to a certain time (~5×10 -6 The threshold remains almost unchanged when the same erase voltage is applied (around 100°), but then changes slowly and roughly linearly when the same erase voltage is applied.

[0054] In the ISPE of this embodiment of the invention, the voltage of the erase pulse is determined by utilizing the characteristic that this threshold changes slowly and linearly. For example, in Figure 3 5×10 shown -6 ~1×10 -1 During the erasure period, or within the threshold range corresponding to this erasure period, the first erasure verification EV1 and the second erasure verification EV2 of the selected block are performed to verify whether the threshold of the storage cell is within the range. When the threshold of the storage cell is between the first erasure verification EV1 and the second erasure verification EV2, an erasure pulse with the same erasure voltage is applied to the selected block as much as possible.

[0055] However, since the allowed erasure time is limited, an upper limit needs to be set on the number of erasure pulses applying the same voltage. For example, when the allowed erasure time is set to Tmax and the application time of one erasure pulse is set to Tp (the application time of each erasure pulse is equal), the allowed number of erasure pulses Nmax is Nmax = Tmax / Tp. Based on the allowed number of applications Nmax, the number of erasure pulses that can be applied at the same voltage can be determined.

[0056] Figure 4 This is a flowchart of the ISPE operation according to an embodiment of the present invention. Controller 140 executes the ISPE algorithm (S100) in response to an externally input erase command and address, or in response to an internal erase command for initiating internal garbage collection.

[0057] The controller 140 sets the word line of the block selected via the word line selection circuit 160 to GND level and applies an erase pulse to the P-well (S110). As an initial sequence, it enters the memory cell threshold... Figure 3 The threshold shown is applied in a slow and linear manner over a region, with one or more initial erase pulses.

[0058] Next, the controller 140 performs the erase verification EV1 (S120) of the selected block. The erase verification EV1 applies a verification read voltage Vg1 to each word line of the selected block to verify the erase status of each NAND string in the selected block.

[0059] Figure 5 (A) is a schematic diagram illustrating the relationship between erase verification EV1 and the threshold distribution of memory cells. If, as in threshold distribution A, the threshold of all memory cells (or NAND strings) is less than the verification read voltage Vg1, then erase verification EV1 is successful. On the other hand, if, as in threshold distribution B1, the threshold of some memory cells is greater than the verification read voltage Vg1, then erase verification EV1 is unsuccessful. Furthermore, if, as in threshold distribution B2, the lower limit does not reach the verification read voltage Vg1, then erase verification EV1 is also unsuccessful.

[0060] If the erase verification EV1 fails, the threshold for determining the storage unit to be selected as the block has not yet shifted sufficiently in the negative direction; in other words, it has not been reached. Figure 3 In the region where the threshold changes slowly and linearly, the controller 140 increases the erase voltage of the next erase pulse by a step (S160) and applies this increased erase pulse to the selected block (S110).

[0061] On the other hand, if the erase verification EV1 is successful, a second erase verification EV2 is performed (S130). The erase verification EV2 is performed using a verification readout voltage Vg2 that is smaller than the verification readout voltage Vg1. Figure 5 (B) is a schematic diagram illustrating the relationship between erase verification EV2 and the threshold distribution of memory cells. If the threshold distribution A for erase verification EV1 is as shown in threshold distribution A1, where the threshold of all memory cells is less than the verification read voltage Vg2, then erase verification EV2 is qualified. However, if, as shown in threshold distribution A2, even some thresholds are greater than the verification read voltage Vg2, then erase verification EV2 is unqualified.

[0062] If the erase verification EV2 passes (step S130), the erasure of the selected block ends. If the erase verification EV2 fails, the controller 140 determines the voltage of the next erase pulse. In this case, the controller 140 determines whether the number of times the same erase pulse has been applied has reached a predetermined value Q (S140). If it is below the predetermined value Q, the controller determines that the erase voltage of the next erase pulse is the same as the previous one (S150), and applies an erase pulse with the same erase voltage as the previous one to the selected block (S110). If the predetermined value Q is exceeded, the controller 140 sets a flag in the memory to increase the erase voltage of the erase pulse by one step (S170). When erasing the next programmed block, the controller 140 refers to the flag and applies an erase pulse with an increased erase voltage by one step to the selected block. After the flag is set, the controller 140 determines that the erase voltage of the next erase pulse is the same as the previous one (S150), and applies an erase pulse with the same erase voltage as the previous one to the selected block (S110).

[0063] Repeat steps S110 to S170 until the erase verification EV2 is successful, and repeatedly apply erase pulses with a slow erase speed. When the total number of erase pulses applied reaches the allowed number of applications Nmax, the selected block is managed as a bad block, and the erase ends.

[0064] The erasure method according to this embodiment can effectively utilize the allowed erasure time and repeatedly apply erasure pulses with the same erasure voltage as the previous one. Therefore, it can prevent excessive voltage stress on memory cells with high erasure speeds and slow down the rate of memory cell degradation. As a result, the durability characteristics of flash memory can be improved compared to conventional ISPE.

[0065] Next, specific examples of ISPE in embodiments of the present invention will be described. Figure 6 A table showing an example of the erase voltage and the number of erase pulses applied. Figure 7 (A) is Figure 6 The erasure example of "Step-4" Figure 7 (B) is Figure 6The erasure example in "Step-9" is as follows. As the initial sequence for erasure, a ramp erasure pulse P1, an erasure pulse P2 with a peak value of 14.0V, and an erasure pulse P3 with a peak value of 14.4V are applied. This initial sequence is implemented to shift the threshold of the selected block's memory cell to a region where the threshold changes slowly and linearly. The application time of each erasure pulse is set to 500µs, the verification readout voltage of erasure verification EV1 is set to Vg1 = 1.4V, and the verification readout voltage of erasure verification EV2 is set to Vg2 = 1.0V. Furthermore, it is assumed that the threshold offset × a predetermined value Q when applying a 14.4V erasure pulse is approximately equal to the threshold offset when applying a 14.8V erasure pulse with a higher step voltage, and here, the predetermined value Q for the number of erasure pulses with the same erasure voltage as the previous one is set to 5.

[0066] like Figure 6 As shown in the "Fresh" section, the selected block with a low P / E cycle count is used as the initial sequence for erasure. A ramp erasure pulse P1 (500µs) is applied, followed by erasure pulse P2 (14V, 500µs) and then erasure pulse P3 (14.4V, 500µs). After 1.5ms, erasure verification EV1 and erasure verification EV2 are performed.

[0067] (1) The erasure ends when both the erasure verification EV1 and erasure verification EV2 are qualified.

[0068] (2) If the erase verification EV1 is qualified and the erase verification EV2 is unqualified, apply the erase pulse P4 (14.4V, 500us) as shown in "Step-1".

[0069] (3) After 2.0ms, the erasure ends if the erasure verification EV1 and erasure verification EV2 are both qualified. If the erasure verification EV1 is qualified and the erasure verification EV2 is unqualified, as shown in "Step-2", the erasure pulse P5 (14.4V, 500us) is applied.

[0070] (4) After 2.5ms, the erasure ends if the erasure verification EV1 and erasure verification EV2 are both qualified. If the erasure verification EV1 is qualified but the erasure verification EV2 is unqualified, as shown in "Step-3", the erasure pulse P5 (14.4V, 500us) is applied.

[0071] (5) After 3.0ms, the erasure ends if the erasure verification EV1 and erasure verification EV2 are both qualified. If the erasure verification EV1 is qualified but the erasure verification EV2 is unqualified, as shown in "Step-4", the erasure pulse P6 (14.4V, 500us) is applied.

[0072] (6) In step-4, since the application of erase pulse P6 has reached a predetermined number Q, a flag is set to increase the erase voltage by a step voltage. With this flag set, the erase voltage of the erase pulse for the next erase of the block is set to 14.8V. Therefore, in the erase of the selected block after the next programming, as shown in "Step-5", after the application of the initial erase sequence (erasure pulse P1, erase pulse P2, erase pulse P3), an erase pulse (14.8V, 500µs) is applied.

[0073] Figure 7 Example (A) is as follows: After the initial sequence of erase pulses P1, P2, and P3 is applied, erase verification EV1 passes, but erase verification EV2 fails. Then, erase pulse P4 with the same voltage as erase pulse P3 is applied, and erase verification EV2 also fails continuously. This process is repeated with erase pulses P5, P6, and P7, each with the same voltage as erase pulse P3. Finally, with the application of erase pulse P7, erase verification EV2 passes. Figure 6 (Example of "Step-4" erasure). In this case, since the number of times the 14.4V erasure pulse is applied reaches the specified value Q (=5), a flag is set to increase the erasure voltage of the erasure pulse by a step voltage.

[0074] Figure 7 (B) is an example of erasure where a flag for adding a step voltage was set during the last erasure. Figure 6 In "Step-9", after applying erase pulses P1, P2, and P3 as the initial sequence, an erase pulse P4 (14.8V) with an increased voltage is applied according to the flag set during the last erase. The 2.0ms erase verification EV1 passes, but erase verification EV2 fails. An erase pulse P5 with the same voltage as erase pulse P4 is then applied. Subsequently, erase verification EV2 also fails continuously. The same erase pulses P5, P6, P7, and P8 with the same voltage as erase pulse P4 are repeatedly applied. With the application of erase pulse P8, erase verification EV2 passes. In this case, since the number of times the 14.8V erase pulse is applied reaches the specified value Q (=5), a flag is set to increase the erase voltage of the erase pulse by a step voltage.

[0075] The erase voltage, erase pulse application time, step voltage, and specified value Q described in the above embodiments are just examples. These values ​​can be appropriately changed according to the specifications required by NAND flash memory.

[0076] Although preferred embodiments of the present invention have been described in detail, the present invention is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the spirit of the invention as set forth in the claims.

Claims

1. An erasing method, specifically an erasing method for a NAND flash memory, the erasing method comprising: The step of applying an erase pulse to a selected block of the memory cell array; The step of performing a first erasure verification on the selected block using a first readout voltage; The step of performing a second erase verification on the selected block using a second readout voltage lower than the first readout voltage; and Based on the first erase verification and the second erase verification, the next erase pulse to be applied is controlled. The control steps include applying an erase pulse with the same erase voltage as the previous one. The control steps are configured as follows: if the number of erase pulses with the same erase voltage as the previous one reaches a predetermined number Q, the erase voltage of the erase pulse applied to the selected block during the next erase after programming is increased by a step voltage.

2. The erasure method according to claim 1, wherein, The control steps include applying an erase pulse with the same erase voltage as the previous one between a threshold defined by the first erase verification and the second erase verification.

3. The erasure method according to claim 1 or 2, wherein, The control step applies an erase pulse with the same erase voltage as the previous one if the first erase verification is successful and the second erase verification is unsuccessful; and applies an erase pulse with a higher step voltage than the previous one if the first erase verification is unsuccessful.

4. The erasure method according to claim 1, wherein, The control step sets the predetermined number Q such that the offset of the threshold when an erase pulse of the predetermined number Q is applied is equal to the offset of the threshold when an erase pulse of a higher step voltage is applied.

5. The erasure method according to claim 1, wherein, When the allowed erasure time is set to Tmax and the application time of the next erasure pulse is set to Tp, the allowed number of erasure pulses, Nmax, is Nmax = Tmax / Tp. The control step sets the specified number Q based on the allowed number of applications Nmax.

6. The erasure method according to claim 1 or 2, wherein, The application step includes applying an initial erase pulse to create a state in which the threshold of the memory cell is shifted negatively at a slow and approximately linear rate. The control step controls the next erase pulse after the initial erase pulse is applied.

7. A semiconductor device, comprising: NAND-type memory cell array; as well as Erasure components, erasing selected blocks of the storage cell array. The erasure component performs a first erasure verification on the selected block using a first readout voltage and a second erasure verification using a second readout voltage lower than the first readout voltage. Based on the first and second erasure verifications, it controls the next erasure pulse to be applied, applying an erasure pulse with the same erasure voltage as the previous one between the thresholds defined by the first and second erasure verifications. The erasure component is configured as follows: when the number of erasure pulses with the same erasure voltage as the previous one reaches a predetermined number Q, the erasure voltage of the erasure pulse applied to the selected block during the next erasure after programming is increased by a step voltage.

8. The semiconductor device according to claim 7, wherein, If the first erasure verification is successful and the second erasure verification is unsuccessful, the erasure component applies an erasure pulse with the same erasure voltage as the previous one; if the first erasure verification is unsuccessful, it applies an erasure pulse with a higher step voltage than the previous one.

9. The semiconductor device according to claim 7, wherein, The erasure component sets the predetermined number Q such that the offset of the threshold when an erasure pulse of the predetermined number Q is applied is equal to the offset of the threshold when an erasure pulse of a higher step voltage is applied.

10. The semiconductor device according to claim 7, wherein, When the allowed erasure time is set to Tmax and the application time of the next erasure pulse is set to Tp, the allowed number of erasure pulses, Nmax, is Nmax = Tmax / Tp. The erasure component sets the specified number Q based on the allowed number of applications Nmax.

11. The semiconductor device according to claim 7 or 8, wherein, The erasure component applies an initial erasure pulse to form a state in which the threshold of the memory cell shifts in the negative direction at a slow speed and approximately linearly, and controls the next erasure pulse after the initial erasure pulse is applied.

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