Display device

Abstract

A display device is provided. The display device includes a substrate; and a plurality of thin film transistors disposed on the substrate, wherein each of the plurality of thin film transistors includes an active layer having a channel portion; and a gate separated from the active layer, the substrate includes a first region, a gate of a thin film transistor disposed in the first region includes a first portion at least partially overlapping the channel portion of the active layer; and a second portion, the second portion has a thickness smaller than a thickness of the first portion and at least partially overlaps the channel portion of the active layer, a light transmittance of the second portion is greater than a light transmittance of the first portion.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0176922, filed on December 10, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] One embodiment of the present invention relates to a thin-film transistor and a display device including the thin-film transistor, and more specifically, to a thin-film transistor with a stepped thickness profile at the gate and a display device including the thin-film transistor. Background Technology

[0004] Because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching devices in display devices such as liquid crystal displays or organic light-emitting devices.

[0005] Based on the material constituting the active layer, thin-film transistors can be classified into amorphous silicon thin-film transistors that use amorphous silicon as the active layer, polycrystalline silicon thin-film transistors that use polycrystalline silicon as the active layer, and oxide semiconductor thin-film transistors that use oxide semiconductors as the active layer.

[0006] Among thin-film transistors (TFTs), oxide semiconductor TFTs offer the advantage of readily obtainable desired characteristics due to their high mobility and large resistance variation depending on oxygen content. Furthermore, the manufacturing cost of oxide semiconductor TFTs is reduced because the oxide constituting the active layer is grown at relatively low temperatures during the fabrication process. Given the properties of oxides, their transparency facilitates the realization of transparent display devices.

[0007] The display panels that make up a display device are typically manufactured using a large mother substrate. For example, after multiple display panels are manufactured using a large mother substrate, the mother substrate is cut to form each display panel.

[0008] In the process of manufacturing display panels using large-area mother substrates, large-area deposition equipment can be used to form multiple thin-film transistors (TFTs). When multiple components are manufactured from a large-area mother substrate, process variations can occur for each region. As a result, performance variations can occur in the components formed in each region, such as TFTs. When performance variations occur, TFTs formed in localized areas may exhibit reliability issues, such as significant changes in threshold voltage over time.

[0009] Therefore, when manufacturing display panels using large-sized mother substrates, it is necessary to reduce the performance deviation of thin-film transistors and minimize or avoid the degradation of thin-film transistor reliability. Summary of the Invention

[0010] The present invention was made in view of the above problems. One object of the present invention is to minimize the performance deviation of thin-film transistors when using a large-sized mother substrate to manufacture a display panel.

[0011] Another object of the present invention is to provide a thin-film transistor whose reliability does not deteriorate over time, even when the thin-film transistor is manufactured on a large-size mother substrate.

[0012] Another object of the present invention is to provide a thin-film transistor including a gate having a thickness step profile.

[0013] Another object of the present invention is to provide a display device including the above-described thin-film transistor.

[0014] In addition to the objectives of the invention as described above, those skilled in the art will clearly understand additional objectives and features of the invention from the following description.

[0015] According to one aspect of the present invention, the above and other objectives can be achieved by providing a display device comprising: a substrate; and a plurality of thin-film transistors disposed on the substrate, wherein each of the plurality of thin-film transistors comprises: an active layer having a channel portion; and a gate spaced apart from the active layer, the substrate comprising a first region, the gate of the thin-film transistor disposed in the first region comprising: a first portion at least partially overlapping the channel portion of the active layer; and a second portion having a thickness less than that of the first portion and at least partially overlapping the channel portion of the active layer, the second portion having a light transmittance greater than that of the first portion.

[0016] According to another aspect of the present invention, the above and other objectives can be achieved by providing a thin-film transistor comprising: an active layer having a channel portion; and a gate overlapping the channel portion of the active layer, wherein the gate comprises: a first portion at least partially overlapping the channel portion; and a second portion having a thickness less than that of the first portion and at least partially overlapping the channel portion, wherein the light transmittance of the second portion is greater than that of the first portion.

[0017] The second part may have a light transmittance of 5% to 70%.

[0018] The first part and the second part may be made of the same material.

[0019] The first part may have a thickness of 100 nm or greater.

[0020] The thickness of the second part may be 5% to 50% of the thickness of the first part.

[0021] The second part may have a thickness of 10 nm to 50 nm.

[0022] Based on the plan view, the area occupied by the second portion in the entire region where the channel portion and the gate overlap can be in the range of 10% to 60%.

[0023] The gate may have an area transmittance (ATC) of 1% to 10%, and the area transmittance (ATC) can be calculated using Equation 1 below:

[0024] Equation 1

[0025] ATC[%] = T x A,

[0026] In Equation 1, T is the light transmittance of the second part and is expressed as a percentage. The light transmittance of the second part is the average light transmittance measured in the range of 360 nm to 740 nm. A is the area ratio of the second part calculated by Equation 2 below:

[0027] Equation 2

[0028] A = Area of ​​the second portion overlapping with the channel portion / Area of ​​the gate portion overlapping with the channel portion.

[0029] The second part may have a circular, elliptical, semi-circular, semi-elliptical, or polygonal plane in the plan view.

[0030] The first portion may be located on one side of the gate, and the second portion may be located on the other side of the gate.

[0031] The first part can be configured to surround the second part.

[0032] The gate may include at least one of molybdenum (Mo) and titanium (Ti).

[0033] The active layer may include at least one of the following: IGZO (InGaZnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, FIZO (FeInZnO) based oxide semiconductor material, ZnO based oxide semiconductor material, SIZO (SiInZnO) based oxide semiconductor material, and ZnON (Zn oxynitride) based oxide semiconductor material.

[0034] The active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0035] The active layer may further include a third oxide semiconductor layer on the second oxide semiconductor layer.

[0036] According to another aspect of the present invention, the above and other objectives can be achieved by providing a mother panel comprising: a mother substrate having one or more display panel regions; and a plurality of thin-film transistors disposed on the mother substrate, wherein the mother substrate has a first region and a second region separated from each other, each of the plurality of thin-film transistors including an active layer and a gate, the active layer including a channel portion, the gate of the thin-film transistor disposed in the first region including: a first portion at least partially overlapping the channel portion of the active layer; and a second portion having a thickness less than that of the first portion and at least partially overlapping the channel portion of the active layer, the second portion having a light transmittance greater than that of the first portion.

[0037] The gate of the thin-film transistor disposed in the second region may have the same height as the first portion without having a stepped thickness profile.

[0038] The mother substrate may have a third region that is distinct from the first region and the second region. The gate of the thin-film transistor disposed in the third region may include: a first portion that at least partially overlaps with the channel portion of the active layer; and a second portion that has a thickness less than the first portion and at least partially overlaps with the channel portion of the active layer. The second portion of the gate included in the thin-film transistor disposed in the third region may have a smaller area or a larger thickness than the second portion of the gate included in the thin-film transistor disposed in the first region.

[0039] According to another aspect of the invention, the above and other objectives can be achieved by providing a display device comprising a plurality of pixels having pixel driving circuitry, wherein the pixel driving circuitry comprises the aforementioned thin-film transistors.

[0040] The display device may further include a gate driver disposed on a substrate, the gate driver including a plurality of thin-film transistors, wherein each of the plurality of thin-film transistors of the gate driver may include an active layer and a gate, and the gate of the thin-film transistor disposed in the gate driver may have the same thickness as a first portion of the gate of the thin-film transistor disposed in the pixel driving circuit without having a stepped thickness profile.

[0041] The substrate may further include a second region separate from the first region, wherein the gate of the thin-film transistor disposed in the second region may have the same height as the first region without having a thickness difference.

[0042] The substrate may further include a third region separate from the first region and the second region. The gate of the thin-film transistor disposed in the third region may include: a first portion that at least partially overlaps with the channel portion of the active layer; and a second portion that has a thickness less than the first portion and at least partially overlaps with the channel portion of the active layer. The second portion of the gate in the thin-film transistor disposed in the third region may have a smaller area or a larger thickness than the second portion of the gate in the thin-film transistor disposed in the first region. Attached Figure Description

[0043] The above and other objects, features, and advantages of the invention will become more clearly understood from the following detailed description given with reference to the accompanying drawings. In the drawings:

[0044] Figure 1A This is a plan view illustrating a thin-film transistor according to an embodiment of the present invention;

[0045] Figure 1B It is along Figure 1A A sectional view taken by line I-I';

[0046] Figure 2 This is a plan view illustrating a thin-film transistor according to another embodiment of the present invention;

[0047] Figure 3 This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0048] Figure 4A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0049] Figure 4BIt is along Figure 4A A sectional view taken from line II-II';

[0050] Figure 5 This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0051] Figure 6 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0052] Figure 7 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0053] Figure 8 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0054] Figure 9 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0055] Figure 10 It is a graph illustrating the light transmittance of metals and alloys based on thickness and wavelength;

[0056] Figure 11 This is a plan view illustrating the mother panel according to another embodiment of the present invention;

[0057] Figure 12A These are the PBTS measurement results for thin-film transistors;

[0058] Figure 12B This is a cross-sectional view of a thin-film transistor based on a reference example;

[0059] Figure 13 This is a schematic diagram illustrating a display device according to yet another embodiment of the present invention;

[0060] Figure 14 It is a diagram Figure 13 The circuit diagram of any pixel;

[0061] Figure 15 It is a diagram Figure 14 A planar image of pixels;

[0062] Figure 16 It is along Figure 15 A sectional view taken from line III-III';

[0063] Figure 17 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0064] Figure 18 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0065] Figure 19 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0066] Figure 20 This is a schematic diagram illustrating a display device according to another embodiment of the present invention. Detailed Implementation

[0067] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art.

[0068] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings to describe various embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0069] Where the terms “including,” “having,” and “contains” are used in the description in this application, other parts may be added unless “only” is used.

[0070] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0071] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0072] This document may use spatially relative terms such as “below,” “lower,” “below,” “above,” and “upper” to readily describe the relationship of one or more elements shown in the figures to other elements. It will be understood that these terms are intended to cover different orientations of the device beyond those depicted in the figures. For example, if the device shown in the figures is reversed, a device described as being “below” or “lower” to other devices may be arranged to be “above” to other devices. Thus, the exemplary term “below or lower” may include both “below or lower” and “upper” orientations. Similarly, the exemplary term “upper” or “above” may include both “above” and “below or lower” orientations.

[0073] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0074] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0075] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second and third items" means a combination of all items selected from the first, second and third items, as well as the first, second or third item.

[0076] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The various embodiments of the present invention can be implemented independently of each other, or implemented jointly in a mutually dependent relationship.

[0077] In the accompanying drawings, even when depicted in different figures, the same or similar elements are referred to by the same reference numerals.

[0078] In embodiments of the present invention, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. The source can be the drain, and the drain can be the source. Furthermore, the source in any embodiment of the present invention can be the drain in another embodiment of the present invention, and the drain in any embodiment of the present invention can be the source in another embodiment of the present invention.

[0079] For ease of description, in some embodiments of the present invention, the source region is separated from the source, and the drain region is separated from the drain. However, the embodiments of the present invention are not limited to this structure. For example, the source region can be the source, and the drain region can be the drain. Furthermore, the source region can be the drain, and the drain region can be the source.

[0080] Figure 1A This is a plan view illustrating a thin-film transistor according to an embodiment of the present invention; Figure 1B It is along Figure 1A A sectional view taken by line I-I'.

[0081] A thin-film transistor 100 according to one embodiment of the present invention includes an active layer 130 and a gate 150 at least partially overlapping the active layer 130. (See also...) Figure 1B The gate 150 has a stepped thickness profile.

[0082] Reference Figure 1B A thin-film transistor 100 according to one embodiment of the present invention is disposed on a substrate 110.

[0083] Glass or plastic can be used as substrate 110. Transparent plastics with flexible properties, such as polyimide, can be used as plastic. When polyimide is used as substrate 110, heat-resistant polyimide that can withstand high temperatures can be used, taking into account the high-temperature deposition process performed on substrate 110.

[0084] A buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The buffer layer 120 can protect the active layer 130 by blocking oxygen (O2) or moisture (H2O) from permeating from the substrate 110. In addition, the upper surface of the substrate 110 may be homogenized by the buffer layer 120.

[0085] Reference Figure 1B The active layer 130 is disposed on the buffer layer 120.

[0086] The active layer 130 includes a semiconductor material. According to one embodiment of the present invention, the active layer 130 may include an oxide semiconductor material.

[0087] According to one embodiment of the present invention, the active layer 130 includes a channel portion 130n, a first connecting portion 130a, and a second connecting portion 130b. The first connecting portion 130a contacts one side of the channel portion 130n, and the second connecting portion 130b contacts the other side of the channel portion 130n.

[0088] The first connection portion 130a and the second connection portion 130b can be formed by selectively conductiveizing the active layer 130. Providing conductivity to a selected portion of the active layer 130 refers to selective conductiveizing. Selective conductiveizing can be performed by doping, plasma treatment, etc. The first connection portion 130a and the second connection portion 130b are referred to as conductive portions. According to one embodiment of the present invention, the first connection portion 130a of the active layer 130 can be a source region and the second connection portion 130b can be a drain region, but one embodiment of the present invention is not limited thereto, and the first connection portion 130a can be a drain region and the second connection portion 130b can be a source region.

[0089] According to one embodiment of the present invention, the active layer 130 may include at least one of IGZO (InGaZnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, FIZO (FeInZnO) based oxide semiconductor material, ZnO based oxide semiconductor material, SIZO (SiInZnO) based oxide semiconductor material, and ZnON (Zn oxynitride) based oxide semiconductor material. However, one embodiment of the present invention is not limited to this, and the active layer 130 may be formed by other oxide semiconductor materials known in the art.

[0090] although Figure 1B The active layer 130 is shown to be formed of a single layer, but one embodiment of the invention is not limited thereto. The active layer 130 may have a single-layer structure or may have a multi-layer structure.

[0091] A gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 protects the channel portion 130n.

[0092] The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0093] Reference Figure 1B The gate insulating layer 140 may have a patterned structure. In the process of patterning the gate insulating layer 140, the active layer 130 may be selectively conductive, thereby forming the first connection portion 130a and the second connection portion 130b, but one embodiment of the invention is not limited thereto. The gate insulating layer 140 may be disposed on the entire surface of the substrate 110 without being patterned (see...). Figure 7 ).

[0094] The gate 150 is disposed on the gate insulating layer 140. The gate 150 overlaps with the channel portion 130n of the active layer 130.

[0095] The gate 150 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate 150 may have a multilayer structure comprising at least two conductive layers with different physical properties from each other.

[0096] More specifically, the gate 150 may include at least one of molybdenum (Mo) and titanium (Ti).

[0097] According to one embodiment of the present invention, the gate insulating layer 140 can be patterned by performing an etching process using the gate 150 as a mask. In this process, the active layer 130 can be selectively conductive to form a first connection portion 130a and a second connection portion 130b. More specifically, according to one embodiment of the present invention, the regions of the active layer 130 overlapping with the gate 150 are not conductive, thereby becoming a channel portion 130n with semiconductor characteristics; the regions of the active layer not overlapping with the gate 150 are conductive, thereby becoming the first connection portion 130a and the second connection portion 130b.

[0098] According to one embodiment of the present invention, the gate 150 includes a first portion 151 and a second portion 152. (See also...) Figure 1A and 1B The first portion 151 at least partially overlaps with the channel portion 130n. The second portion 152 has a thickness less than that of the first portion 151 and at least partially overlaps with the channel portion 130n.

[0099] Due to the thickness difference between the first portion 151 and the second portion 152, the gate 150 may have a stepped thickness profile. In one embodiment of the invention, a stepped thickness profile of the gate 150 means that a gate 150 includes portions with different thicknesses, rather than having the same thickness.

[0100] Reference Figure 1A The first portion 151 may be disposed on one side of the gate 150, and the second portion 152 may be disposed on the other side of the gate 150, but one embodiment of the present invention is not limited thereto. The arrangement of the first portion 151 and the second portion 152 may vary as needed.

[0101] Reference Figure 1A The second part 152 may have a rectangular plane, but one embodiment of the invention is not limited thereto, and the second part 152 may have various planar shapes. For example, the second part 152 may have a circular, elliptical, semi-circular, semi-elliptical or polygonal plane, or may have an irregular planar shape.

[0102] According to one embodiment of the invention, the light transmittance of the second portion 152 is greater than that of the first portion 151. According to one embodiment of the invention, light transmittance refers to the average light transmittance in the range of 360 nm to 740 nm. Light transmittance can be measured by a spectrophotometer using known methods. For example, a KONICA MINOLTA product can be used as a spectrophotometer.

[0103] According to one embodiment of the invention, the first portion 151 has no light-transmitting properties, or essentially no light-transmitting properties, while only the second portion 152 may have light-transmitting properties. More specifically, the first portion 151 of the gate 150 may be manufactured in the same manner as conventionally known gates to prevent light from passing through it, while the second portion 152 may be manufactured to allow light to pass through it.

[0104] When the second portion 152 has light-transmitting properties, light can be transmitted through the second portion 152 so that the light can selectively irradiate the channel portion 130n. When the light selectively irradiates the channel portion 130n, the electron trap generated at the interface between the channel portion 130n and the gate insulating layer 140 can be resolved, that is, the electron trap can be alleviated.

[0105] When the active layer 130 is formed of an oxide semiconductor, an electron trap can be generated at the interface between the channel portion 130n of the active layer 130 and the gate insulating layer 140. When an electron trap is generated, the mobility of the thin-film transistor 100 may deteriorate, and the threshold voltage of the thin-film transistor 100 may be changed due to the electron trap.

[0106] Furthermore, the electron trap can become non-uniform over time. In this case, the threshold voltage of the thin-film transistor 100 can become unstable. As a result, the stability of the thin-film transistor 100 can deteriorate, so it is necessary to address the electron trap issue to improve the reliability of the thin-film transistor 100.

[0107] According to one embodiment of the present invention, light can be transmitted through the second portion 152 of the gate 150, and the electron trap of the active layer can be resolved by the transmitted light.

[0108] For example, when the thin-film transistor 100 according to one embodiment of the present invention is used in a display device, light emitted from the display device can be irradiated onto the channel portion 130n through the second portion 152 passing through the gate 150. When light irradiates the channel portion 130n, the electron trap generated at the interface between the channel portion 130n and the gate insulating layer 140 can be resolved. When the electron trap in the channel portion 130n is resolved, the instability of the threshold voltage of the thin-film transistor 100 can be eliminated.

[0109] To address the electron trap issue through light transmission, according to one embodiment of the invention, the second portion 152 may have a light transmittance of 5% to 70%. More specifically, the second portion 152 may have an average light transmittance of 5% to 70% in the range of 360 nm to 740 nm. The light transmittance can be measured using a spectrophotometer, such as a spectrophotometer from KONICA MINOLTA.

[0110] When the light transmittance of the second portion 152 is less than 5%, the electron trap elimination effect generated by light transmission may not be sufficiently demonstrated. When the light transmittance of the second portion 152 exceeds 70%, the intensity of light passing through the second portion 152 may be greater than the required intensity, thereby damaging the channel portion 130n. Furthermore, the thickness of the second portion 152 may be too thin to achieve a light transmittance exceeding 70%, thereby degrading the film stability of the second portion 152. According to one embodiment of the invention, the second portion 152 may have a light transmittance of 10% to 50%, and may have a light transmittance of 20% to 50%.

[0111] The thickness of the first portion 151 and the thickness of the second portion 152 may vary depending on the material constituting the gate 150. According to one embodiment of the invention, the first portion 151 and the second portion 152 may be made of the same material, such as a metal or a metal alloy.

[0112] According to one embodiment of the invention, to avoid light transmission through the first portion 151, the first portion 151 may have a thickness of 100 nm or greater. When the first portion 151 is made of metal or a metal alloy and the thickness of the first portion 151 is greater than or equal to 100 nm, light is almost entirely or completely blocked by the first portion 151. When the thickness of the first portion 151 is greater than or equal to 100 nm, the first portion 151 may have a light transmittance close to zero (0).

[0113] According to one embodiment of the present invention, the gate 150 may have a thickness of 500 nm or less. Therefore, according to one embodiment of the present invention, the first portion 151 may have a thickness of 100 nm to 500 nm. More specifically, the first portion 151 may have a thickness of 100 nm to 300 nm. Optionally, the first portion 151 may have a thickness of 150 nm to 500 nm, a thickness of 150 nm to 300 nm, or a thickness of 200 nm to 500 nm.

[0114] The thickness of the second portion 152 can be 5% to 50% of the thickness of the first portion 151 to achieve a predetermined light transmittance. When the thickness of the second portion 152 exceeds 50% of the thickness of the first portion 151, almost no light transmittance occurs through the second portion 152. On the other hand, when the thickness of the second portion 152 is less than 5% of the thickness of the first portion 151, the film stability of the second portion 152 may deteriorate.

[0115] According to one embodiment of the invention, the second portion 152 may have a thickness of 10 nm to 50 nm to have light transmittance. The second portion 152 may be made of metal or a metal alloy, and light can pass through the second portion 152 when the thickness of the second portion 152 is 10 nm to 50 nm. When light passes through the second portion 152, the channel portion 130n may be selectively exposed to light.

[0116] When the thickness of the second portion 152 is less than 10 nm, the intensity of light passing through the second portion 152 may increase beyond the required intensity, the film stability of the gate 150 may deteriorate, and the electric field effect may not be sufficiently induced through the second electrode 150. When the thickness of the second portion 152 exceeds 50 nm, the light transmittance may deteriorate, thereby failing to achieve a light transmission effect. The thickness of the second portion 152 can vary depending on the type of material used as the gate 150 and can be set taking into account the optical properties of the material used as the gate 150.

[0117] According to one embodiment of the present invention, the thickness of the second part 152 may range from 15 nm to 50 nm, from 20 nm to 50 nm, or from 20 nm to 30 nm.

[0118] The area of ​​the second part 152 can vary depending on the light transmittance of the second part 152 and the extent of the electron trap generated in the thin-film transistor 100.

[0119] According to one embodiment of the present invention, based on a plan view, the proportion of the area occupied by the second portion 152 in the entire region where the channel portion 130n and the gate 150 overlap with each other can be in the range of 10% to 60%. Therefore, light transmission can be performed for 10% to 60% of the area of ​​the channel portion 130n.

[0120] Based on the planar diagram, when the area occupied by the second portion 152 in the entire region where the channel portion 130n and the gate 150 overlap is less than 10%, the electron trap elimination effect may not be fully demonstrated through light transmission. Conversely, when the area occupied by the second portion 152 in the entire region where the channel portion 130n and the gate 150 overlap exceeds 60%, the light-illuminated area of ​​the channel portion 130n increases, thereby increasing the number of charge carriers beyond the desired value, and thus the threshold voltage of the thin-film transistor 100 can be shifted in the negative (-) direction. More specifically, the area occupied by the second portion 152 in the entire region where the channel portion 130n and the gate 150 overlap can be in the range of 10% to 50%, or in the range of 15% to 45%.

[0121] The specific area occupied by the second portion 152 can vary depending on the light transmittance of the second portion 152. According to one embodiment of the invention, the area of ​​the second portion 152 can be determined taking into account the light transmittance of the second portion 152.

[0122] According to one embodiment of the invention, the gate 150 has an area transmittance coefficient (ATC) calculated by Equation 1 below. According to one embodiment of the invention, the area transmittance system (ATC) defines the relationship between the area occupied by the second portion 152 overlapping with the channel portion 130n and the light transmittance of the second portion 152.

[0123] Equation 1

[0124] ATC[%] = T x A

[0125] In Equation 1, T is the light transmittance of the second part 152, and is expressed as a percentage (%), with x representing a multiplication sign. In this case, light transmittance refers to the average light transmittance measured in the range of 360 nm to 740 nm.

[0126] In Equation 1, A is the area ratio of the second part 152, and is calculated by Equation 2 below.

[0127] Equation 2

[0128] A = Area of ​​the second portion overlapping with the channel / Area of ​​the gate overlapping with the channel

[0129] In Equation 2, the area of ​​the second portion 152 overlapping with the channel portion 130n corresponds to the area of ​​the channel portion 130n overlapping with the second portion 152. The area of ​​the gate 150 overlapping with the channel portion 130n corresponds to the area of ​​the channel portion 130n.

[0130] For example, when the light transmittance of the second portion 152 is 20% and the ratio of the area of ​​the second portion 152 overlapping with the channel portion 130n to the area of ​​the gate 150 overlapping with the channel portion 130n is 0.2, the area transmittance coefficient (ATC) of the gate 150 is as follows:

[0131] ATC[%]=T x A=20%x0.2=4%

[0132] According to one embodiment of the invention, the gate 150 may have an area transmittance coefficient (ATC) of 1% to 10%.

[0133] When the area transmittance coefficient (ATC) of the gate is less than 1%, the amount of light transmitted through the second portion 152 of the gate 150 decreases, resulting in insufficient electron trap elimination effect through light transmission. On the other hand, when the area transmittance coefficient (ATC) of the gate 150 exceeds 10%, the amount of light transmitted through the second portion 152 of the gate 150 increases, resulting in damage to the channel portion 130n or a shift in the threshold voltage of the thin-film transistor 100 due to excessive light irradiation.

[0134] According to one embodiment of the present invention, the gate 150 may have an area transmittance coefficient (ATC) of 1% to 7%, or an area transmittance coefficient (ATC) of 1% to 5%.

[0135] Reference Figure 1B An interlayer insulating layer 160 may be disposed on the gate 150. The interlayer insulating layer 160 may be made of organic or inorganic insulating materials. The interlayer insulating layer 160 may be formed of a composite layer of organic and inorganic layers.

[0136] According to one embodiment of the present invention, the thin-film transistor 100 may have a first electrode 171 and a second electrode 172 disposed on the interlayer insulating layer 160. The first electrode 171 may be used as a source and the second electrode 172 may be used as a drain, but one embodiment of the present invention is not limited thereto. The first electrode 171 may be used as a drain and the second electrode 172 may be used as a source. In addition, the first connection portion 130a and the second connection portion 130b may be used as a source and a drain, respectively, and the first electrode 171 and the second electrode 172 may be used as connection electrodes between elements.

[0137] Reference Figure 1A and 1B The first electrode 171 and the second electrode 172 can be connected to the active layer 130 via contact holes CH1 and CH2, respectively. Specifically, the first electrode 171 can contact the first connection portion 130a via contact hole CH1. The second electrode 172 can be separated from the first electrode 171 and contact the second connection portion 130b via contact hole CH2.

[0138] Figure 2 This is a plan view illustrating a thin-film transistor 200 according to another embodiment of the present invention. Descriptions of already described elements will be omitted below to avoid repetition.

[0139] Reference Figure 2The second portion 152 of the gate 150 may have a trapezoidal plane. The second portion 152 may be disposed on one side of the gate 150. The second portion 152 may be disposed in the direction of contact between the second connection portion 130b and the second electrode 172 serving as the drain. That is, the longest side of the trapezoidal plane of the second portion may be disposed toward the second connection portion 130b that contacts the second electrode 172.

[0140] However, another embodiment of the present invention is not limited to Figure 2 As shown. For example, the second portion 152 may be disposed in the direction of contact between the first connection portion 130a and the first electrode 171 used as the source. Furthermore, as described above, the second portion 152 may have a circular, elliptical, semi-circular, semi-elliptical, or polygonal plane, or may have various planar shapes other than those shown in the figure.

[0141] Figure 3 This is a plan view illustrating a thin-film transistor 300 according to another embodiment of the present invention.

[0142] Reference Figure 3 The second portion 152 of the gate 150 may be semi-circular. The planar shape of the second portion 152 (the diameter of the semi-circle pointing towards the edge of the gate 150) is as follows: Figure 3 As shown, but another embodiment of the present invention is not limited thereto. The diameter portion of the semicircle may be configured to point towards the center portion of the gate 150.

[0143] Figure 4A This is a plan view illustrating a thin-film transistor 400 according to yet another embodiment of the present invention. Figure 4B It is along Figure 4A The sectional view taken from line II-II'.

[0144] Reference Figure 4A Based on the plan view, the second portion 152 may be located at the center of the gate 150. Specifically, the second portion 152 may overlap with the channel portion 130n, and the first portion 151 may be configured to surround the second portion 152.

[0145] Reference Figure 4B Based on the sectional view, the first part 151, which protrudes more than the second part 152, can be set on both sides of the second part 152.

[0146] Figure 5 This is a plan view illustrating a thin-film transistor 500 according to another embodiment of the present invention.

[0147] Reference Figure 5 The second portion 152 overlaps with the channel portion 130n and may have a circular or elliptical plane. The first portion 151 may be configured to surround the circular or elliptical second portion 152.

[0148] Figure 6 This is a cross-sectional view illustrating a thin-film transistor 600 according to yet another embodiment of the present invention.

[0149] Reference Figure 6 A light-shielding layer 111 may be disposed on the substrate 110. The light-shielding layer 111 may be made of a material with light-shielding properties. The light-shielding layer 111 blocks light incident from the outside to protect the active layer 130.

[0150] Reference Figure 6 The buffer layer 120 can be disposed on the light-shielding layer 111. Although Figure 6 It is not shown in the figure, but the lower buffer layer may be disposed between the substrate 110 and the light-shielding layer 111.

[0151] Reference Figure 6 The light-shielding layer 111 can be connected to the first electrode 171 via contact holes formed in the buffer layer 120 and the interlayer insulating layer 160, but another embodiment of the invention is not limited thereto. The light-shielding layer 111 can be connected to the first electrode 172, or it can be connected to other lines or grounding portions. The light-shielding layer 111 can be in a floating state and is not connected to other lines in any case.

[0152] exist Figure 1A , 1B In the thin-film transistors 100, 200, 300, 400 and 500 shown in 2, 3, 4A, 4B and 5, a light-shielding layer 111 may be disposed on a substrate 110, and a buffer layer 120 may be disposed on the light-shielding layer 111.

[0153] Figure 7 This is a cross-sectional view illustrating a thin-film transistor 700 according to another embodiment of the present invention.

[0154] Figure 7 The thin-film transistor 700 includes an unpatterned gate insulating layer 140. For example... Figure 1B and 6 As shown, the gate insulating layer 140 can be patterned to correspond to the gate 150, but as Figure 7 As shown, the gate insulating layer 140 may be unpatterned.

[0155] When the gate insulating layer 140 is not patterned, the active layer 130 can be selectively conductive by selective ion implantation, selective hydrogen implantation, or selective ultraviolet light irradiation, thereby forming a first connection portion 130a and a second connection portion 130b. Furthermore, contact holes CH1 and CH2 can be formed through the gate insulating layer 140.

[0156] Figure 8 This is a cross-sectional view illustrating a thin-film transistor 800 according to yet another embodiment of the present invention.

[0157] According to another embodiment of the present invention, the active layer 130 of the thin-film transistor 800 may have a multilayer structure. (See also...) Figure 8 The active layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131.

[0158] The first oxide semiconductor layer 131 can support the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 can be referred to as a "support layer". The channel portion 130n can be mainly formed in the second oxide semiconductor layer 132. Therefore, the second oxide semiconductor layer 132 can be referred to as a "channel layer", but one embodiment of the present invention is not limited thereto, and the channel portion 130n can also be formed on the first oxide semiconductor layer 131.

[0159] The structure of the active layer 130, which includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132, is called a bi-layer structure.

[0160] Figure 9 This is a cross-sectional view illustrating a thin-film transistor 900 according to another embodiment of the present invention.

[0161] exist Figure 9 In the thin-film transistor 900, compared to Figure 8 The thin-film transistor 800 has an active layer 130 that further includes a third oxide semiconductor layer 133 on the second oxide semiconductor layer 132.

[0162] Reference Figure 9 The active layer 130 includes a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 133. However, another embodiment of the invention is not limited to this, and the active layer may further include other semiconductor layers. Utilizing three oxide semiconductor layers, the intermediate layer is protected from damage in two directions during manufacturing. For example, the bottom oxide semiconductor layer protects the intermediate semiconductor layer from the influence of gases during manufacturing, and the top oxide semiconductor layer protects the intermediate semiconductor layer from the influence of etchants or gases during manufacturing.

[0163] Figure 10 It is a graph illustrating the light transmittance of metals and alloys based on thickness and wavelength.

[0164] exist Figure 10 In the diagram, LT1 represents the light transmittance based on the wavelength of a molybdenum-titanium alloy (MoTi) with a thickness of 60 nm, LT2 represents the light transmittance based on the wavelength of molybdenum (Mo) with a thickness of 30 nm, and LT3 represents the light transmittance based on the wavelength of a molybdenum-titanium alloy (MoTi) with a thickness of 30 nm.

[0165] Reference Figure 10 It should be noted that light transmittance varies depending on the type of metal, the type of alloy, and the thickness of the metal or alloy.

[0166] According to one embodiment of the invention, the thickness of the second portion 152 of the gate 150 may be determined based on the type of metal or alloy and the degree of degradation of the thin-film transistor due to electron trap.

[0167] Figure 11 This is a plan view illustrating a mother panel 1000 according to another embodiment of the present invention.

[0168] According to one embodiment of the present invention, a panel having multiple display panels is referred to as a mother panel. The display panels constituting a display device are typically manufactured on a larger mother substrate. A mother panel can be formed when multiple display panels are manufactured on a larger mother substrate. The mother panel is cut to form each display panel.

[0169] In the process of manufacturing display panels using large-sized mother substrates, multiple thin-film transistors are formed on the mother substrate. To form a large number of thin-film transistors on a large-sized mother substrate, large-sized deposition equipment is used, and processes such as exposure and etching are performed over a large area. As a result, process variations can occur for each area of ​​the mother substrate. Due to this process variation, the degree of electron trapping can differ for each thin-film transistor.

[0170] Figure 11 The diagram illustrates an implementation of a mother panel 1000 comprising six display panels: panel 1, panel 2, panel 3, panel 4, panel 5, and panel 6. Figure 11 In the diagram, the region represented by ① refers to the first region with lower component reliability, the region represented by ② refers to the second region with higher component reliability, and the region represented by ③ refers to the third region with intermediate component reliability.

[0171] According to another embodiment of the invention, the level of reliability can be determined based on the density of electron traps generated in the thin-film transistor. Regions with high-density electron traps can be classified as a first region (region ①) with low reliability, regions with low-density electron traps can be classified as a second region (region ②) with high reliability, and regions with intermediate-level electron trap densities can be classified as a third region (region ③) with intermediate-level reliability.

[0172] Because of the electron trap problem in the thin-film transistor that occurs in the first region (region ①) with low reliability, a second portion 152 can be formed in the gate 150. As the electron trap becomes more severe, the area of ​​the second portion 152 can be increased or the second portion 152 can be formed thinner.

[0173] In the second region (region ②) with high reliability, since the electron trap in the thin-film transistor is not a major problem, the second part 152 does not need to be formed in the gate 150.

[0174] In the third region (region ③), which has an intermediate level of reliability, the electron trap problem occurs in the thin-film transistor, but the degree of electron trap is not severe. Therefore, the second portion 152 can be formed in the gate 150 with a smaller area, or the second portion 152 can be formed with a thicker thickness.

[0175] Figure 12A These are the PBTS measurement results for thin-film transistors. Figure 12B This is a cross-sectional view of a thin-film transistor based on a reference example.

[0176] Specifically, Figure 12A It is set in Figure 11 The PBTS measurement results of the thin-film transistors in the first region (region ①) of the mother panel 1000 are shown. Figure 12A Embodiment 1 shows the PBTS measurement results of a thin-film transistor 100 having the structure of FIG1. ​​In the curve shown in Embodiment 1, light is transmitted through the second portion 152 of the gate 150, thereby measuring the PBTS under the condition that light illuminates a portion of the channel portion 130n.

[0177] Figure 12A The reference examples in the text represent PBTS measurement results of thin-film transistors based on the reference examples. For example... Figure 12B As shown, the thin-film transistor according to the reference example has a structure similar to that of FIG. 1, but does not include the second portion 152 of the gate 150. The thickness of the gate 150 is equal to the thickness of the first portion 151 of FIG. 1.

[0178] PBTS (Positive Bias Temperature Stress) refers to the stress under conditions of applying a positive (+) bias voltage and constant temperature.

[0179] According to one embodiment of the present invention, the PBTS of a thin-film transistor can be estimated by measuring the change in the threshold voltage ΔVth of the thin-film transistor under conditions of applied positive (+) bias voltage and constant temperature. The PBTS of the thin-film transistor can be expressed as the change in the threshold voltage ΔVth of the thin-film transistor under PBTS conditions.

[0180] Figure 12AIt is a graph illustrating the change in the threshold voltage of the thin-film transistor over time (seconds, sec) under a state in which a temperature stress of 60°C and a positive (+) bias voltage are applied to the thin-film transistor formed in the first region (region ①) of the mother panel 1000 according to Embodiment 1 and the reference example.

[0181] In the thin-film transistor according to Embodiment 1, light is transmitted through the second portion 152 of the gate 150, thereby illuminating a portion of the channel portion 130n. On the other hand, in the thin-film transistor according to the reference example, no external light illuminates the channel portion 130n.

[0182] Reference Figure 12A In the thin-film transistor according to embodiment 1, which includes a gate 150 having a second portion 152, it is noted that even if the thin-film transistor is formed in a first region (region ①) with low reliability in the area of ​​the mother panel 1000, the threshold voltage Vth does not change significantly over time.

[0183] On the other hand, in the thin-film transistor according to the reference example, it is noted that the threshold voltage Vth changes over time. (Reference) Figure 12A When a thin-film transistor is formed in a first region (region ①) with low reliability, the threshold voltage Vth of the thin-film transistor changes over time, thereby degrading the reliability of the thin-film transistor.

[0184] On the other hand, it is noted that the thin-film transistor according to one embodiment of the present invention exhibits excellent driving stability under PBTS conditions, even when formed in a first region (region ①) with low reliability.

[0185] In a thin-film transistor including an active layer 130 made of oxide semiconductor, when an electron trap appears at the interface between the channel portion 130n of the active layer 130 and the gate insulating layer 140, the mobility of the thin-film transistor 100 may deteriorate, thereby changing the threshold voltage. For example... Figure 12A As shown in the reference example, when the threshold voltage changes, the evaluation shows that the reliability of the thin-film transistor is poor.

[0186] In the thin-film transistor according to Embodiment 1, light is transmitted through the second portion 152 of the gate 150, and the transmitted light can resolve the electron trap. As a result, the thin-film transistor according to Embodiment 1 maintains a nearly constant threshold voltage Vth even after prolonged use under the worst stress conditions. Figure 12A As shown.

[0187] Another embodiment of the present invention provides a mother panel 1000, which can be divided into multiple display panels by cutting.

[0188] The mother panel 1000 according to another embodiment of the present invention may include, according to Figure 1A , 1B At least one of the following thin-film transistors: 100, 200, 300, 400, 500, 600, 700, 800, and 900: 2, 3, 4A, 4B, 5, 6, 7, 8, and 9.

[0189] Specifically, the mother panel 1000 may include a mother substrate having one or more display panels, such as panel 1, panel 2, panel 3, panel 4, panel 5 and panel 6, and a plurality of thin film transistors 100, 200, 300, 400, 500, 600, 700, 800 and 900 disposed on the mother substrate.

[0190] The mother substrate includes a first region (region ①) and a second region (region ②) that are distinct from each other. The first region of the mother substrate corresponds to the region with low component reliability (region ①), and the second region corresponds to the region with high component reliability (region ②). The first region (region ①) of the mother substrate corresponds to the first region of the mother panel 1000, and the second region (region ②) of the mother substrate corresponds to the second region of the mother panel 1000.

[0191] Each of the plurality of thin-film transistors disposed on the mother substrate includes an active layer 130 and a gate 150. The active layer 130 includes a channel portion 130n.

[0192] The gate 150 of the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900 disposed in a first region (region ①) with low component reliability may include a first portion 151 and a second portion 152. The first portion 151 at least partially overlaps with the channel portion 130n of the active layer 130. The second portion 152 has a thickness less than that of the first portion 151 and at least partially overlaps with the channel portion 130n of the active layer 130. Furthermore, the light transmittance of the second portion 152 is greater than that of the first portion 151.

[0193] The gate 150 of the thin-film transistor disposed in the second region (region ②) which has high component reliability may not include the second portion 152. The gate 150 of the thin-film transistor disposed in the second region (region ②) may have the same thickness as the first portion 151. For example, the thin-film transistor disposed in the second region (region ②) may have Figure 12B The structure shown.

[0194] For example, the gate 150 of the thin-film transistor disposed in the second region (region ②) of the mother substrate may have the same thickness as the first portion 151 of the gate 150 of the thin-film transistor disposed in the second region, without having a stepped thickness profile. More specifically, the entire gate 150 of the thin-film transistor disposed in the second region of the mother substrate may have the same thickness as the first portion 151.

[0195] According to another embodiment of the present invention, the mother substrate may include a third region (region ③) that is distinct from the first region (region ①) and the second region (region ②). The third region (region ③) of the mother substrate corresponds to the region (region ③) having an intermediate level of reliability. The third region (region ③) of the mother substrate corresponds to the third region of the mother panel 1000.

[0196] Since the thin-film transistor included in the third region (region ③) has an intermediate level of reliability, the area of ​​the second part 152 can be reduced compared to the area of ​​the second part of the thin-film transistor included in the first region (region ①).

[0197] Specifically, the gate 150 of the thin-film transistor disposed in the third region (region ③) includes a first portion 151 and a second portion 152. The first portion 151 overlaps with at least a portion of the channel portion 130n of the active layer 130. The second portion 152 has a smaller thickness than the first portion 151 and at least partially overlaps with the channel portion 130n of the active layer 130. The gate 150 of the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900 disposed in the third region (region ③) of the mother substrate may include the first portion 151 and the second portion 152.

[0198] The area of ​​the second portion 152 of the gate 150 in the thin-film transistor disposed in the third region (region ③) may be smaller than the area of ​​the second portion 152 of the gate 150 in the thin-film transistor disposed in the first region (region ①). Optionally, the thickness of the second portion 152 of the gate 150 in the thin-film transistor disposed in the third region (region ③) may be greater than the thickness of the second portion 152 of the gate 150 in the thin-film transistor disposed in the first region (region ①).

[0199] For example, the second portion 152 of the gate 150 included in the thin-film transistor disposed in the third region (region ③) may have a smaller area or a larger thickness than the second portion 152 of the gate 150 included in the thin-film transistor disposed in the first region (region ①).

[0200] The following describes a display device according to another embodiment of the present invention. The display device according to another embodiment of the present invention may include the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900 described above. The display device may include LED, OLED, LCD, PDP, micro-LED, or mini-LED display devices.

[0201] Figure 13 This is a schematic diagram illustrating a display device 1100 according to yet another embodiment of the invention.

[0202] like Figure 13 As shown, a display device 1100 according to another embodiment of the present invention includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0203] Gate lines GL and data lines DL are disposed in the display panel 310, and multiple pixels P are disposed in the intersection area of ​​gate lines GL and data lines DL. Images are displayed by driving the pixels P.

[0204] The controller 340 controls the gate driver 320 and the data driver 330.

[0205] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0206] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Additionally, control signals for controlling the shift register may be included in the gate control signal GCS.

[0207] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0208] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and provides the data voltage to the data line DL.

[0209] Gate driver 320 may include shift register 350.

[0210] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage capable of turning on the switching elements (thin-film transistors) disposed in the pixel P.

[0211] In addition, shift register 350 provides a gate cutoff signal to gate line GL during other periods of a frame when no gate pulse is provided, which enables the switching element to turn off. Hereinafter, the gate pulse and gate cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0212] According to one embodiment of the present invention, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 is referred to as a gate-in-panel (GIP) structure.

[0213] The gate driver 320 may include a plurality of thin-film transistors. The plurality of thin-film transistors included in the gate driver 320 may be disposed in the shift register 350.

[0214] According to one embodiment of the present invention, each of a plurality of thin-film transistors disposed in a gate driver 320 includes an active layer 130 and a gate 150. The active layer 130 includes a channel portion 130n. The gate 150 of the thin-film transistor disposed in the gate driver 320 may or may not include a second portion 152. The thin-film transistors disposed in the gate driver 320 may have the same structure as each of the aforementioned thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900, or may have a different structure. Figure 12B The structure shown.

[0215] For example, the gate 150 of the thin-film transistor disposed in the gate driver 320 may have a second portion 152, or may have the same thickness as the first portion 151 of the gate of the thin-film transistor disposed in the pixel driving circuit, without having a stepped thickness profile.

[0216] Figure 14 It is a diagram Figure 13 The circuit diagram of any pixel P. Figure 15 It is a diagram Figure 14 A planar image of pixel P. Figure 16 It is a cross-sectional view taken along line III-III' in Figure 12.

[0217] Figure 14The circuit diagram is an equivalent circuit diagram of a pixel P of a display device 1100 that includes an organic light-emitting diode (OLED) as a display element 710. Pixel P includes the display element 710 and a pixel driving circuit PDC for driving the display element 710.

[0218] According to another embodiment of the present invention, the display device 1100 includes a plurality of pixels P having a pixel driving circuit PDC. The pixel driving circuit PDC includes a first thin-film transistor TR1 and a second thin-film transistor TR2. At least one of the aforementioned thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900 can be used as at least one of the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0219] According to another embodiment of the present invention, the first thin-film transistor TR1 is a driving transistor, and the second thin-film transistor TR2 is a switching transistor.

[0220] The second thin-film transistor TR2 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided via the gate line GL.

[0221] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0222] The driving power line PL provides a driving voltage Vdd to the display element 710, and the first thin-film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0223] When the second thin-film transistor TR2 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata provided via the data line DL is supplied to the gate G2 of the first thin-film transistor TR1, which is connected to the display element 710. The data voltage Vdata is charged into the storage capacitor C1 formed between the gate G2 and the source S2 of the first thin-film transistor TR1.

[0224] The amount of current supplied to the organic light-emitting diode (OLED) 710 via the first thin-film transistor TR1 is controlled according to the data voltage Vdata, thereby controlling the gray level of the light emitted from the display element 710.

[0225] Reference Figure 15 and 16 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0226] The substrate 110 may be made of glass or plastic. Plastics with flexible properties, such as polyimide (PI), may be used as the substrate 110.

[0227] Light-shielding layers 111 and 211 are disposed on substrate 110. Light-shielding layers 111 and 211 can block light incident from the outside to protect active layers A1 and A2.

[0228] A buffer layer 120 is disposed on light-shielding layers 111 and 211. The buffer layer 120 is made of insulating material and protects the active layers A1 and A2 from external moisture or oxygen.

[0229] The active layer A1 of the first thin-film transistor TR1 and the active layer A2 of the second thin-film transistor TR2 are disposed on the buffer layer 120. For example, the active layers A1 and A2 may comprise an oxide semiconductor material. The active layers A1 and A2 may be composed of oxide semiconductor layers made of an oxide semiconductor material. The active layers A1 and A2 may have a multilayer structure.

[0230] The gate insulating layer 140 is disposed on the active layers A1 and A2.

[0231] The gate G1 of thin-film transistor TR1 and the gate G2 of thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0232] Gates G1 and G2 may each include a first portion 151 and a second portion 152. The first portion 151 at least partially overlaps with the channel portions of active layers A1 and A2. The second portion 152 has the same thickness as the first portion 151 and at least partially overlaps with the channel portions of active layers A1 and A2. Due to the thickness difference between the first portion 151 and the second portion 152, gates G1 and G2 may have a stepped thickness profile.

[0233] The light transmittance of the second part 152 is greater than that of the first part 151.

[0234] Furthermore, the gate line GL may be disposed on the gate insulating layer 140. The gate G2 of the second thin-film transistor TR2 may extend from the gate line GL, but one embodiment of the present invention is not limited thereto, and a portion of the gate line GL may be the gate G2 of the second thin-film transistor TR2.

[0235] Reference Figure 15 and 16 The first capacitor electrode C11 of the storage capacitor C1 is disposed in the same layer as the gates G1 and G2. The first capacitor electrode C11 can be connected to the gate G1 of the first thin-film transistor TR1. The first capacitor electrode C11 can be integrally formed with the gate G1 of the first thin-film transistor TR1.

[0236] An interlayer insulating layer 160 is disposed on gates G1 and G2, gate line GL, and first capacitor electrode C11. The interlayer insulating layer 160 may be made of organic or inorganic insulating materials.

[0237] The source S1 and drain D1 of the first thin-film transistor TR1 and the source S2 and drain D2 of the second thin-film transistor TR2 are disposed on the interlayer insulating layer 160. The data line DL, the drive power line PL, and the second capacitor electrode C12 of the storage capacitor C1 can be disposed on the interlayer insulating layer 160.

[0238] A portion of the drive power line PL may extend to become the drain D1 of the first thin-film transistor TR1. The drain D1 of the first thin-film transistor TR1 is connected to the active layer A1 via a contact hole H1.

[0239] The source S1 of the first thin-film transistor TR1 can be connected to the active layer A1 via contact hole H2, and can be connected to the light-shielding layer 111 via another contact hole H3.

[0240] The source S1 of the first thin-film transistor TR1 and the second capacitor electrode C12 are connected to each other. The source S1 of the first thin-film transistor TR1 and the second capacitor electrode C12 can be formed as one unit.

[0241] A portion of the data line DL can extend to become the source S2 of the second thin-film transistor TR2. The source S2 of the second thin-film transistor TR2 can be connected to the active layer A2 via the contact hole H4.

[0242] The drain D2 of the second thin-film transistor TR2 can be connected to the active layer A2 via contact hole H5, to the light-shielding layer 211 via another contact hole H6, and to the first capacitor electrode C11 via another contact hole H7.

[0243] A planarization layer 180 is disposed on the source S1 and drain D1 of the first thin film transistor TR1, the source S2 and drain D2 of the second thin film transistor TR2, the data line DL, the drive power line PL, and the second capacitor electrode C12.

[0244] The planarization layer 180 is made of an insulating layer, which planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0245] The first pixel electrode 711 of the display element 710 is disposed on the planarization layer 180. The first pixel electrode 711 is in contact with the second capacitor electrode C12 via a contact hole H8 formed in the planarization layer 180. As a result, the first pixel electrode 711 can be connected to the source S1 of the first thin film transistor TR1.

[0246] The embankment 750 is disposed at the edge of the first pixel electrode 711. The embankment 750 defines the light-emitting area of ​​the display element 710.

[0247] An organic light-emitting layer 712 is disposed on the first pixel electrode 711, and a second pixel electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 15 and 16 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 1100 according to another embodiment of the present invention is an organic light-emitting display device.

[0248] Figure 17 This is a circuit diagram illustrating any pixel P of a display device 1200 according to another embodiment of the present invention.

[0249] Figure 17 This is an equivalent circuit diagram illustrating the pixel P of an organic light-emitting display device.

[0250] Figure 17 The pixel P of the display device 1200 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0251] In pixel P, signal lines DL, GL, PL, RL, and SCL are set to provide signals to the pixel driving circuit PDC.

[0252] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for driving the pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL.

[0253] The pixel driving circuit PDC includes, for example, a second thin-film transistor TR2 (switching transistor) connected to the gate line GL and the data line DL; a first thin-film transistor TR1 (driving transistor) for controlling the amplitude of the current output to the display element 710 according to the data voltage Vdata transmitted via the second thin-film transistor TR2; and a third thin-film transistor TR3 (reference transistor) for sensing the characteristics of the first thin-film transistor TR1.

[0254] The storage capacitor C1 is disposed between the gate of the first thin-film transistor TR1 and the display element 710.

[0255] The second thin-film transistor TR2 is turned on by the scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate of the first thin-film transistor TR1.

[0256] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL located between the first thin-film transistor TR1 and the display element 710, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the first thin-film transistor TR1 as a driving transistor during the sensing period.

[0257] A second node n2, connected to the gate of the first thin-film transistor TR1, is connected to the second thin-film transistor TR2. A storage capacitor C1 is formed between the second node n2 and the first node n1.

[0258] When the second thin-film transistor TR2 is turned on, the data voltage Vdata supplied via the data line DL is provided to the gate of the first thin-film transistor TR1. The data voltage Vdata is then charged into the storage capacitor C1 formed between the gate and source of the first thin-film transistor TR1.

[0259] When the first thin-film transistor TR1 is turned on, current is supplied to the display element 710 via the first thin-film transistor TR1 according to the driving voltage Vdd used to drive the pixel, thereby outputting light from the display element 710.

[0260] Figure 18 This is a circuit diagram illustrating any pixel of a display device 1300 according to another embodiment of the present invention.

[0261] Figure 18 The pixel P of the display device 1300 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0262] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0263] In pixel P, signal lines DL, EL, GL, PL, SCL, and RL are set to provide drive signals to the pixel drive circuit PDC.

[0264] and Figure 17 Compared to the pixel P, Figure 18 The pixel P further includes an emission control line EL. An emission control signal EM is provided to the emission control line EL.

[0265] In addition, with Figure 17 Compared to the pixel drive circuit PDC, Figure 18 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4, which serves as a light-emitting control transistor for controlling the light-emitting timing of the first thin-film transistor TR1.

[0266] The storage capacitor C1 is disposed between the gate of the first thin-film transistor TR1 and the display element 710.

[0267] The second thin-film transistor TR2 is turned on by the scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate of the first thin-film transistor TR1.

[0268] The third thin-film transistor TR3 is connected to the reference line RL, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the first thin-film transistor TR1, which is the driving transistor, during the sensing period.

[0269] The fourth thin-film transistor TR4 transmits a driving voltage Vdd to the first thin-film transistor TR1 according to the light emission control signal EM, or shields the driving voltage Vdd. When the fourth thin-film transistor TR4 is turned on, current is supplied to the first thin-film transistor TR1, thereby outputting light from the display element 710.

[0270] In addition to the structure described above, the pixel driving circuit PDC according to another embodiment of the present invention can be formed in various structures. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0271] Figure 19 This is a circuit diagram illustrating any pixel of a display device 1400 according to another embodiment of the present invention.

[0272] Figure 19 The display device 1400 shown is a liquid crystal display device. Figure 19 The pixel P of the display device 1400 shown includes a pixel driving circuit PDC and a liquid crystal capacitor Clc connected to the pixel driving circuit PDC. The liquid crystal capacitor Clc corresponds to the display element.

[0273] The pixel driving circuit PDC includes: a thin-film transistor TR connected to the gate line GL and the data line DL; a pixel electrode 371 connected to the thin-film transistor TR; a common electrode 372 facing the pixel electrode 371; and a storage capacitor Cst connected between the thin-film transistor TR and the common electrode 372. A liquid crystal capacitor Clc is connected in parallel with the storage capacitor Cst between the thin-film transistor TR and the common electrode 372.

[0274] The liquid crystal capacitor Clc is charged with a differential voltage between the data signal supplied to the pixel electrode via the thin-film transistor TR and the common voltage Vcom supplied to the common electrode 372, and the amount of light transmission is controlled by driving the liquid crystal according to the charged voltage. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

[0275] The display device 1400 according to another embodiment of the present invention may include at least one of the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900 described above.

[0276] Figure 20 This is a schematic diagram illustrating a display device 1500 according to another embodiment of the present invention.

[0277] Reference Figure 20 The display device 1500 may include a substrate 110, a gate driver 320, a data driver 330, and a controller 340.

[0278] Gate lines GL and data lines DL can be disposed on substrate 110, and pixels P can be disposed in the intersection area of ​​gate lines GL and data lines DL to form a display panel (not shown, see [reference]). Figure 13 (310). Multiple pixels P may be disposed on substrate 110. Pixel P may include display element 710 and thin-film transistors for driving display element 710. According to another embodiment of the present invention, the area of ​​substrate 110 where pixels P are disposed may be referred to as a display portion. The display panel of display device 1500 according to another embodiment of the present invention may, for example, correspond to... Figure 11 Panel 6 is shown.

[0279] Reference Figure 20 The gate driver 320 may be disposed on the substrate 110. The gate driver 320 may include a plurality of thin-film transistors.

[0280] A display device 1500 according to another embodiment of the present invention may include a substrate 110 and a plurality of thin-film transistors on the substrate 110.

[0281] As described above, each of the plurality of thin-film transistors may include an active layer 130 having a channel portion 130n and a gate 150 separated from the active layer 130.

[0282] The substrate 110 includes a first region (region ①). The first region (region ①) of the substrate 110 may correspond to a first region with low reliability in the mother panel 1000 of FIG12.

[0283] Thin-film transistors can be disposed in a first region (region ①) of substrate 110. At least one of the aforementioned thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900 can be applied to thin-film transistors disposed in the first region (region ①) of substrate 110.

[0284] Specifically, the gate 150 of the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, and 900 disposed in the first region (region ①) of the substrate 110 may include: a first portion 151, which at least partially overlaps with the channel portion 130n of the active layer 130; and a second portion 152, which has a thickness less than that of the first portion 151. The second portion 152 at least partially overlaps with the channel portion 130n of the active layer 130. Furthermore, the light transmittance of the second portion 152 is greater than that of the first portion 151. A detailed description of the structure of the thin-film transistors will be omitted below to avoid repetition.

[0285] According to another embodiment of the present invention, at least a portion of the gate driver 320 may be disposed in a first region (region ①) of the substrate 110, and at least a portion of the thin-film transistor included in the gate driver 320 may be disposed in the first region (region ①). Therefore, the gate driver 320 may include, according to Figure 1A , 1B At least one of the following thin-film transistors: 100, 200, 300, 400, 500, 600, 700, 800, and 900: 2, 3, 4A, 4B, 5, 6, 7, 8, and 9.

[0286] A portion of the plurality of pixels P disposed on the substrate 110 may be disposed in a first region (region ①) of the substrate 110. Therefore, at least a portion of the pixels P may include, according to Figure 1A , 1B At least one of the following thin-film transistors: 100, 200, 300, 400, 500, 600, 700, 800, and 900: 2, 3, 4A, 4B, 5, 6, 7, 8, and 9.

[0287] Reference Figure 20 The substrate 110 may include a second region (region ②) distinct from the first region (region ①). The second region (region ②) of the substrate 110 may correspond to Figure 11 The mother panel 1000 has a highly reliable second zone.

[0288] The gate of the thin-film transistor disposed in the second region (region ②) may have the same height as the first portion 151, without a thickness difference. For example, having Figure 12B The thin-film transistor with the structure shown can be applied to thin-film transistors disposed in the second region (region ②).

[0289] According to another embodiment of the present invention, at least a portion of the gate driver 320 may be included in the second region (region ②) of the substrate 110. Therefore, a portion of the gate driver 320 may include having Figure 12B The thin-film transistor shown has the following structure.

[0290] A portion of the plurality of pixels P disposed on the substrate 110 may be disposed in the second region (region ②) of the substrate 110. Therefore, at least a portion of the pixel P may include having Figure 12B The thin-film transistor shown has the following structure.

[0291] The substrate 110 may further include a third region (region ③) that is distinct from the first region (region ①) and the second region (region ②). The third region (region ③) of the substrate 110 may correspond to... Figure 11 The third zone in the mother panel 1000 has an intermediate level of reliability.

[0292] The gate of the thin-film transistor disposed in the third region (region ③) may include: a first portion 151 that at least partially overlaps with the channel portion 130n of the active layer 130; and a second portion 152 having a thickness less than that of the first portion 151. The second portion 152 at least partially overlaps with the channel portion 130n of the active layer 130. Furthermore, the light transmittance of the second portion 152 may be greater than that of the first portion 151.

[0293] The area of ​​the second portion 152 of the gate 150 included in the thin-film transistor disposed in the third region (region ③) may be smaller than the area of ​​the second portion 152 of the gate 150 included in the thin-film transistor disposed in the first region (region ①).

[0294] The thickness of the second portion 152 of the gate 150 included in the thin-film transistor disposed in the third region (region ③) may be greater than the thickness of the second portion 152 of the gate 150 included in the thin-film transistor disposed in the first region (region ①).

[0295] For example, the second portion 152 of the gate 150 included in the thin-film transistor disposed in the third region (region ③) may have a smaller area or a larger thickness than the second portion 152 of the gate 150 included in the thin-film transistor disposed in the first region (region ①).

[0296] According to another embodiment of the present invention, at least a portion of the gate driver 320 may be included in the third region (region ③) of the substrate 110. Therefore, the gate driver 320 may include components according to… Figure 1A , 1B At least one of the following thin-film transistors: 100, 200, 300, 400, 500, 600, 700, 800, and 900: 2, 3, 4A, 4B, 5, 6, 7, 8, and 9.

[0297] In the thin-film transistor of the gate driver 320, the second portion 152 of the gate 150 disposed in the third region (region ③) may have a smaller area or a larger thickness than the second portion 152 of the gate 150 included in the thin-film transistor disposed in the first region (region ①).

[0298] A portion of the plurality of pixels P disposed on the substrate 110 may be disposed in the third region (region ③) of the substrate 110. Therefore, at least a portion of the pixels P may include, according to Figure 1A , 1B At least one of the following thin-film transistors: 100, 200, 300, 400, 500, 600, 700, 800, and 900: 2, 3, 4A, 4B, 5, 6, 7, 8, and 9.

[0299] In the thin-film transistor of pixel P located in the third region (region ③), the second portion 152 of the gate 150 may have a smaller area or a larger thickness than the second portion 152 of the gate 150 included in the thin-film transistor located in the first region (region ①).

[0300] According to the present invention, the following beneficial effects can be obtained.

[0301] A thin-film transistor according to one embodiment of the present invention includes a gate, the gate comprising a first portion having a relatively large thickness and a second portion having a relatively small thickness. According to one embodiment of the present invention, light is transmitted through the second portion of the gate, and the transmitted light resolves the electron trap of the active layer, thereby preventing reliability degradation of the thin-film transistor.

[0302] According to one embodiment of the invention, light is transmitted through a second portion of the gate having a smaller thickness, and the transmitted light illuminates the interface between the active layer and the gate insulating layer, thereby eliminating the electron trap that appears at the interface between the active layer and the gate insulating layer. As a result, changes in the threshold voltage of the thin-film transistor can be prevented.

[0303] Specifically, according to one embodiment of the present invention, variations in the threshold voltage of a thin-film transistor can be avoided or minimized under conditions of applied positive (+) bias voltage and constant temperature positive (+) bias temperature stress (PBTS).

[0304] A display device according to one embodiment of the present invention may include the thin-film transistor described above, thereby preventing the display quality from deteriorating over time and thus maintaining excellent display quality.

[0305] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments and drawings described herein; various substitutions, modifications, and variations may be made in this invention without departing from the spirit or scope thereof. Therefore, the scope of this invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this invention.

Claims

1. A display device, comprising: substrate; as well as Multiple thin-film transistors disposed on the substrate Each of the plurality of thin-film transistors includes: an active layer having a channel portion; and a gate spaced apart from the active layer. The active layer comprises an oxide semiconductor material. The substrate includes a first region. The gate of the thin-film transistor disposed in the first region includes: The first portion that at least partially overlaps with the channel portion of the active layer; and The second part has a thickness less than that of the first part and at least partially overlaps with the channel portion of the active layer. The light transmittance of the second part is greater than that of the first part. The second part has a light transmittance of 5% to 70%. Based on the plan view, the area occupied by the second portion in the entire region where the channel portion and the gate overlap is in the range of 10% to 60%.

2. The display device according to claim 1, wherein the second portion has a light transmittance of 10% to 50%.

3. The display device according to claim 1, wherein the first portion and the second portion are made of the same material.

4. The display device according to claim 1, wherein the first portion has a thickness of 100 nm or greater.

5. The display device according to claim 1, wherein the thickness of the second portion is 5% to 50% of the thickness of the first portion.

6. The display device according to claim 1, wherein the second portion has a thickness of 10 nm to 50 nm.

7. The display device according to claim 1, wherein, based on a plan view, the area occupied by the second portion in the entire region where the channel portion and the gate overlap is in the range of 10% to 50%.

8. The display device according to claim 1, wherein the gate has an area transmittance coefficient (ATC) of 1% to 10%, and the area transmittance coefficient (ATC) is calculated by the following Equation 1: Equation 1 ATC[%] = T x A, In Equation 1, T is the light transmittance of the second part and is expressed as a percentage (%). The light transmittance of the second part is the average light transmittance measured in the range of 360 nm to 740 nm. A is the area ratio of the second part calculated by Equation 2 below: Equation 2 A = Area of ​​the second portion overlapping with the channel portion / Area of ​​the gate overlapping with the channel portion.

9. The display device according to claim 1, wherein the second portion has a circular, elliptical, semi-circular, semi-elliptical, or polygonal plane in a plan view.

10. The display device according to claim 1, wherein the first portion is located on one side of the gate and the second portion is located on the other side of the gate.

11. The display device of claim 1, wherein the first portion surrounds the second portion.

12. The display device according to claim 1, wherein the gate comprises at least one of molybdenum (Mo) and titanium (Ti).

13. The display device according to claim 1, wherein the active layer comprises at least one of IGZO (InGaZnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, FIZO (FeInZnO) based oxide semiconductor material, ZnO based oxide semiconductor material, SIZO (SiInZnO) based oxide semiconductor material, and ZnON (Zn oxynitride) based oxide semiconductor material.

14. The display device according to claim 1, wherein the active layer comprises: First oxide semiconductor layer; as well as A second oxide semiconductor layer on top of the first oxide semiconductor layer.

15. The display device of claim 14, wherein the active layer further comprises a third oxide semiconductor layer on the second oxide semiconductor layer.

16. The display device according to claim 1, further comprising a gate driver disposed on the substrate, The gate driver includes multiple thin-film transistors. At least a portion of the thin-film transistors included in the gate driver are disposed in the first region.

17. The display device according to claim 1, further comprising a plurality of pixels disposed on the substrate. Each of the plurality of pixels includes a thin-film transistor. At least a portion of the plurality of pixels are disposed in the first region.

18. The display device according to claim 1, wherein the substrate further comprises a second region separated from the first region. The gate of the thin-film transistor disposed in the second region has the same height as the first portion without any thickness difference.

19. The display device according to claim 1, wherein the substrate further comprises a third region separated from the first region. The gate of the thin-film transistor disposed in the third region includes: A first portion that at least partially overlaps with the channel portion of the active layer; as well as A second portion having a thickness less than that of the first portion and at least partially overlapping with the channel portion of the active layer. The second portion of the gate in the thin-film transistor disposed in the third region has a smaller area or a larger thickness than the second portion of the gate in the thin-film transistor disposed in the first region.

20. The display device according to claim 19, further comprising a gate driver disposed on the substrate, The gate driver includes multiple thin-film transistors. At least a portion of the thin-film transistors included in the gate driver are disposed in the third region.

21. The display device according to claim 19, further comprising a plurality of pixels disposed on the substrate. Each of the plurality of pixels includes a thin-film transistor. At least a portion of the plurality of pixels are disposed in the third region.

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