Real-time driving system, method and terminal for digital reconfigurable intelligent reflective surface

Abstract

The present invention belongs to the field of communication technology, and discloses a real-time driving system, method and terminal of a digital reconfigurable intelligent reflective surface. The system tasks are managed and scheduled through a PS-side communication module, and the structured data in the structured data frame is structured through a PS-side RIS driving module; after the array data is stored in a BRAM, the array table address is adapted and switched through a PL-side timing generation module, so as to realize the real-time switching of any array state; the PL-side FIFO data is output to a PL-side phase calculation module through bit width conversion, and the timing generator takes out and obtains the array control timing signal through phase calculation; the phase data is XORed to each unit state in the array through a PL-side phase calculation module to obtain the output state of the array, so as to realize the signal transmission based on BPSK modulation. The present invention improves the stability and real-time performance by a method in which the phase information and the array data information are transmitted separately and then calculated by the PL-side.

Description

Technical Field

[0001] The present invention belongs to the technical field of array antennas, and in particular relates to a real-time driving system, method and terminal of a digital reconfigurable intelligent reflection surface. Background Art

[0002] At present, the reconfigurable intelligent reflective surface (RIS) is an array surface composed of many low-cost passive periodic or non-periodic sub-wavelength units, and the state of each unit in the array can be independently controlled. The reflected signal of the unit in different states shows different properties such as phase, amplitude, polarization, etc., which makes RIS have flexible characteristics that can be defined by software. By jointly controlling each unit in RIS, electromagnetic wave control can be achieved, such as beamforming (for example, generating high-gain directional beams, or generating multi-beams pointing to multiple targets), or creating ideal multipath effects to enhance signal coverage and improve wireless channels, or based on the time domain switching of the unit state in RIS, the modulation of the incoming wave signal is realized to achieve communication. RIS transforms the passive adaptive channel of traditional wireless communication into an active controllable channel of wireless communication. The introduction of RIS can jointly optimize the receiving end, the transmitting end and the channel, and intelligently adjust the propagation of electromagnetic waves. At the same time, since it does not require high-cost devices such as mixers, digital-to-analog / analog-to-digital converters, and power amplifiers, RIS has the advantages of low cost and low power consumption, making it a key candidate technology for future wireless networks.

[0003] In recent years, many experiments in academia have proved that the reasonable deployment of RIS can improve user throughput and indoor and outdoor signal coverage performance. At the same time, RIS can achieve signal modulation and transmission by regulating the state of each unit in the time domain, thereby improving the signal. The paper Cheng, Qiang, et al. "Reconfigurable Intelligent Surfaces: Simplified-Architecture Transmitters-From Theory to Implementations." Proceedings of the IEEE 110.9 (2022): 1266-1289. published by the Southeast University team elaborates on the use of space-time domain coding technology to achieve beam scanning and beamforming on RIS, arbitrary multi-bit phase generation, and the realization of BPSK (Binary Phase-shift keying), QAM (quadrature amplitude modulation) and other modulation technologies.

[0004] Before RIS can be put into commercial use on a large scale, it still faces many problems and challenges in terms of technical research, engineering application, network deployment and standardization. At present, there is no unified universal interface and driving method for RIS in the industry. If it is necessary to develop actual communication-related applications of RIS based on spatiotemporal coding technology, it is necessary to implement a continuous dynamic real-time RIS control system based on actual hardware, so that each unit in each RIS can be stably, quickly and continuously controlled. Therefore, it is urgent to design a digital reconfigurable intelligent reflective surface driving system.

[0005] Through the above analysis, the problems and defects of the prior art are as follows: the reconfigurable intelligent reflective surface RIS in the industry is still lacking a unified universal interface and driving method. The existing driving methods, such as the control method based on fixed-length data frames, which packages the array matrix data or application required data (such as the beam scanning angle of RIS, etc.) and sends it to the RIS controller, are difficult to realize the flexible software-defined characteristics of RIS (implementing different functions of RIS through different software on the same RIS hardware platform), or in the case of large arrays with a large number of units and bits, it is difficult to achieve high-speed real-time driving in the time domain due to the limitations of data bandwidth. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention provides a real-time driving system, method and terminal for a digital reconfigurable intelligent reflective surface.

[0007] The present invention is implemented as follows: a real-time driving system for a digitally reconfigurable intelligent reflective surface, the real-time driving system for a digitally reconfigurable intelligent reflective surface comprising:

[0008] PS communication module, the PS of ZYNQ runs a real-time operating system, which is used to manage and schedule the tasks of the real-time drive system of the digital reconfigurable intelligent reflective surface;

[0009] The PS-side RIS driver module is used for the structured data contained in the structured data frame;

[0010] The PL-side timing generation module, when the array data is stored in the BRAM, switches the array data by revising the array table address to achieve real-time switching of any array state;

[0011] PL-side phase calculation module: PL-side FIFO data is output to the phase calculation module through bit width conversion, and the timing generator takes it out and obtains the final array control timing signal through phase calculation;

[0012] The PL-side phase calculation module obtains the output state of the array by taking the XOR of the phase data for the states of each unit in the array, thereby realizing signal transmission based on BPSK modulation.

[0013] Furthermore, the PS-side communication module uses the LWIP protocol stack to parse the Ethernet data sent by the PC, and completes the sending and receiving analysis of instructions and data streams between the PC; the instructions and data streams are deserialized using ProtocolBuffer to obtain structured data frames.

[0014] Furthermore, the structured data in the PS-side RIS driver module includes: control instructions for the RIS clock controller, phase data stream, array state address data stream, and array state data.

[0015] Furthermore, in the RIS driver module on the PS side, the clock control data will be written into the corresponding control register on the PL side through the AXI-Lite bus to realize the control of the clock frequency of each module; the phase data stream is the phase value of the data code element symbol during array communication modulation, and the array table address data stream is the address of the array data in the BRAM; the phase data stream and the array address data stream will be written into the corresponding FIFO, and the array status information is the actual status data set of each unit of the array, which will be written into the BRAM for use by the PL side.

[0016] Furthermore, the real-time switching of any array state can be achieved by using the method of cyclically writing data streams into BRAM through the PL-side timing generation module.

[0017] Furthermore, the RIS used by the PL-side phase calculation module is a 16×16 1-bit array.

[0018] Another object of the present invention is to provide a real-time driving method of a digital reconfigurable intelligent reflective surface using the real-time driving system of the digital reconfigurable intelligent reflective surface. The real-time driving method of the digital reconfigurable intelligent reflective surface comprises the following steps:

[0019] Step 1: Manage and schedule the tasks of the real-time operating system running on the PS side of ZYNQ through the PS side communication module, and structure the structured data in the data frame through the PS side RIS driver module;

[0020] Step 2: After the array data is stored in the BRAM, the array table address is adapted by the PL-side timing generation module to switch the array data, thus realizing the real-time switching of any array state.

[0021] Step 3: The PL-side FIFO data is output to the PL-side phase calculation module through bit width conversion, and the timing generator takes it out and obtains the final array control timing signal through phase calculation;

[0022] Step 4: Through the PL-side phase calculation module, the phase data is XORed to the state of each unit in the array to obtain the output state of the array, thereby realizing signal transmission based on BPSK modulation.

[0023] Another object of the present invention is to provide a computer device, the computer device comprising a memory and a processor, the memory storing a computer program, and when the computer program is executed by the processor, the processor executes the steps of the real-time driving method of the digital reconfigurable intelligent reflective surface.

[0024] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the steps of the real-time driving method of the digital reconfigurable intelligent reflective surface.

[0025] Another object of the present invention is to provide an information data processing terminal, which is used to implement the real-time driving system of the digital reconfigurable intelligent reflective surface.

[0026] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0027] First, in view of the technical problems existing in the above-mentioned prior art and the difficulty of solving the problems, the technical solutions to be protected by the present invention and the results and data during the research and development process are closely combined to analyze in detail and deeply how the technical solutions of the present invention solve the technical problems, and some creative technical effects brought about after solving the problems. The specific description is as follows:

[0028] The real-time driving system of the digital reconfigurable intelligent reflective surface provided by the present invention completes the control of the RIS array through the collaborative development of ZYNQ software and hardware, and is suitable for the RIS system using low-cost circuit solutions such as shift registers. The scanning characteristic data and phase modulation method of the beam are calculated by the PC end, and the array phase transformation and array data control are realized by sending a data stream method from the PC end to realize communication modulation. At the same time, the array beam scanning control can also be completed, thereby improving the availability of RIS, reducing the difficulty of developing applications based on RIS, and maximizing the flexibility of software-defined functions in RIS.

[0029] The present invention provides a method for realizing real-time continuous regulation of a 16×16 RIS array through an Ethernet interface, which mainly solves the following technical problems:

[0030] 1. Adjust the main frequency of the clock controller of each module through the register to achieve adjustable array switching frequency.

[0031] 2. Send symbol information, unit phase sequence information corresponding to the symbol and array state data stream through PC to realize real-time control of the phase time domain waveform and state distribution of the array, thereby realizing beam forming, beam scanning, communication modulation and other functions.

[0032] 3. It is suitable for RIS systems controlled by low-cost solutions such as shift registers. Under the condition of using a single ZYNQ chip, a real-time array switching speed of more than 5MHz has been achieved for RIS above 16×16 1bit, which meets the required indicators of RIS modulation communication technology based on array phase switching and beam scanning direction switching.

[0033] Second, considering the technical solution as a whole or from the perspective of the product, the technical effects and advantages of the technical solution to be protected by the present invention are described in detail as follows:

[0034] The present invention adopts a method in which the phase information and the array data information are transmitted separately and then the calculation is performed by the PL end, which can avoid the problem of occupying a large bandwidth caused by the real-time transmission of the entire array status information data in modulation applications based on BPSK, thereby improving stability and real-time performance.

[0035] The present invention stores array data information and unit sequence information corresponding to symbols in BRAM, realizes time domain modulation by transmitting BRAM address, provides flexibility in developing communication applications, and fully realizes software-defined RIS array control.

[0036] The clock of each module of the present invention can be controlled individually, and the RIS working mode can be flexibly adjusted to adapt to various application scenarios. For example, the modulation communication technology based on TDC (time-domain coding) requires fast switching of the array, while spatial beam scanning only requires modification of the entire array.

[0037] Third, as auxiliary evidence of the inventiveness of the claims of the present invention, it is also reflected in the following important aspects:

[0038] The technical solution of the present invention fills the technical gap in the industry at home and abroad:

[0039] The present invention provides a flexible RIS driving method that can realize software definition, which can make RIS fully have software-defined characteristics, and the specific functions can be determined by the data stream sent by the PC end, such as the array unit matrix data required for beam scanning, the symbol data stream required for communication modulation, the spatial scanning angle data stream required for time-space domain coding, etc. The driving system with software-defined characteristics can also speed up the development and verification of RIS-related applications and reduce the extra time overhead caused by modifying programmable logic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a flow chart of a real-time driving method for a digital reconfigurable intelligent reflective surface provided by an embodiment of the present invention;

[0042] Figure 2 is a schematic diagram of a digital reconfigurable intelligent reflective surface real-time driving system provided by an embodiment of the present invention;

[0043] Figure 3 is a schematic diagram of a front state calculation module provided by an embodiment of the present invention;

[0044] Figure 4 It is a schematic diagram of the array calculation state of the timing generator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] In view of the problems existing in the prior art, the present invention provides a real-time driving system, method and terminal for a digital reconfigurable intelligent reflective surface. The present invention is described in detail below with reference to the accompanying drawings.

[0047] 1. Explanatory Examples In order to enable those skilled in the art to fully understand how to implement the present invention, this section provides an illustrative example that expands and describes the technical solution of the claims.

[0048] like Figure 1 As shown, the real-time driving method of a digital reconfigurable intelligent reflective surface provided by an embodiment of the present invention comprises the following steps:

[0049] S101, managing and scheduling the tasks of the real-time operating system running on the PS side of the Xilinx ZYNQ series platform processor (ZYNQ) through the communication module of the Processing System (PS) side, and structuring the structured data in the data frame through the RIS driver module on the PS side;

[0050] S102, after the array data is stored in the block random access memory (BRAM), the array table address is adapted to switch the array data through the timing generation module of the programmable logic (PL) end, so as to realize the real-time switching of any array state;

[0051] S103, the data of the FIFO memory at the PL end is output to the phase calculation module at the PL end through bit width conversion, and the timing generator takes it out and obtains the final array control timing signal through phase calculation;

[0052] S104, using the PL-side phase calculation module to perform XOR on the phase data of each unit state in the array to obtain the output state of the array, thereby realizing signal transmission based on binary phase shift keying (BPSK) modulation.

[0053] like Figure 2 As shown, the digital reconfigurable intelligent reflective surface real-time driving system provided by the embodiment of the present invention is completed by the software and hardware collaborative development of the Xilinx ZYNQ chip, specifically including:

[0054] PS communication module: The PS of ZYNQ runs a real-time operating system to manage and schedule tasks for the entire system. It uses the LWIP protocol stack to parse Ethernet data sent by the PC and complete the sending and receiving of instructions and data streams between the PC. The instructions and data streams are deserialized using ProtocolBuffer to obtain structured data frames.

[0055] RIS driver module on the PS side: The structured data contained in the structured data frame includes control instructions for the RIS clock controller, phase data stream, array status address data stream, and array status data. The clock control data will be written to the corresponding control register on the PL side through the AXI-Lite bus to control the clock frequency of each module. The phase data stream is the phase value of the data code symbol during array communication modulation, and the array table address data stream is the address of the array data in the BRAM. The phase data stream and the array address data stream will be written to the corresponding FIFO. The array status information is the actual status data set of each unit of the array, which will be written to the BRAM for use on the PL side.

[0056] PL-side timing generation module: After the array data is stored in BRAM, the array data can be quickly switched by revising the array table address. The real-time switching of any array state can be achieved by writing the data stream into BRAM in a loop.

[0057] PL-side phase calculation module: The PL-side FIFO data is output to the phase calculation module through bit width conversion. The timing generator takes it out and obtains the final array control timing signal through phase calculation.

[0058] PL-side phase calculation module: The RIS used in this solution case is a 16×16 1-bit array. By taking the XOR of the phase data on the states of each unit in the array to obtain the output state of the array, signal transmission based on BPSK modulation is achieved.

[0059] Figure 2 The software and hardware architecture of the ZYNQ chip provided by the embodiment of the present invention is included, which is divided into two parts: the PL end and the PS end. The PS end first receives the Ethernet data from the PC. After being parsed by the LWIP protocol stack, the data packet will be deserialized through the ProtocolBuffer module. The structured data frame obtained after deserialization is divided into two parts: register control instructions and data streams. The register control instructions will be sent to the AXI4 write module, and the data stream will be further parsed into the data that needs to be written to the PL end through the array distribution calculation module and sent to the AXI4 write module. The AXI4 write module is responsible for the final AXI bus write operation to complete the communication with the PL end. The clock controller, array state table address FIFO, symbol data FIFO, timing generator, and BRAM controller of the PL end are all connected to the AXI bus. The clock controller will generate a clock signal of a certain frequency according to its register state. These clock lines are connected to the timing generator, symbol data FIFO, and array state address FIFO. The symbol data FIFO transmits data to the timing generator under the control of the clock line. The array state table address FIFO transfers data to the array state data BRAM under the control of the clock line, controlling the data output of the BRAM. The BRAM controller completes the writing of the BRAM under the control of the AXI bus. Finally, the timing generator outputs the data signal to the register IO port of the RIS after internal calculation.

[0060] Figure 3 This is a principle block diagram of an array state calculation module provided in an embodiment of the present invention. In the figure, the symbol data sequence from the FIFO will control the output data of the BRAM used to store the unit phase sequence corresponding to the symbol. The array unit data phase from the BRAM is superimposed with the phase data sequence output by the BRAM to obtain the final time domain sequence of the entire RIS array state data.

[0061] Figure 4The schematic diagram of the array calculation state of the timing generator provided by the embodiment of the present invention. The symbol data FIFO will enter the array calculation module through the data bit width converter, and the output data of the BRAM used to store the array state data will also enter the array state calculation module. The result calculated by this module will generate the final IO control timing through the data bit width conversion, and finally connected to the IO port of the RIS.

[0062] Embodiment 1:

[0063] This embodiment provides a method for controlling RIS to perform beam scanning by using the driving method. First, the array distribution matrix data M1 corresponding to the RIS array at each scanning angle is calculated by the PC end, and the data frame to be sent is obtained by serializing it through ProtocolBuffer. This step is Figure 2 The PC part is not expanded in detail in the figure. Figure 2 As shown, the data is sent to the PS side of ZYNQ via Ethernet, the data frame is received by LWIP and deserialized using ProtocolBuffer to obtain M1, and then written to the BRAM in the PL side through the register control instruction module. At this time, the PC side can achieve fast switching of the scanning angle by sending the BRAM address data stream S1 corresponding to the time domain scanning angle. Based on the fast switching of the scanning angle, a specific S1 can be further sent based on the PC side to achieve RIS communication modulation based on time-space domain coding technology. The RIS driver implemented by this method has software-defined flexibility. Developers can calculate different array distributions on the PC side and store them in BRAM, and achieve array switching by sending BRAM address data streams, thereby achieving different functions.

[0064] Embodiment 2:

[0065] This embodiment provides a method for applying the driving method to control a 1-bit RIS to realize BSPK communication in the target direction. First, through Example 1, the writing of the scanning angle data is completed. At this time, S1 is a constant, which is equal to the target azimuth angle required for communication. The symbol data stream S2 required for communication will be obtained by the PC end by source encoding the data source. The array phase distribution matrix data M2 corresponding to each symbol is also calculated by the PC, and the two are serialized together through ProtocolBuffer to obtain the data frame to be sent. This step is Figure 2 The PC part is not expanded in detail in the figure. Figure 2 As shown, the data frame is sent to the PS end of ZYNQ via Ethernet, received by LWIP and deserialized using ProtocolBuffer to obtain S2 and M2. M2 will be written to the corresponding BRAM. S2 enters the timing generator (such as Figure 4After that, the bit width conversion is performed. This step realizes the mapping from the symbol data stream to the address stream. Then the array state calculation is performed (as shown in Figure 3 As shown in the figure, the array state data read by S2 will be superimposed with the array data corresponding to S1 (here, the 1-bit case is an XOR operation) to generate the final array data, which will be further converted to the IO port of RIS through bit width conversion (here, taking the 1-bit 16x16 array based on the 8-bit shift register as an example, 256 bits to 32 bits), thereby realizing the drive control of BSPK modulation of the data source through RIS.

[0066] The embodiments of the present invention have achieved some positive effects during the development or use process, and indeed have great advantages over the prior art. The following content is described in conjunction with data, charts, etc. of the test process.

[0067] Experiments were conducted on a 1-bit 16×16RIS based on an 8-bit shift register hardware architecture. The theoretical switching speed of the array state can reach more than 5MHz when using the default 50MHz clock, and a higher switching rate can be achieved by adjusting the clock module. At the same time, by sending different data streams through the PC, each unit of the array can be controlled at the same time, realizing array beam scanning, and further realizing functions such as BPSK signal modulation on this basis.

[0068] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0069] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A real-time driving system for a digitally reconfigurable intelligent reflective surface, characterized in that: The real-time driving system of the digital reconfigurable smart reflective surface includes: PS communication module, the PS of ZYNQ runs a real-time operating system, which is used to manage and schedule the tasks of the real-time drive system of the digital reconfigurable intelligent reflective surface; The PS-side RIS driver module is used for the structured data contained in the structured data frame; The timing generation module at the PL end, after the array data is stored in the BRAM, switches the array data by revising the array table address to achieve real-time switching of any array state; PL-side phase calculation module, the PL-side FIFO data is output to the phase calculation module through bit width conversion, the timing generator takes it out and obtains the final array control timing signal through phase operation; the output state of the array is obtained by taking XOR of the phase data to the state of each unit in the array, thereby realizing signal transmission based on BPSK modulation.

2. The real-time driving system of the digital reconfigurable intelligent reflective surface according to claim 1, characterized in that: The PS communication module uses the LWIP protocol stack to parse the Ethernet data sent by the PC and completes the sending and receiving analysis of instructions and data streams between the PC; the instructions and data streams are deserialized using ProtocolBuffer to obtain structured data frames.

3. The real-time driving system of the digital reconfigurable intelligent reflective surface according to claim 1, characterized in that: The structured data in the RIS driver module on the PS side includes: control instructions for the RIS clock controller, phase data stream, array state address data stream and array state data.

4. The real-time driving system of the digital reconfigurable intelligent reflective surface according to claim 1, characterized in that: In the RIS driver module on the PS side, the clock control data will be written into the corresponding control register on the PL side through the AXI-lite bus to realize the control of the clock frequency of each module; the phase data stream is the phase value of the data code element symbol during array communication modulation, and the array table address data stream is the address of the array data in the BRAM; the phase data stream and the array address data stream will be written into the corresponding FIFO, and the array status information is the actual status data set of each unit of the array, which will be written into the BRAM for use by the PL side.

5. The real-time driving system of a digital reconfigurable intelligent reflective surface according to claim 1, characterized in that: The PL-side timing generation module uses the method of cyclically writing data streams into BRAM to achieve real-time switching of any array state.

6. The real-time driving system of a digital reconfigurable intelligent reflective surface according to claim 1, characterized in that: The RIS used by the PL-side phase calculation module is a 16×16 1-bit array.

7. A real-time driving method for a digital reconfigurable intelligent reflective surface using the real-time driving system for a digital reconfigurable intelligent reflective surface according to any one of claims 1 to 6, characterized in that: The real-time driving method of the digital reconfigurable intelligent reflective surface includes the following steps: Step 1: Manage and schedule the tasks of the real-time operating system running on the PS side of ZYNQ through the PS side communication module, and structure the structured data in the data frame through the PS side RIS driver module; Step 2: After the array data is stored in the BRAM, the array table address is adapted by the PL-side timing generation module to switch the array data, thus realizing the real-time switching of any array state. Step 3: The PL-side FIFO data is output to the PL-side phase calculation module through bit width conversion, and the timing generator takes it out and obtains the final array control timing signal through phase calculation; Step 4: Through the PL-side phase calculation module, the phase data is XORed to the state of each unit in the array to obtain the output state of the array, thereby realizing signal transmission based on BPSK modulation.

8. A computer device, characterized in that: The computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the real-time driving method of the digital reconfigurable intelligent reflective surface as claimed in claim 7.

9. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the real-time driving method of a digitally reconfigurable intelligent reflective surface as claimed in claim 7.

10. An information data processing terminal, characterized in that: The information data processing terminal is used to implement the real-time driving system of the digital reconfigurable intelligent reflective surface as described in any one of claims 1 to 6.

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