FPGA Link Driving Method, Apparatus, System, and Equipment Based on State Machine

Abstract

The application provides a state machine-based FPGA link driving method, device, system, equipment and medium, which is applied to a SOC chip in a car-machine display system, first, after initialization of a DPI interface and a DSI interface of the SOC chip is completed, a FPGA chip is controlled to enter an image checking mode and output a checking image to the FPGA chip; then, the FPGA chip is controlled to be powered on and run; then, when the FPGA chip is normally powered on, if it is determined that the DPI checking result and the DSI checking result returned by the FPGA chip both correspond to checking pass results, the FPGA chip is controlled to enter an image cutting mode; if it is determined that the current power-on of the FPGA chip in the image cutting mode is abnormal or the current DSI checking result corresponds to a checking failure result, re-initialization is returned. The FPGA chip is controlled by using a state machine mechanism, which not only meets the demand of multi-screen display, but also can be self-recovered when a screen of the car-machine appears an abnormal display condition.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of car machine technology, and in particular to a FPGA link driving method, device, system, computer equipment and storage medium based on state machine. BACKGROUND

[0002] At present, the screen of the car machine is multi-screen display (such as two screens, three screens or even more screens), and the SOC chip (the full name of SOC is System on Chip, which means system level chip) usually does not have so many screen display interfaces, and usually may support two screen display, and needs to divide one display into multiple displays to realize multi-screen display, and the division work usually needs to be completed by the FPGA chip (the full name of FPGA is Field Programmable Gate Array, which means field programmable logic gate array). Therefore, the SOC chip needs to control the FPGA chip to ensure the normality of the display link. However, at present, many controls of the FPGA chip are only simple controls such as power-on and power-off, without verification mechanism, without signal feedback of the FPGA chip, and without restart mechanism after verification exception, and cannot self-recover when the screen of the car machine appears display abnormality. SUMMARY

[0003] The embodiment of the present application provides a FPGA link driving method, device, system, computer equipment and storage medium based on state machine, the FPGA chip is controlled by the state machine mechanism, the control logic is more organized, the SOC chip can judge whether the display link is normal through the signal returned by the FPGA chip, the demand of multi-screen display is met, and self-recovery is realized when the screen of the car machine appears display abnormality.

[0004] In a first aspect, the embodiment of the present application provides a FPGA link driving method based on state machine, applied to a SOC chip in a car machine display system, wherein the car machine display system further comprises an FPGA chip, and the SOC chip is connected with the FPGA chip; the method comprises the following steps:

[0005] Initializing a DPI interface and a DSI interface of the SOC chip;

[0006] If it is detected that the initialization of the DPI interface and the DSI interface is completed, the FPGA chip is controlled to enter an image verification mode, and a preset verification image is output to the FPGA chip through the DPI interface and the DSI interface;

[0007] Controlling the FPGA chip to be powered on and run;

[0008] Detecting the power-on working state of the FPGA chip;

[0009] if it is determined that the power-on working state of the FPGA chip is a normal state, receiving a DPI check result and a DSI check result returned by the FPGA chip based on the check image;

[0010] if it is determined that the DPI check result and the DSI check result both correspond to a check pass result, controlling the FPGA chip to enter an image cutting mode and outputting a normal picture image;

[0011] obtaining a current power-on working state of the FPGA chip in the image cutting mode and a current DSI check result returned by the FPGA chip based on the normal picture image;

[0012] if it is determined that the current power-on working state of the FPGA chip is an abnormal state or the current DSI check result corresponds to a check failure result, returning to perform the initialization step of the DPI interface and the DSI interface of the SOC chip.

[0013] In a second aspect, an embodiment of the present application provides an FPGA link driving method based on a state machine, applied to a car machine display system, wherein the car machine display system comprises an SOC chip and an FPGA chip, the SOC chip is connected with the FPGA chip; the method comprises:

[0014] initializing a DPI interface and a DSI interface of the SOC chip;

[0015] if the SOC chip detects that the initialization of the DPI interface and the DSI interface is completed, controlling the FPGA chip to enter an image check mode and outputting a preset check image to the FPGA chip through the DPI interface and the DSI interface;

[0016] receiving the check image by the FPGA chip;

[0017] controlling the FPGA chip to run in power-on by the SOC chip;

[0018] running in power-on by the FPGA chip and returning a power-on working state to the SOC chip;

[0019] detecting the power-on working state of the FPGA chip by the SOC chip;

[0020] if it is determined that the power-on working state of the FPGA chip is a normal state, receiving a DPI check result and a DSI check result returned by the FPGA chip based on the check image;

[0021] The SOC chip determines that the DPI check result and the DSI check result correspond to check pass results, controls the FPGA chip to enter an image cutting mode, and outputs a normal picture image.

[0022] The FPGA chip receives the normal picture image, cuts the normal picture image based on the image cutting mode, and sends the normal picture image to multiple displays.

[0023] The SOC chip obtains a current power-on working state of the FPGA chip in the image cutting mode and a current DSI check result returned by the FPGA chip based on the normal picture image.

[0024] If the SOC chip determines that the current power-on working state of the FPGA chip is an abnormal state or the current DSI check result corresponds to a check failure result, the SOC chip returns to perform the initialization step of the DPI interface and the DSI interface of the SOC chip.

[0025] In a third aspect, an FPGA link driving device based on a state machine is provided, which is run in an SOC chip of an in-vehicle infotainment display system, the in-vehicle infotainment display system further includes an FPGA chip, and the SOC chip is connected with the FPGA chip; the FPGA link driving device executes the FPGA link driving method based on the state machine in the first aspect.

[0026] In a fourth aspect, an FPGA link driving system based on a state machine is provided, which is run in an in-vehicle infotainment display system, the in-vehicle infotainment display system includes an SOC chip and an FPGA chip, and the SOC chip is connected with the FPGA chip; the FPGA link driving system executes the FPGA link driving method based on the state machine in the second aspect.

[0027] In a fifth aspect, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor executes the computer program to implement the FPGA link driving method based on the state machine in the first aspect or the FPGA link driving method based on the state machine in the second aspect.

[0028] In a sixth aspect, the embodiments of the present application further provide a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program, when executed by a processor, causes the processor to perform the state machine based FPGA link driving method in the first aspect or the state machine based FPGA link driving method in the second aspect.

[0029] The embodiments of the present application provide a state machine based FPGA link driving method, device, system, computer device and storage medium. The method is applied to a SOC chip in a car machine display system. The car machine display system further comprises an FPGA chip, and the SOC chip is connected with the FPGA chip. The method comprises the following steps: initializing a DPI interface and a DSI interface of the SOC chip; if it is detected that the initialization of the DPI interface and the DSI interface is completed, controlling the FPGA chip to enter an image checking mode, and outputting a preset checking image to the FPGA chip through the DPI interface and the DSI interface; controlling the FPGA chip to be powered on and run; detecting a power-on working state of the FPGA chip; if it is determined that the power-on working state of the FPGA chip is a normal state, receiving a DPI checking result and a DSI checking result returned by the FPGA chip based on the checking image; if it is determined that the DPI checking result and the DSI checking result both correspond to a checking pass result, controlling the FPGA chip to enter an image cutting mode, and acquiring a current power-on working state of the FPGA chip in the image cutting mode and a current DSI checking result returned by the FPGA chip based on the normal picture image; and if it is determined that the current power-on working state of the FPGA chip is an abnormal state or the current DSI checking result corresponds to a checking fail result, returning to the step of initializing the DPI interface and the DSI interface of the SOC chip. The FPGA chip is controlled by using the state machine mechanism, so that the control logic is more organized, the SOC chip can judge whether the display link is normal through the signal returned by the FPGA chip, the demand of multi-screen display is met, and the screen of the car machine can be self-recovered in the case of display abnormality. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0031] Figure 1 The application scenario diagram of the state machine based FPGA link driving method provided by the embodiments of the present application is shown in the figure.

[0032] Figure 2A flowchart illustrating the FPGA link driving method based on a state machine provided in an embodiment of the present invention;

[0033] Figure 3 Another flowchart illustrating the FPGA link driving method based on a state machine provided in this embodiment of the invention;

[0034] Figure 4 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0037] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0038] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram illustrating an application scenario of the FPGA link-driven method based on a state machine provided in an embodiment of the present invention. Figure 2 This is a flowchart illustrating the FPGA link driving method based on a state machine provided in an embodiment of the present invention. The FPGA link driving method based on a state machine is applied to a SOC chip in an in-vehicle display system, wherein the in-vehicle display system further includes an FPGA chip, and the SOC chip is connected to the FPGA chip.

[0040] See Figure 1The vehicle infotainment system also includes multiple displays (such as the first, second, and third displays shown in the diagram). The SOC chip is connected to the FPGA chip, and each display is connected to the FPGA chip. The SOC chip supports two outputs: a DPI interface (Display Pixel Interface) and a DSI interface (Display Serial Interface). The SOC chip transmits image data to the FPGA chip via both interfaces. The FPGA chip receives the image data, segments it, and then transmits the segmented image data to the corresponding displays. For example, to achieve a three-screen display in the vehicle infotainment system, the SOC chip transmits image data to the FPGA chip via both interfaces. The FPGA chip receives the image data output via the DSI interface, segments it into two screen images, and transmits them to the first and second displays respectively. The display pixel resolution of the SOC chip's DSI interface can be configured to 3840*720. The FPGA chip can segment the image as needed, such as dividing it into two 1920*720 images, thus extending the screen display. Additionally, image data output from the DPI interface can be processed in a similar way. However, in implementing a three-screen display, the FPGA chip does not segment the image output from the DPI interface and outputs it directly to the third display. Meanwhile, Figure 1 In this context, `Gpio_p` represents a signal on a GPIO port connecting the SOC chip and the FPGA chip, used to control the FPGA chip to enter image verification mode or image segmentation mode. `Rsv1`, `Rsv2`, and `Rsv3` are three signals returned through the GPIO port: `Rsv1` represents the periodic heartbeat packet returned by the FPGA chip, `Rsv2` represents the DPI verification result returned by the FPGA chip, and `Rsv3` represents the DSI verification result returned by the FPGA chip. The state machine-based FPGA link driving method provided in this embodiment includes multiple steps, which are divided into multiple states. A state machine can be used to control the flow of this method.

[0041] like Figure 2 As shown, the method includes steps S101 to S108.

[0042] S101. The DPI interface and DSI interface of the SOC chip are initialized.

[0043] In this embodiment, before the vehicle-mounted display system performs multi-screen display, the DPI and DSI interfaces of the SOC chip in the vehicle-mounted display system are initialized and wait for initialization to complete. This step S101 is designated as state 1 in the state machine mechanism. During the startup process of the vehicle-mounted display system or after waking from sleep, the system waits for the DPI and DSI interface drivers of the SOC chip to complete initialization to ensure that the display driver of the SOC chip is ready. Then, the system can switch to state 2.

[0044] S102. If the initialization of the DPI interface and the DSI interface is detected to be complete, the FPGA chip is controlled to enter the image verification mode, and the preset verification image is output to the FPGA chip through the DPI interface and the DSI interface.

[0045] In this embodiment, after the DPI and DSI interfaces of the SOC chip in the vehicle display system are initialized, if the initialization of the DPI and DSI interfaces is detected as complete, it indicates that the display driver of the SOC chip is ready. The SOC chip then controls the FPGA chip to enter the image verification mode. Then, the SOC chip outputs a preset verification image to the FPGA chip through the DPI and DSI interfaces. The FPGA chip receives this verification image, which is used to verify whether the display link is normal. Step S102 is considered state 2 in the state machine mechanism, and can switch to state 3 after the SOC chip outputs the verification image to the FPGA chip.

[0046] S103. Control the FPGA chip to power on and run.

[0047] In this embodiment, the SOC chip controls the FPGA chip to power on and run. This step S103 is considered state 3 in the state machine mechanism. The SOC chip controls the FPGA chip's power supply by directly controlling the power supply chip (not shown in the figure). Then, the FPGA chip powers on and automatically loads its own image from flash memory. After the FPGA chip initializes normally, it returns the FPGA chip's power-on operating state to the SOC chip.

[0048] S104. Detect the power-on working status of the FPGA chip.

[0049] In this embodiment, after the SOC chip controls the FPGA chip to power on and operate, the SOC chip detects the power-on operating state of the FPGA chip after a certain delay, and this step S104 is taken as state 4 in the state machine mechanism. The certain delay by the SOC chip is to ensure that the FPGA chip initializes normally. The SOC chip determines whether the FPGA chip is operating normally based on the detected power-on operating state of the FPGA chip. Specifically, the second GPIO port of the SOC chip is connected to the FPGA chip, and the signal on the second GPIO port of the SOC chip is... Figure 1 In Rsv1, the SOC chip receives the periodic heartbeat packets returned by the FPGA chip through the second GPIO port. Rsv1 represents the periodic heartbeat packets returned by the FPGA chip. If there is a normal 1HZ heartbeat in Rsv1, it indicates that the FPGA chip is in a normal power-on state and is running normally. If there is an abnormal 1HZ heartbeat in Rsv1, it indicates that the FPGA chip is in an abnormal power-on state and is not running normally.

[0050] In one embodiment, step S104 is followed by:

[0051] If it is determined that the power-on working state of the FPGA chip is abnormal, then return to step S101.

[0052] In this embodiment, if the SOC chip detects an abnormal 1Hz heartbeat in Rsv1 on the second GPIO port, it determines that the FPGA chip's power-on operating state is abnormal, indicating that the FPGA chip is not operating normally, causing an abnormal display link in the vehicle display system. At this time, the SOC chip returns to step S101, that is, the process switches back to state 1 and re-initializes, thereby ensuring that the FPGA chip can operate normally.

[0053] S105. If it is determined that the power-on working state of the FPGA chip is normal, then the DPI verification result and DSI verification result returned by the FPGA chip based on the verification image are received.

[0054] In this embodiment, if the SOC chip detects a normal 1Hz heartbeat in Rsv1 on the second GPIO port, it determines that the FPGA chip's power-on operating state is normal, indicating that the FPGA chip is operating normally. Then, after a certain delay, the FPGA chip verifies the verification image based on the image verification mode, obtaining DPI and DSI verification results based on the verification image. The SOC chip receives the DPI and DSI verification results returned by the FPGA chip based on the verification image to determine whether the SOC chip's DPI and DSI interface outputs can output image data normally. This allows the SOC chip to determine whether the display link of the vehicle display system is normal based on the signals returned by the FPGA chip. Specifically, the third and fourth GPIO ports of the SOC chip are connected to the FPGA chip, and the signal on the third GPIO port of the SOC chip is... Figure 1 In the SOC chip, Rsv2 represents the DPI verification result returned by the FPGA chip via the third GPIO port. A value of 1 for Rsv2 indicates a successful DPI verification, while a value of 0 indicates a failed DPI verification. The signal on the fourth GPIO port of the SOC chip is... Figure 1 In Rsv3, the SOC chip receives the DSI verification result returned by the FPGA chip through the fourth GPIO port. Rsv3 represents the DSI verification result returned by the FPGA chip, and Rsv3 is 1 to indicate that the DSI verification is successful, and Rsv3 is 0 to indicate that the DSI verification is unsuccessful.

[0055] In one embodiment, step S105 is followed by:

[0056] If the DPI verification result or the corresponding DSI verification result is determined to be a verification failure, then return to step S101.

[0057] In this embodiment, if the SOC chip detects that Rsv2 on the third GPIO port is 0, it indicates that the DPI verification has failed, thus determining that the DPI verification result corresponds to a verification failure result. If the SOC chip detects that Rsv3 on the fourth GPIO port is 0, it indicates that the DSI verification has failed, thus determining that the DSI verification result corresponds to a verification failure result. If the SOC chip determines that either the DPI verification result or the DSI verification result corresponds to a verification failure result, that is, if the SOC chip detects that Rsv2 is 0 or Rsv3 is 0, it returns to step S101, that is, the process switches back to state 1 and re-initializes, thereby ensuring that the DPI interface and DSI interface of the SOC chip can output normally.

[0058] S106. If it is determined that both the DPI verification result and the DSI verification result are valid, then the FPGA chip is controlled to enter the image cutting mode and output a normal image.

[0059] In this embodiment, step S106 is designated as state 5 in the state machine mechanism. If the SOC chip determines that both the DPI and DSI verification results correspond to successful verifications (i.e., the SOC chip detects Rsv2 as 1 and Rsv3 as 1), it controls the FPGA chip to enter the image segmentation mode. Then, the SOC chip begins outputting the normal image, transmitting it to the FPGA chip via the DPI and DSI interfaces. After receiving the normal image, the FPGA chip segments it according to the image segmentation mode and then transmits the segmented normal images to the corresponding displays for display. For example, see [reference needed]. Figure 1 When the vehicle display system is a three-screen display, the SOC chip transmits the normal image to the FPGA chip through the DPI interface and the DSI interface. After receiving the normal image output through the DSI interface, the FPGA chip cuts it into two screen images according to the preset cutting points, and transmits the two screen images to the first display and the second display respectively for display. The FPGA chip does not split the normal image output by the DPI interface, but directly outputs it to the third display for display.

[0060] S107. Obtain the current power-on working state of the FPGA chip in the image cutting mode and the current DSI verification result returned by the FPGA chip based on the normal screen image.

[0061] In this embodiment, step S107 is designated as state 6 in the state machine mechanism. After the FPGA chip enters the image segmentation mode and the SOC chip outputs a normal image, the SOC chip continuously monitors the current power-on operating state returned by the FPGA chip and the current DSI verification result returned by the FPGA chip based on the normal image. Specifically, the SOC chip continuously monitors Rsv1 and Rsv3 to determine whether the current display link is functioning correctly. During the display process of the vehicle-mounted display system, the DSI interface has its own verification function, enabling real-time verification. However, the DPI interface does not have its own verification function and therefore cannot perform real-time verification. Thus, the SOC chip detects the current display link's functionality by continuously monitoring the current power-on operating state returned by the FPGA chip and the current DSI verification result returned by the FPGA chip based on the normal image.

[0062] S108. If it is determined that the current power-on working state of the FPGA chip is an abnormal state or the current DSI verification result corresponds to a verification failure result, then return to step S101.

[0063] In this embodiment, if the SOC chip determines that the current power-on operating state of the FPGA chip is abnormal or the current DSI verification result corresponds to a verification failure, that is, the SOC chip detects an abnormal 1Hz heartbeat in Rsv1 or Rsv3 is 0, it returns to step S101, that is, the process switches back to state 1 and re-initializes. The SOC chip can determine whether the display link is normal through the signal returned by the FPGA chip. If an abnormality is detected in the display link (i.e., the vehicle screen displays abnormally), it returns to the initialization state to re-initialize. This ensures that the screen can display normally again, rather than remaining undisplayed after a problem occurs, thus providing a self-recovery mechanism.

[0064] In one embodiment, the first GPIO port of the SOC chip is connected to the FPGA chip, and controlling the FPGA chip to enter the image verification mode includes:

[0065] By controlling the first GPIO port to output a low level, the FPGA chip is controlled to enter the image verification mode.

[0066] The process of controlling the FPGA chip to enter the image slicing mode includes:

[0067] By controlling the first GPIO port to output a high level, the FPGA chip is controlled to enter the image cutting mode.

[0068] In this embodiment, refer to Figure 1 The SOC chip controls the FPGA chip to enter image verification mode or image segmentation mode through the first GPIO port. Specifically, the signal on the first GPIO port is... Figure 1 In the Gpio_p parameter, when the SOC chip pulls the first GPIO port low, the first GPIO port outputs a low level (i.e., Gpio_p is 0), and the FPGA chip enters image verification mode. When the SOC chip pulls the first GPIO port high, the first GPIO port outputs a high level (i.e., Gpio_p is 1), the FPGA chip enters image verification mode.

[0069] For in-vehicle infotainment systems, screen display is crucial. If one or more screens suddenly stop displaying, the driver might panic, fearing a serious technical problem and a potential safety hazard. Therefore, ensuring the screen display is functioning correctly is vital for drivers. This invention provides a state machine-based FPGA link driving method that utilizes a state machine mechanism to control the FPGA chip, making the control logic more structured. The SOC chip can determine the display link's functionality based on signals returned from the FPGA chip, satisfying the needs of multi-screen displays while also enabling self-recovery in the event of screen display anomalies.

[0070] This invention provides a state machine-based FPGA link driving method for use in vehicle infotainment systems, wherein the vehicle infotainment system includes a SOC chip and an FPGA chip, and the SOC chip is connected to the FPGA chip.

[0071] See Figure 1 The vehicle infotainment display system also includes multiple displays (such as the first, second, and third displays shown in the figure), each connected to an FPGA chip. The SOC chip supports dual outputs via DPI and DSI interfaces. The SOC chip transmits image data to the FPGA chip through both interfaces. Upon receiving the image data, the FPGA chip segments it and then transmits the segmented image data to the corresponding displays for display. For example, to achieve a three-screen display in the vehicle infotainment system, the SOC chip transmits image data to the FPGA chip through both DPI and DSI interfaces. The FPGA chip receives the image data output through the DSI interface, segments it into two screen images, and transmits them to the first and second displays respectively. The display pixel resolution of the SOC chip's DSI interface output can be configured to 3840*720. The FPGA chip can segment the image as needed, such as dividing it into two 1920*720 images, thus extending the screen. Alternatively, image data output through the DPI interface can be processed in a similar way, but in the three-screen display implementation, the FPGA chip does not segment the image output through the DPI interface and outputs it directly to the third display. Figure 1 In this context, Gpio_p represents a signal on a GPIO port connecting the SOC chip and the FPGA chip, used to control the FPGA chip to enter image verification mode or image segmentation mode; Rsv1, Rsv2, and Rsv3 are three signals returned through the GPIO port, where Rsv1 represents the periodic heartbeat packet returned by the FPGA chip, Rsv2 represents the DPI verification result returned by the FPGA chip, and Rsv3 represents the DSI verification result returned by the FPGA chip.

[0072] See Figure 3 ,Figure 3 This is another flowchart illustrating the FPGA link driving method based on a state machine provided in an embodiment of the present invention. The method includes steps S201 to S211.

[0073] S201. The DPI interface and DSI interface of the SOC chip are initialized.

[0074] In this embodiment, before the vehicle-mounted display system performs multi-screen display, the DPI and DSI interfaces of the SOC chip in the vehicle-mounted display system are initialized and wait for initialization to complete. This step S201 is designated as state 1 in the state machine mechanism. During the startup process of the vehicle-mounted display system or after waking from sleep, the system waits for the DPI and DSI interface drivers of the SOC chip to complete initialization to ensure that the display driver of the SOC chip is ready. Then, the system can switch to state 2.

[0075] S202. If the SOC chip detects that the initialization of the DPI interface and the DSI interface is complete, it controls the FPGA chip to enter the image verification mode and outputs the preset verification image to the FPGA chip through the DPI interface and the DSI interface.

[0076] S203, The FPGA chip receives the verification image.

[0077] In this embodiment, after the DPI and DSI interfaces of the SOC chip in the vehicle display system are initialized, if the initialization of the DPI and DSI interfaces is detected as complete, it indicates that the display driver of the SOC chip is ready. The SOC chip then controls the FPGA chip to enter the image verification mode. Then, the SOC chip outputs a preset verification image to the FPGA chip through the DPI and DSI interfaces. The FPGA chip receives this verification image, which is used to verify whether the display link is normal. Step S202 is considered state 2 in the state machine mechanism, and can switch to state 3 after the SOC chip outputs the verification image to the FPGA chip.

[0078] S204. The SOC chip controls the FPGA chip to power on and run.

[0079] S205, The FPGA chip powers on and returns to the power-on working state to the SOC chip.

[0080] In this embodiment, the SOC chip controls the FPGA chip to power on and operate. This step S204 is considered state 3 in the state machine mechanism. The SOC chip controls the FPGA chip's power supply by directly controlling the power supply chip (not shown in the figure). Then, the FPGA chip powers on and automatically loads its own image from flash memory. After the FPGA chip initializes normally, it returns the FPGA chip's power-on operating state to the SOC chip.

[0081] S206. The SOC chip detects the power-on working status of the FPGA chip.

[0082] In this embodiment, after the SOC chip controls the FPGA chip to power on and operate, the SOC chip detects the power-on operating state of the FPGA chip after a certain delay, and this step S206 is taken as state 4 in the state machine mechanism. The certain delay by the SOC chip is to ensure that the FPGA chip initializes normally. The SOC chip determines whether the FPGA chip is operating normally based on the detected power-on operating state of the FPGA chip. Specifically, the second GPIO port of the SOC chip is connected to the FPGA chip, and the signal on the second GPIO port of the SOC chip is... Figure 1 In Rsv1, the SOC chip receives the periodic heartbeat packets returned by the FPGA chip through the second GPIO port. Rsv1 represents the periodic heartbeat packets returned by the FPGA chip. If there is a normal 1HZ heartbeat in Rsv1, it indicates that the FPGA chip is in a normal power-on state and is running normally. If there is an abnormal 1HZ heartbeat in Rsv1, it indicates that the FPGA chip is in an abnormal power-on state and is not running normally.

[0083] In one embodiment, step S206 is followed by:

[0084] If the SOC chip determines that the power-on working state of the FPGA chip is abnormal, it returns to step S201.

[0085] In this embodiment, if the SOC chip detects an abnormal 1Hz heartbeat in Rsv1 on the second GPIO port, it determines that the FPGA chip's power-on operating state is abnormal, indicating that the FPGA chip is not running normally, causing an abnormal display link in the vehicle display system. At this time, the SOC chip returns to step S201, that is, the process switches back to state 1 and re-initializes, thereby ensuring that the FPGA chip can run normally.

[0086] S207. If the SOC chip determines that the FPGA chip is in a normal power-on state, it receives the DPI verification result and DSI verification result returned by the FPGA chip based on the verification image.

[0087] In this embodiment, if the SOC chip detects a normal 1Hz heartbeat in Rsv1 on the second GPIO port, it determines that the FPGA chip's power-on operating state is normal, indicating that the FPGA chip is operating normally. Then, after a certain delay, the FPGA chip verifies the verification image based on the image verification mode, obtaining DPI and DSI verification results based on the verification image. The SOC chip receives the DPI and DSI verification results returned by the FPGA chip based on the verification image to determine whether the SOC chip's DPI and DSI interface outputs can output image data normally. This allows the SOC chip to determine whether the display link of the vehicle display system is normal based on the signals returned by the FPGA chip. Specifically, the third and fourth GPIO ports of the SOC chip are connected to the FPGA chip, and the signal on the third GPIO port of the SOC chip is... Figure 1 In the SOC chip, Rsv2 represents the DPI verification result returned by the FPGA chip via the third GPIO port. A value of 1 for Rsv2 indicates a successful DPI verification, while a value of 0 indicates a failed DPI verification. The signal on the fourth GPIO port of the SOC chip is... Figure 1 In Rsv3, the SOC chip receives the DSI verification result returned by the FPGA chip through the fourth GPIO port. Rsv3 represents the DSI verification result returned by the FPGA chip, and Rsv3 is 1 to indicate that the DSI verification is successful, and Rsv3 is 0 to indicate that the DSI verification is unsuccessful.

[0088] In one embodiment, step S207 is followed by:

[0089] If the SOC chip determines that the DPI verification result or the corresponding DSI verification result is a verification failure, it returns to step S201.

[0090] In this embodiment, if the SOC chip detects that Rsv2 on the third GPIO port is 0, it indicates that the DPI verification has failed, thus determining that the DPI verification result corresponds to a verification failure result. If the SOC chip detects that Rsv3 on the fourth GPIO port is 0, it indicates that the DSI verification has failed, thus determining that the DSI verification result corresponds to a verification failure result. If the SOC chip determines that either the DPI verification result or the DSI verification result corresponds to a verification failure result, that is, if the SOC chip detects that Rsv2 is 0 or Rsv3 is 0, it returns to step S201, that is, the process switches back to state 1 and re-initializes, thereby ensuring that the DPI interface and DSI interface of the SOC chip can output normally.

[0091] S208. If the SOC chip determines that both the DPI verification result and the DSI verification result correspond to a verification pass result, it controls the FPGA chip to enter the image cutting mode and outputs a normal image.

[0092] S209. The FPGA chip receives the normal screen image, and cuts the normal screen image according to the image cutting mode and sends it to multiple displays.

[0093] In this embodiment, step S208 is designated as state 5 in the state machine mechanism. If the SOC chip determines that both the DPI and DSI verification results correspond to successful verifications (i.e., the SOC chip detects Rsv2 as 1 and Rsv3 as 1), it controls the FPGA chip to enter the image segmentation mode. Then, the SOC chip begins outputting the normal image, transmitting it to the FPGA chip via the DPI and DSI interfaces. After receiving the normal image, the FPGA chip segments it according to the image segmentation mode and then transmits the segmented normal images to the corresponding displays for display. For example, see [reference needed]. Figure 1 When the vehicle display system is a three-screen display, the SOC chip transmits the normal image to the FPGA chip through the DPI interface and the DSI interface. After receiving the normal image output through the DSI interface, the FPGA chip cuts it into two screen images according to the preset cutting points, and transmits the two screen images to the first display and the second display respectively for display. The FPGA chip does not split the normal image output by the DPI interface, but directly outputs it to the third display for display.

[0094] S210, the SOC chip acquires the current power-on working state of the FPGA chip in the image cutting mode and the current DSI verification result returned by the FPGA chip based on the normal image.

[0095] In this embodiment, step S210 is designated as state 6 in the state machine mechanism. After the FPGA chip enters the image segmentation mode and the SOC chip outputs a normal image, the SOC chip continuously monitors the current power-on operating state returned by the FPGA chip and the current DSI verification result returned by the FPGA chip based on the normal image. Specifically, the SOC chip continuously monitors Rsv1 and Rsv3 to determine whether the current display link is functioning correctly. During the display process of the vehicle-mounted display system, the DSI interface has its own verification function, enabling real-time verification. However, the DPI interface does not have its own verification function and therefore cannot perform real-time verification. Thus, the SOC chip detects the normality of the current display link by continuously monitoring the current power-on operating state returned by the FPGA chip and the current DSI verification result returned by the FPGA chip based on the normal image.

[0096] S211. If the SOC chip determines that the current power-on working state of the FPGA chip is an abnormal state or the current DSI verification result corresponds to a verification failure result, then it returns to the execution step S201.

[0097] In this embodiment, if the SOC chip determines that the current power-on operating state of the FPGA chip is abnormal or the current DSI verification result corresponds to a verification failure, that is, the SOC chip detects an abnormal 1Hz heartbeat in Rsv1 or Rsv3 is 0, it returns to step S201, that is, the process switches back to state 1 and re-initializes. The SOC chip can determine whether the display link is normal through the signal returned by the FPGA chip. If an abnormality is detected in the display link (i.e., the vehicle screen displays abnormally), it returns to the initialization state to re-initialize. This ensures that the screen can display normally again, rather than remaining undisplayed after a problem occurs, thus providing a self-recovery mechanism.

[0098] In one embodiment, the first GPIO port of the SOC chip is connected to the FPGA chip, and controlling the FPGA chip to enter the image verification mode includes:

[0099] By controlling the first GPIO port to output a low level, the FPGA chip is controlled to enter the image verification mode.

[0100] The process of controlling the FPGA chip to enter the image slicing mode includes:

[0101] By controlling the first GPIO port to output a high level, the FPGA chip is controlled to enter the image cutting mode.

[0102] In this embodiment, refer to Figure 1The SOC chip controls the FPGA chip to enter image verification mode or image segmentation mode through the first GPIO port. Specifically, the signal on the first GPIO port is... Figure 1 In the Gpio_p parameter, when the SOC chip pulls the first GPIO port low, the first GPIO port outputs a low level (i.e., Gpio_p is 0), and the FPGA chip enters image verification mode. When the SOC chip pulls the first GPIO port high, the first GPIO port outputs a high level (i.e., Gpio_p is 1), the FPGA chip enters image verification mode.

[0103] For in-vehicle infotainment systems, screen display is crucial. If one or more screens suddenly stop displaying, the driver might panic, fearing a serious technical problem and a potential safety hazard. Therefore, ensuring the screen display is functioning correctly is vital for drivers. This invention provides a state machine-based FPGA link driving method that utilizes a state machine mechanism to control the FPGA chip, making the control logic more structured. The SOC chip can determine the display link's functionality based on signals returned from the FPGA chip, satisfying the needs of multi-screen displays while also enabling self-recovery in the event of screen display anomalies.

[0104] This invention also provides a state machine-based FPGA link driver device, which runs on a SOC chip in an in-vehicle display system. The in-vehicle display system further includes an FPGA chip, and the SOC chip is connected to the FPGA chip. This state machine-based FPGA link driver device is used to execute any embodiment of the aforementioned state machine-based FPGA link driver method applied to the SOC chip in the in-vehicle display system.

[0105] This invention also provides a state machine-based FPGA link driving system running in an in-vehicle display system. The in-vehicle display system includes a SOC chip and an FPGA chip, with the SOC chip connected to the FPGA chip. This state machine-based FPGA link driving system is used to execute any of the aforementioned state machine-based FPGA link driving methods applied to the in-vehicle display system.

[0106] The aforementioned state machine-based FPGA link driver device and state machine-based FPGA link driver system can be implemented as a computer program, which can be used in, for example... Figure 4 It runs on the computer device shown. Please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic block diagram of a computer device provided in an embodiment of the present invention.

[0107] See Figure 4The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a device bus 501, wherein the memory may include a storage medium 503 and internal memory 504.

[0108] The storage medium 503 can store the operating device 5031 and the computer program 5032. When the computer program 5032 is executed, it causes the processor 502 to execute a state machine-based FPGA link driving method.

[0109] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0110] The internal memory 504 provides an environment for the execution of the computer program 5032 in the storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a state machine-based FPGA link driving method.

[0111] This network interface 505 is used for network communication, such as providing data transmission. Those skilled in the art will understand that... Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device 500 to which the present invention is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0112] The processor 502 is used to run a computer program 5032 stored in a memory to implement the FPGA link driving method based on a state machine disclosed in this embodiment of the invention.

[0113] Those skilled in the art will understand that Figure 4 The embodiments of the computer device shown do not constitute a limitation on the specific configuration of the computer device. In other embodiments, the computer device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. For example, in some embodiments, the computer device may include only memory and a processor. In such embodiments, the structure and function of the memory and processor are different from those shown. Figure 4 The embodiments shown are consistent and will not be described again here.

[0114] It should be understood that, in this embodiment of the invention, the processor 502 is an off-the-shelf field-programmable gate array (FPGA) or the like.

[0115] In another embodiment of the present invention, a computer-readable storage medium is provided. This computer-readable storage medium may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the state machine-based FPGA link driving method disclosed in the embodiments of the present invention.

[0116] Those skilled in the art will readily understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.

[0117] In the embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Units with the same function may be grouped into one unit. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, or may be electrical, mechanical, or other forms of connection.

[0118] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.

[0119] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0120] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a backend server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks.

[0121] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A state machine-based FPGA link driving method applied to an SOC chip in a car-machine display system, characterized in that, The car machine display system further comprises an FPGA chip, and the SOC chip is connected with the FPGA chip; the method comprises the following steps: the DPI interface and the DSI interface of the SOC chip are initialized; if it is detected that the initialization of the DPI interface and the DSI interface is completed, the FPGA chip is controlled to enter an image checking mode, and a preset checking image is output to the FPGA chip through the DPI interface and the DSI interface; the FPGA chip is controlled to be powered on and operated; the powered-on working state of the FPGA chip is detected; if it is determined that the powered-on working state of the FPGA chip is a normal state, the FPGA chip returns a DPI checking result and a DSI checking result based on the checking image are received; if it is determined that the DPI checking result and the DSI checking result both correspond to a checking pass result, the FPGA chip is controlled to enter an image cutting mode, and a normal picture image is output; the current powered-on working state of the FPGA chip in the image cutting mode and a current DSI checking result returned by the FPGA chip based on the normal picture image are acquired; if it is determined that the current powered-on working state of the FPGA chip is an abnormal state or the current DSI checking result corresponds to a checking failure result, the step of initializing the DPI interface and the DSI interface of the SOC chip is executed again.

2. The state machine based FPGA link driving method of claim 1, wherein, after the powered-on working state of the FPGA chip is detected, the following steps are further included: if it is determined that the powered-on working state of the FPGA chip is an abnormal state, the step of initializing the DPI interface and the DSI interface of the SOC chip is executed again.

3. The state machine based FPGA link driving method of claim 1, wherein, after it is determined that the powered-on working state of the FPGA chip is a normal state, the FPGA chip returns a DPI checking result and a DSI checking result based on the checking image are received, the following steps are further included: if it is determined that the DPI checking result or the DSI checking result corresponds to a checking failure result, the step of initializing the DPI interface and the DSI interface of the SOC chip is executed again.

4. The state machine based FPGA link driving method of claim 1, wherein, the first GPIO port of the SOC chip is connected with the FPGA chip, and the FPGA chip is controlled to enter the image checking mode, which comprises the following steps: the FPGA chip is controlled to enter the image checking mode by controlling the first GPIO port to output a low level; the FPGA chip is controlled to enter the image cutting mode, which comprises the following steps: the FPGA chip is controlled to enter the image cutting mode by controlling the first GPIO port to output a high level. 5.A state machine based FPGA link driving method applied to a car-machine display system, characterized in that, The car machine display system comprises an SOC chip and an FPGA chip, and the SOC chip is connected with the FPGA chip; the method comprises the following steps: the DPI interface and the DSI interface of the SOC chip are initialized; if it is detected that the initialization of the DPI interface and the DSI interface is completed, the FPGA chip is controlled to enter an image checking mode, and a preset checking image is output to the FPGA chip through the DPI interface and the DSI interface; the FPGA chip receives the checking image; The SOC chip controls the FPGA chip to run in power-on; The FPGA chip runs in power-on and returns a power-on working state to the SOC chip; The SOC chip detects the power-on working state of the FPGA chip; If the SOC chip determines that the power-on working state of the FPGA chip is a normal state, the SOC chip receives a DPI check result and a DSI check result returned by the FPGA chip based on the check image; If the SOC chip determines that the DPI check result and the DSI check result both correspond to a check pass result, the SOC chip controls the FPGA chip to enter an image cutting mode and outputs a normal picture image; The FPGA chip receives the normal picture image and cuts the normal picture image based on the image cutting mode and sends the normal picture image to multiple displays; The SOC chip acquires a current power-on working state of the FPGA chip in the image cutting mode and a current DSI check result returned by the FPGA chip based on the normal picture image; If the SOC chip determines that the current power-on working state of the FPGA chip is an abnormal state or the current DSI check result corresponds to a check failure result, the SOC chip returns to perform the initialization step of the DPI interface and the DSI interface of the SOC chip.

6. The state machine based FPGA link driving method of claim 5, wherein, After the SOC chip detects the power-on working state of the FPGA chip, the SOC chip further includes: If the SOC chip determines that the power-on working state of the FPGA chip is an abnormal state, the SOC chip returns to perform the initialization step of the DPI interface and the DSI interface of the SOC chip. 7.A state machine based FPGA link driver apparatus, running on a SOC chip in an in-vehicle infotainment display system, characterized in that, The car machine display system further includes an FPGA chip, and the SOC chip is connected with the FPGA chip; the FPGA link driving device executes the state machine-based FPGA link driving method according to any one of claims 1 to 4. 8.A state machine based FPGA link driving system running in an in-vehicle infotainment display system, characterized in that, The car machine display system includes an SOC chip and an FPGA chip, and the SOC chip is connected with the FPGA chip; the FPGA link driving system executes the state machine-based FPGA link driving method according to any one of claims 5 to 6.

9. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the state machine-based FPGA link driving method according to any one of claims 1 to 4, or the processor executes the computer program to implement the state machine-based FPGA link driving method according to any one of claims 5 to 6.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program causes the processor to execute the state machine-based FPGA link driving method according to any one of claims 1 to 4 when the computer program is executed by the processor, or the computer program causes the processor to execute the state machine-based FPGA link driving method according to any one of claims 5 to 6 when the computer program is executed by the processor.

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