Subscriber station for a serial bus system and method of communication in a serial bus system

Abstract

A subscriber station (10; 30) for a serial bus system (1) and a method for communicating in a serial bus system (1) are provided. The subscriber station (10; 30) has a communication control device (11; 31) for controlling a communication of the subscriber station (10; 20; 30) with at least one further subscriber station (10; 20; 30) of the bus system (1) and for generating a transmission signal (TxD) such that for messages (45) exchanged between subscriber stations (10, 20, 30) of the bus system (1) a bit time (t_bt1) of a signal transmitted onto the bus (40) in a first communication phase (451) can be distinguished from a bit time (t_bt2) of a signal transmitted in a second communication phase (452); wherein the communication control device (11; 31) is configured to generate the transmission signal (TxD) in accordance with a frame (450) and to insert a field (ADS) with a rising edge and a following falling edge into the frame (450) for a transition from the first communication phase (451) to the second communication phase (452); and wherein the field (ADS) has a predetermined length between the rising edge and the following falling edge such that between the rising edge and the following falling edge a sampling instant (t1) is arranged at which the communication control device (21; 31; 11) of the at least one further subscriber station (10; 20; 30) of the bus system (1) will sample a first bit (DH1) of the second communication phase (452).

Description

Technical Field

[0001] The present invention relates to a user station for a serial bus system and a method for communication in a serial bus system, the serial bus system operating with high data rates, high flexibility and high error robustness. Background Technology

[0002] Depending on the number of functions of the technical facilities or vehicle, (e.g., in a vehicle) the bus system used for communication between sensors and control devices should be able to transmit large amounts of data. This often requires faster data transmission from sender to receiver than has been the case so far, and the ability to transmit large data packets when needed.

[0003] In vehicles, the bus system is currently in the introduction phase, during which data is transmitted as messages in the standard ISO 11898-1:2015, which is the CAN protocol specification with CAN FD. These messages are transmitted between bus users of the bus system, such as sensors, control devices, generators, etc. For this purpose, messages are sent onto the bus in frames, within which transitions are made between two communication phases. In the first communication phase (arbitration), it is negotiated which user station in the bus system is permitted to send its frame onto the bus in the subsequent second communication phase (data phase, or transmission of useful data). CAN FD was initially used in vehicles by most manufacturers at an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s. Therefore, during transmission on the bus, switching back and forth between slow and fast operating modes is performed.

[0004] To achieve even higher data rates in the second communication phase, a successor bus system for CAN FD, called CAN XL, is being developed and is now standardized by the CAN in Automation (CiA) organization. In addition to pure data transmission via the CAN bus, CAN XL should also support additional functions such as functional safety, data security, and quality of service (QoS). These are essential characteristics required in autonomous vehicles.

[0005] CAN XL should support high bit rates during the data phase, such as up to 15 Mbit / s or even 20 Mbit / s. To achieve this, the corresponding transmit-receive devices (so-called CAN XL transceivers) are now being standardized. The operation of these transmit-receive devices can be modified to achieve the required high bit rates during the data phase. The bit rate during the arbitration phase is kept at approximately 500 kbit / s to enable arbitration. This results in CAN XL having to support a very high bit rate ratio. An conceivable example is a bit rate ratio of 40, which corresponds to 20 Mbit / s (high bit rate) in the data phase and 500 kbit / s (low bit rate) in the arbitration phase.

[0006] In CANXL, the communication control unit signals the transmitting and receiving units to change their operating mode. For this signaling, the communication control unit (especially its protocol controller) uses pulse width modulation (PWM) coding. This is particularly true for the CAN SIC XL transceiver.

[0007] The problem is that the PWM encoding in the communication control unit and the corresponding PWM decoding in the transmitter-receiver unit cause a time offset (delay).

[0008] Additionally, it should be noted that in CAN, the clock may have a certain tolerance.

[0009] An additional problem is that the three effects described (i.e., high bit rate ratio, PWM encoding / decoding, and clock tolerance) collectively cause large phase errors at user stations that are now merely receivers of messages transmitted via the bus. Such user stations can also be referred to as receiving nodes.

[0010] In the worst-case scenario, a "fast" receiving node attempts to sample the DH1 bit before the first bit of the data phase arrives at the receiving node, and / or a "slow" receiving node samples the DH1 bit only after it has already passed on the bus. In both cases, this results in invalid frames in the receiving node. This reduces the net data rate that can be transmitted in the bus system because some frames must be retransmitted.

[0011] This means that the phase error at the user station results in the inability to correctly convert bit rates from low bit rate to high bit rate in all cases within a CAN frame. However, reliable and robust communication is impossible without reliable bit rate conversion. Summary of the Invention

[0012] Therefore, the objective of this invention is to provide a user station for a serial bus system and a method for communication in a serial bus system, which solves the aforementioned problems. In particular, it aims to provide a user station for a serial bus system and a method for communication in a serial bus system, wherein high error robustness of communication can be achieved even at high data rates and with increased amounts of useful data per frame.

[0013] This task is solved by a user station for a serial bus system having the features of claim 1. The user station has a communication control device for controlling communication between the user station and at least one other user station in the bus system, such that the bit time of a signal transmitted to the bus in a first communication phase for a message exchanged between user stations in the bus system can be distinguished from the bit time of a signal transmitted in a second communication phase; and the user station has a transmit / receive device for transmitting a transmit signal to the bus of the bus system; wherein the communication control device is configured to generate a transmit signal based on a frame and insert a field with a rising edge and a subsequent falling edge into the frame for transitioning from the first communication phase to the second communication phase; and wherein the field has a predetermined length between the rising edge and the subsequent falling edge, such that a sampling time is arranged between the rising edge and the subsequent falling edge at which the communication control device of at least one other user station in the bus system samples the first bit of the second communication phase.

[0014] By constructing this user station, a modified ADS field is used to ensure that bit rate conversion from low bit rate to high bit rate can be performed correctly in all cases within a CAN frame. Specifically, even with high phase errors, the bit rate conversion during the transition from the first communication stage (arbitration stage) to the second communication stage (data stage) operates reliably. Furthermore, despite phase errors, the user station can still correctly sample the first bit of the second communication stage (data stage) and subsequently correctly sample the subsequent bits of the second communication stage (data stage).

[0015] Therefore, this user station enables reliable and robust communication with CAN XL. This applies even with extreme settings for bus system parameters, such as clock tolerance, PWM symbol length, bit timing settings, or other parameters.

[0016] Furthermore, it is advantageous that the described construction scheme for the user station used to solve the aforementioned tasks can be implemented effortlessly and thus at low cost.

[0017] Therefore, by utilizing this user station, it is possible in the bus system to maintain the arbitration known to CAN during the first communication phase, and even so, to significantly increase the transmission rate again compared to CAN or CAN FD.

[0018] If at least one CAN user station and / or at least one CAN FD user station also exist in the bus system, a method performed by the user station can also be adopted, wherein the at least one CAN user station and the at least one CAN FD user station send messages in accordance with the CAN protocol and / or the CAN FD protocol.

[0019] Other advantageous construction options for the user station are described in the dependent claims.

[0020] It is possible that a field of predetermined length has at least three bits with bit timing for a second communication phase.

[0021] A falling edge can define the start of a predetermined bit in the second communication phase. This edge can be configured for the communication control device of at least one additional user station in the bus system to synchronize with communication on the bus.

[0022] It is conceivable that the communication control device is configured to insert this field as a bit sequence with the logic value 1110.

[0023] In one configuration, the communication control device may be configured to insert, in this field, a bit having the bit time of a first communication phase and immediately thereafter a bit having the bit time of a second communication phase before the falling edge, wherein the communication control device is configured to, immediately following the bit having the bit time of the second communication phase, additionally insert M bits having the bit time of the second communication phase, each of the M bits having the same logic value 1 as the first bit of the second communication phase, and wherein M is a natural number greater than or equal to 1.

[0024] The communication control device can act as a receiving node in the second communication phase, such that the communication control device only acts as a receiver of frames on the bus, but does not act as a sender of frames on the bus. The communication control device is configured to allow N bits with the bit time of the second communication phase, starting from and including the sampling time when the communication control device samples the first bit of the second communication phase, and before the falling edge of the field. The N bits with the bit time of the second communication phase each have a logic value of 1, where N is a natural number greater than or equal to 1. The communication control device is configured to use the falling edge of the field to synchronize with the communication on the bus.

[0025] It is conceivable that the user station further has a transmitting / receiving device for sending transmission signals to the bus of the bus system, wherein the communication control device is configured to signal the transmitting / receiving device by means of pulse width modulation in the transmitted signal, requiring the transmitting / receiving device to switch its operating mode. In this case, the communication control device can be configured to signal the transmitting / receiving device directly after the rising edge of the field by means of pulse width modulation in the transmitted signal, requiring the transmitting / receiving device to switch its operating mode from the operating mode of the first communication stage to a different operating mode of the second communication stage.

[0026] In one implementation, the communication control unit uses S consecutive PWM symbols in the transmitted signal to signal the transmitting / receiving unit which operating mode of the second communication stage it must switch to, where S is a natural number greater than or equal to 1.

[0027] According to one embodiment, the communication control device is configured to transmit at least the last portion of bits having a first communication phase bit time, the last portion having the same logical value as the first bit of a field having a second communication phase bit time.

[0028] According to another embodiment, the transmitting / receiving device is configured to transmit the entire frame onto the bus in an operation mode for transmitting and receiving frames during a first communication phase.

[0029] It is possible to establish frames for message formation in CAN FD compatibility, where, in the first communication phase, it is negotiated which user station in the bus system will obtain at least temporarily exclusive, conflict-free access to the bus in the subsequent second communication phase.

[0030] The user station described above can be part of a bus system that further includes a bus and at least two user stations interconnected via the bus, enabling the at least two user stations to communicate serially with each other. In this case, at least one of the at least two user stations is the user station described above.

[0031] Furthermore, the aforementioned task is solved by a method for communication in a serial bus system according to claim 14. This method is implemented using a user station of the bus system, the user station having a communication control device and a transmitting / receiving device, wherein the method comprises the steps of: using the communication control device to control communication between the user station and at least one other user station of the bus system, such that the bit time of a signal transmitted to the bus in a first communication phase for a message exchanged between the user stations of the bus system can be distinguished from the bit time of a signal transmitted in a second communication phase; and using the transmitting / receiving device to transmit a transmission signal to the bus of the bus system, wherein the communication control device generates the transmission signal according to a frame and inserts a field having a rising edge and a subsequent falling edge into the frame for transition from the first communication phase to the second communication phase; and wherein the field has a predetermined length between the rising edge and the subsequent falling edge, such that a sampling time is arranged between the rising edge and the subsequent falling edge at which the communication control device of at least one other user station of the bus system samples the first bit of the second communication phase.

[0032] This method offers the same advantages as those mentioned earlier regarding the user site.

[0033] Other possible embodiments of the invention also include combinations of features or embodiments not explicitly mentioned in the foregoing or hereinafter related to these embodiments. Those skilled in the art will also add individual aspects as improvements or supplements to the corresponding basic forms of the invention. Attached Figure Description

[0034] The invention will then be described in more detail with reference to the accompanying drawings and embodiments. In the drawings:

[0035] Figure 1 A simplified block diagram of the bus system according to the first embodiment is shown;

[0036] Figure 2 A diagram is shown to illustrate the structure of a message that can be sent by a user station of a bus system according to a first embodiment;

[0037] Figure 3 A simplified schematic block diagram of a user station of a bus system according to a first embodiment is shown.

[0038] Figure 4 The time variation process of bus signals CAN-XL H and CAN-XLL in a user station according to the first embodiment is shown;

[0039] Figure 5The time variation of the differential voltage VDIFF of bus signals CAN-XL H and CAN-XL L in a user station according to the first embodiment is shown.

[0040] Figures 6 to 8 The time change process of the following signals is shown respectively: If the user station according to the first embodiment is the sender of the message, the signal appears when the frame is sent at the terminal of the user station, and the operation mode of the sending / receiving device is switched when the message is sent;

[0041] Figure 9 The following illustrates the time-varying process of the signal state: if another user station is the sender of the message and therefore generates a signal based on... Figures 6 to 8 If a signal is received, the receiving node anticipates the signal state at its receiving terminal.

[0042] Figure 10 and Figure 11 The time variation process of the following signals is shown respectively: If the user station according to the second embodiment is the sender of the message, the signal appears when the frame is transmitted at the terminal of the user station, and no switching of the operation mode of the transmitting / receiving device is performed when the message is transmitted; and

[0043] Figure 12 The following illustrates the time-varying process of the signal state: if another user station is the sender of the message and therefore generates a signal based on... Figure 10 and Figure 11 If a signal is received, the receiving node anticipates the signal state at its receiving terminal.

[0044] In these accompanying drawings, unless otherwise specified, the same or functionally equivalent elements are equipped with the same reference numerals. Detailed Implementation

[0045] As an example Figure 1 Bus system 1 is shown, which is specifically designed for CAN bus systems, CANFD bus systems, CAN XL bus systems and / or their modifications, as described below. Bus system 1 can be used in vehicles, especially motor vehicles, aircraft, etc., or in hospitals, etc.

[0046] exist Figure 1In the bus system 1, there are multiple user stations 10, 20, and 30, which are respectively connected to a bus 40. The bus 40 has a first main cable core 41 and a second main cable core 42. The main cable cores 41 and 42 can also be referred to as CAN H and CAN L, or CAN-XL H and CAN-XL L, and are used for electrical signal transmission after coupling a dominant level or generating a recessive level or other level for a signal in the transmitting state. Messages 45 and 46 can be transmitted serially between the user stations 10, 20, and 30 in the form of signals via the bus 40. If an error occurs in the communication on the bus 40, such as... Figure 1 As shown by the zigzag black thick arrow (Blockpfeil), error frame 47 (Error Flag) can optionally be sent. User stations 10, 20, and 30 are, for example, vehicle control equipment, sensors, display devices, etc.

[0047] As in Figure 1 As shown, user station 10 has a communication control device 11, a transmitting / receiving device 12, and a phase error compensation module 15. User station 20 has a communication control device 21, a transmitting / receiving device 22, and optionally a phase error compensation module 25. User station 30 has a communication control device 31, a transmitting / receiving device 32, and a phase error compensation module 35. The transmitting / receiving devices 12, 22, and 32 of user stations 10, 20, and 30 are directly connected to bus 40, even though this... Figure 1 This is also true even if it is not explicitly stated in the text.

[0048] Communication control devices 11, 21, and 31 are respectively used to control the communication between the corresponding user stations 10, 20, and 30 and at least one other user station among the user stations 10, 20, and 30 connected to the bus 40 via the bus 40.

[0049] Communication control devices 11 and 31 create and read a first message 45, which is, for example, a modified CAN message 45. In this case, the modified CAN message 45 is built based on the CAN XL format, which is related to... Figure 2To describe in more detail, appropriate phase error compensation modules 15 and 35 are employed in the case of the CAN XL format. Furthermore, communication control devices 11 and 31 can be implemented to provide CAN XL messages 45 or CAN FD messages 46 to, or receive CAN XL messages 45 or CAN FD messages 46 from, the transmitting / receiving device 32, as needed. In this case, appropriate phase error compensation modules 15 and 35 are also employed. Communication control devices 11 and 31 thus create and read the first message 45 or the second message 46, wherein the first message 45 and the second message 46 are distinguished by their data transmission standard, i.e., in this case, by CAN XL or CAN FD.

[0050] The communication control device 21 can be implemented as a conventional CAN controller according to ISO 11898-1:2015, that is, as a classic CAN controller or CAN FD controller that allows CAN FD. Additionally, a phase error compensation module 25 may optionally be present, which has the same function as phase error compensation modules 15 and 35. The communication control device 21 creates and reads a second message 46, such as a CAN FD message 46. In the case of the CAN FD message 46, it may include 0 to 64 data bytes, which are transmitted at a significantly faster data rate than in the case of classic CAN messages. In particular, the communication control device 21 is implemented as a conventional CAN FD controller.

[0051] The transmitting / receiving device 22 can be implemented as a conventional CAN transceiver according to ISO 11898-1:2015 or as a CANFD transceiver. The transmitting / receiving devices 12 and 32 can be implemented to provide messages 45 in CAN XL format or messages 46 in the current CAN FD format to the corresponding communication control devices 11 and 31 as needed, or to receive messages 45 in CAN XL format or messages 46 in the current CAN FD format from the corresponding communication control devices 11 and 31.

[0052] Using two user stations 10 and 30, it is possible to form and transmit messages 45 in CAN XL format, and to receive such messages 45.

[0053] Figure 2Message 45 shows a CAN XL frame 450, as provided by the communication control unit 11 to the transmitting / receiving unit 12 for transmission onto the bus 40. In this embodiment, the communication control unit 11 creates frame 450 to be compatible with CAN FD, as also... Figure 2 As explained in the document. The same applies similarly to the communication control device 31 and the transmitting / receiving device 32 of the user station 30.

[0054] according to Figure 2 The CAN XL frame 450 divides CAN communication on bus 40 into different communication phases 451 and 452, namely, an arbitration phase 451 and a data phase 452. Following the start bit (SOF), frame 450 has an arbitration field 453, a control field 454 with an ADS field for transitioning between communication phases 451 and 452, a data field 455, a checksum field 456, and a frame end field 457, in which the ADS field for transitioning between communication phases 452 and 451 is present. This is followed by the frame end field EOF.

[0055] In arbitration phase 451, user stations 10, 20, and 30 negotiate bit-by-bit using identifiers (IDs) with bits ID28 to ID18 in the arbitration field 453, determining which user station 10, 20, or 30 wants to send messages 45 and 46 with the highest priority, and thus obtains exclusive access to bus 40 of bus system 1 in the subsequent data phase 452 for transmission. In arbitration phase 451, the physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the bit transport layer or Layer 1 of the known OSI model (Open Systems Interconnection Model 1).

[0056] During phase 451, an important point is the use of the known CSMA / CR method, which allows user stations 10, 20, and 30 to simultaneously access bus 40 without disrupting messages 45 and 46, which are determined to have higher priority. This allows for the relatively simple addition of other bus user stations 10, 20, and 30 to bus system 1, which is highly advantageous.

[0057] The consequence of the CSMA / CR method is that a so-called recessive state must exist on bus 40, which can be rewritten on bus 40 by other user stations 10, 20, and 30 using a dominant state. In the recessive state, a high-resistance condition dominates on each user station 10, 20, and 30, which, combined with the parasitic nature of bus wiring, results in a longer time constant. This limits the maximum bit rate of the current CANFD physical layer to approximately 2 megabits per second in real-world vehicle use.

[0058] In data phase 452, in addition to the portion of control field 454, useful data consisting of data field 455 of CAN-XL frame or message 45 is transmitted, along with checksum field 456. This is followed by DAS field, which is used to transition from data phase 452 back to data phase 451.

[0059] The sender of message 45 only begins to send bits of data stage 452 onto bus 40 when user station 10 as the sender has won the arbitration and thus has exclusive access to bus 40 of bus system 1 for sending.

[0060] Generally speaking, compared to CAN or CAN FD, the following deviations can be achieved in a bus system with CAN XL:

[0061] a) Take over and, where necessary, adapt proven features responsible for the robustness and user-friendliness of CAN and CAN FD, especially frame structures with identifiers and arbitration according to the CSMA / CR method.

[0062] b) Increase the net data transfer rate, especially to approximately 10 megabits per second.

[0063] c) Increase the size of useful data per frame, especially to about 2KB or any other value.

[0064] As in Figure 2 As shown, in the arbitration phase 451, which is the first communication phase, user station 10 uses the CAN / CAN-FD format known according to ISO 11898-1:2015, in part, and especially up to the FDF bit (including the FDF bit). From the FDF bit onwards, user station 10 uses the CAN XL format, which will be described later, in the first communication phase and in the second communication phase (data phase 452).

[0065] In this embodiment, CANXL and CANFD are compatible. In this case, the res bit (hereinafter referred to as the XLF bit) known in CANFD is used for conversion from CAN FD format to CAN XL format. Therefore, the frame formats of CAN FD and CAN XL are the same up to the res bit or XLF bit. The receiver identifies the format in which frame 450 is transmitted only at the res bit. CANXL user stations (i.e., user stations 10 and 30 here) also support CAN FD.

[0066] Alternative selection in Figure 2 The frame 450 shown uses 11-bit identifiers ID28 to ID18. Optionally, a CAN XL extended frame format is possible, in which a 29-bit identifier is used. This is identical up to the FDF bit to the known CAN FD extended frame format from ISO 11898-1:2015.

[0067] according to Figure 2 From the SOF bit to the FDF bit and including the FDF bit, frame 450 is identical to the CAN FD Basic Frame Format according to ISO 11898-1:2015. Therefore, the known structure will not be further elaborated here. Figure 2 The bit shown in bold on its lower line is transmitted as dominant or '0' in frame 450. Figure 2 The bit shown in bold on its upper line is transmitted as recessive or '1' in frame 450. In CAN XL data phase 452, symmetrical '1' and '0' levels are used instead of recessive and dominant levels.

[0068] Generally, two different stuffing rules are applied when generating frame 450. Up to the FDF bit in the arbitration field 453, the dynamic bit stuffing rule of CANFD is applied, resulting in the insertion of inverted stuffing bits consecutively after five identical bits. In the data phase 452 up to the FCP field, a fixed stuffing rule is applied, resulting in the insertion of fixed stuffing bits after a fixed number of bits. Alternatively, instead of inserting only one stuffing bit, two or more bits can be inserted as fixed stuffing bits.

[0069] In frame 450, the XLF bit follows directly after the FDF bit. The XLF bit corresponds in position to the "res bit" of the CANFD basic frame format, as mentioned earlier. If the XLF bit is transmitted as 1 (i.e., recessive), the XLF bit thus identifies frame 450 as a CANXL frame. For CAN FD frames, the communication control device 11 sets the XLF bit to 0 (i.e., dominant).

[0070] In frame 450, the resXL bit follows the XLF bit. The resXL bit is the dominant bit for future use. For frame 450, resXL must be transmitted as 0 (i.e., dominant). However, if user station 10 receives the resXL bit as 1 (i.e., recessive), the receiving user station 10, for example, enters a Protocol Exception State, as implemented in CAN FD message 46 for res=1. Alternatively, the resXL bit may be defined exactly the opposite, i.e., the resXL bit must be transmitted as 1 (i.e., recessive). In this case, the receiving user station enters a Protocol Exception State with the dominant resXL bit.

[0071] In frame 450, the sequence ADS (Arbitration Data Switch) follows the resXL bit, in which a predetermined bit sequence is encoded. This bit sequence allows for a simple and secure transition from the bit rate (arbitration bit rate) of arbitration phase 451 to the bit rate (data bit rate) of data phase 452. Optionally, the physical layer is switched within the ADS field in the transmitting / receiving devices 12, 22, and 32. In this case, the operating mode of the transmitting-receiving devices 12 and 32 is also switched during the ADS sequence. The bit sequence of the ADS field has an AL1 bit, which is transmitted as a logic 1 at least in its last portion (e.g., the last 50% of the bits). The AL1 bit is the last bit of arbitration phase 451. The following three bits DH1, DH2, and DL1 have already been transmitted at the data bit rate. Therefore, bits DH1, DH2, and DL1 are the shortest bits in time in data phase 452 in CANXL. Bits DH1 and DH2 each have a logic value of 1. The last bit is bit DL1, which has a logic value of 0. After the bit rate conversion, the receiving node synchronizes with the falling edge of bit DL1. The ADS field is used to transition from the first communication phase 451 to the second communication phase 452.

[0072] In frame 450, the sequence ADS is followed by an SDT field, which indicates the contents of data field 455. The contents of the SDT field describe what type of information is contained in data field 455. For example, the SDT field indicates whether an "Internet Protocol" (IP) frame, a tunneled Ethernet frame, or another type of frame is present in data field 455.

[0073] Following the SDT field is the SEC field, which specifies whether the CAN security protocol is used to secure frame 450. The SEC field is 1 bit wide and, like the SDT field, must specify the type of information contained in data field 455.

[0074] The DLC field follows the SEC field, and a Data Length Code (DLC = Data Length Code) is inserted in the DLC field. This Data Length Code indicates the number of data bytes in data field 455 of frame 450. The Data Length Code (DLC) can take any value from 1 up to the maximum number of bytes in data field 455 or any data field length. If the maximum data field length is, in particular, 2048 bits, then assuming DLC ​​= 0 means a data field length of 1 byte and DLC = 2047 means a data field length of 2048 bytes, the Data Length Code (DLC) requires 11 bits. Alternatively, a data field 455 of length 0 might be allowed, as in, for example, CAN. In this case, DLC = 0 might, for example, encode a data field length of 0 bytes. Then, the maximum encodeable data field length, for example, in the case of 11 bits, is (2... 11 )-1=2047.

[0075] In frame 450, the DLC field is followed by the SBC bit count field (Stuff-Bit-Count). This field indicates the number of dynamic padding bits that have been sent in the arbitration field 453. The receiving node uses the information in the SBC bit count field to check whether it has received the correct number of dynamic padding bits.

[0076] Following the SBC bit count field is the Preface Checksum PCRC, also known as the Preface-CRC. The Preface Checksum PCRC is a checksum used to ensure the frame format of Frame 450; that is, it is the checksum of all variable bits from the SOF bits of Frame 450 up to the beginning of the Preface Checksum PCRC (including all dynamic padding bits and optionally fixed padding bits up to the beginning of the Preface Checksum PCRC). The length of the Preface Checksum PCRC based on Cyclic Redundancy Check (CRC) and the length of the resulting checksum polynomial are selected according to the desired Hamming distance.

[0077] In frame 450, the VCID (Virtual CAN Bus ID) field follows the preamble checksum and PCRC. The VCID field is 1 byte long and contains the number of the virtual CAN bus.

[0078] In frame 450, the VCID field is followed by the AF field (Acceptance Field). The AF field is 32 bits long. The AF field contains the address or another value used for acceptance filtering.

[0079] In frame 450, the AF field is followed by the data field 455. The data field 455 consists of P bytes B, where P is encoded in the DLC field as described above. P is a natural number greater than or equal to 1.

[0080] In frame 450, a checksum field 456 follows the data field 455, containing both a frame checksum (FCRC) and an FCP field. The FCRC is composed of FCRC bits. The length of the FCRC and the resulting CRC polynomial is selected based on the desired Hamming distance. The FCRC ensures the security of the entire frame 450. Alternatively, only the data field 455 may optionally be secured using the FCRC.

[0081] In frame 450, the Frame Check and FCRC are followed by the FCP field, where FCP stands for Frame Check Pattern. The FCP field consists of four bits, specifically bit sequence 1100. The receiving node uses the FCP field to check whether it is synchronized with the transmitted data stream. Furthermore, the receiving node synchronizes with the falling edge of the FCP field.

[0082] Following the FCP field is the End of Frame field 457. The End of Frame field 457 consists of two fields: a DAS field and an acknowledgment field or ACK field with at least one ACK bit and one ACK-Dlm bit.

[0083] The DAS field contains a sequence DAS (Data Arbitration Switch) in which a predetermined bit sequence is encoded. Bit sequences DAH, AH1, and AL2 allow for a simple and secure transition from the data bit rate of data phase 452 to the arbitration bit rate of arbitration phase 451. Furthermore, during the DAS field, the operating mode of the transmitting / receiving devices 12 and 32 is switched, optionally from operating mode FAST to operating mode SLOW. Figure 2 In the DAS field, bits DAH, AH1, AL2, and AH2 are present. Optionally, bit AH2 is set at the end of the DAS field. Bit AH2 is used to maintain the interval from the acknowledgment (ACK) field. The DAS field has at least three bits. For example, the bit sequence of the DAS sequence has an arbitration bit DAH and an arbitration bit AH1, both of which have a logic value of 1. Within bit DAH, the physical layer (i.e., the operating mode of the transmit / receive devices 12 and 32) is transitioned from FAST_TX or FAST_RX to SLOW. Following bit AH1 are bits AL2 (logic 0) and AH2 (logic 1). The two bits DAH and AH1 are used to ensure that there is sufficient time for the operating mode transition of transmit / receive device 11, and that all user stations 10 and 30 see a recessive level for more than one arbitration bit duration before the edge of bit AL2 (logic 0) at its beginning. This ensures the secure synchronization of the following user stations in the bus system: these user stations are now reintegrated into communication on the bus.

[0084] In the End of Frame field 457, an Acknowledgment (ACK) field follows the sequence of DAS fields. The ACK field contains bits used to acknowledge or deny the successful reception of frame 450. Figure 2 In this example, an ACK bit and an ACK-dlm bit are provided. Optionally, a NACK bit and a NACK-dlm bit may also be present. If the receiving user station 10, 30 has correctly received frame 450, the receiving user station 10, 30 will send the ACK bit as an explicit transmission. The transmitting user station will send the ACK bit as a implicit transmission. Thus, the bits initially sent to bus 40 in frame 450 can be rewritten by the receiving user station 10, 30. The ACK-dlm bit is sent as a implicit bit to separate it from other fields. The NACK bit and NACK-dlm bit are used so that the receiving user station can signal incorrect reception of frame 450 on bus 40. These bits function as the ACK bit and ACK-dlm bit.

[0085] In frame 450, the End of Frame (EOF) field follows the End of Frame (EOF) field (457). The bit sequence of the EOF field is used to indicate the end of frame 450. The EOF field is responsible for sending 8 recessive bits at the end of frame 450. This is a bit sequence that cannot appear within frame 450. In this way, user stations 10, 20, and 30 can safely identify the end of frame 450.

[0086] The End-of-Flight (EOF) field has the following length: this length varies depending on whether a dominant or recessive bit has been seen in the ACK bit. If the sending user station has received the ACK bit as dominant, then the EOF field has 7 recessive bits. Otherwise, the EOF field has only 5 recessive bits.

[0087] In frame 450, after the End-of-Frame Field (EOF) is the Inter-Frame Space (IFS), which... Figure 2 Not shown in the diagram. The inter-frame spacing (IFS) is constructed as in CAN FD according to ISO 11898-1:2015.

[0088] Figure 3 The basic structure of user station 10 is shown below: User station 10 has a communication control device 11, a transmitting / receiving device 12, and a phase error compensation module 15, which is part of the communication control device 11. User station 30 is constructed in a similar manner, as shown in... Figure 3 As shown, however, it is arranged separately from the communication control device 31 and the transmitting / receiving device 32 according to Figure 1 The phase error compensation module 35. Therefore, user station 30 is not described separately.

[0089] according to Figure 3In addition to the communication control unit 11 and the transmitting / receiving unit 12, the user station 10 also has a microcontroller 13 with the communication control unit 11 and a system ASIC 16 (ASIC = Application-Specific Integrated Circuit). The system ASIC 16 can alternatively be a system base chip (SBC) that integrates multiple functions required for the electronic components of the user station 10. In addition to the transmitting / receiving unit 12, the system ASIC 16 includes a power supply unit 17 that supplies power to the transmitting / receiving unit 12. The power supply unit 17 typically supplies a 5V CAN_Supply voltage. However, depending on requirements, the power supply unit 17 can supply an additional voltage with a different value. Alternatively, the power supply unit 17 can be configured as a current source.

[0090] The phase error compensation module 15 has an insertion block 151 and a signaling block 152. The insertion block 151 inserts a predetermined ADS field 1510 into frame 450. Blocks 151 and 152 are described in more detail later.

[0091] Furthermore, the transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122. Even though the transmitting / receiving device 12 is referred to thereafter, it is also possible that the receiving module 122 is disposed in a separate device outside the transmitting module 121. The transmitting module 121 and the receiving module 122 can be constructed as in a conventional transmitting / receiving device 22. The transmitting module 121 may, in particular, have at least one operational amplifier and / or transistor. The receiving module 122 may, in particular, have at least one operational amplifier and / or transistor.

[0092] The transmitting / receiving device 12 is connected to bus 40, more specifically to the first main cable core 41 of bus 40 for CAN H or CAN-XL H and the second main cable core 42 of bus 40 for CAN L or CAN-XL L. The power supply device 17 for supplying electrical power, particularly voltage, to the first main cable core 41 and the second main cable core 42 is supplied with voltage via at least one terminal 43. Connection to ground or CANND is achieved via terminal 44. The first main cable core 41 and the second main cable core 42 are terminated using terminating resistors 49.

[0093] In the transmitting / receiving device 12, the first main cable core 41 and the second main cable core 42 are connected not only to the transmitting module 121, also referred to as the transmitter, but also to the receiving module 122, also referred to as the receiver, even if the connection is... Figure 3 For simplicity, this is also not shown.

[0094] When the bus system 1 is running, the transmitting module 121 converts the transmitting signal TXD or TxD of the communication control device 11 into corresponding signals CAN-XL H and CAN-XL L for the main cable cores 41 and 42, and sends these signals CAN-XL H and CAN-XL L to the bus 40 at the terminals for CAN H and CAN L.

[0095] Receiver module 122 from according to Figure 4 The received signals CAN-XL H and CAN-XL L, received by bus 40, form a received signal RXD or RxD, and then transfer this received signal RXD or RxD to the communication control device 11, such as in Figure 3 As shown in the diagram. Except in idle or standby mode, the transmitting / receiving device 12 always listens for data or messages 45, 46 transmitted on the bus 40 during normal operation using the receiving module 122, and more precisely, listens for data or messages 45, 46 transmitted on the bus 40 regardless of whether the transmitting / receiving device 12 is the sender of message 45.

[0096] according to Figure 4 For example, signals CAN-XL H and CAN-XLL have a dominant bus level 401 and a recessive bus level 402, at least during arbitration phase 451, as is known in CAN. On bus 40, constructed in... Figure 5 The differential signal VDIFF = CAN-XLH - CAN-XLL is shown in the arbitration phase 451. Each bit of the signal VDIFF, with a bit time tbt1, can be identified in arbitration phase 451 using a reception threshold Ta, for example, 0.7V. In the data phase 452, the bits of signals CAN-XLH and CAN-XLL are transmitted faster than in arbitration phase 451, i.e., with a shorter bit time tbt2. This is based on... Figures 6 to 9 To describe in more detail. Therefore, signals CAN-XL H and CAN-XL L differ from conventional signals CAN H and CAN L in data phase 452, at least in terms of their faster bit rate.

[0097] Figure 4 The order of states 401 and 402 for signals CAN-XL H and CAN-XLL. Figure 5 The resulting change in voltage VDIFF is only used to illustrate the function of user station 10. The order of data states for bus states 401 and 402 can be selected as needed.

[0098] In other words, if the transmitting module 121 switches to the first operating mode B 451 (SLOW), then the transmitting module 121 will... Figure 4 A first data state as bus state 402 and a second data state as bus state 401 are generated. The bus state 402 has different bus levels for the two main cable cores 41 and 42 of the bus line of bus 40, while the bus state 401 has the same bus level for the two main cable cores 41 and 42 of the bus line of bus 40.

[0099] Furthermore, for the time-varying process of signals CAN-XL H and CAN-XL L in the second operating mode B452TX (FAST TX) included in data phase 452, the transmitting module 121 transmits these bits to the bus 40 at a higher bit rate. In data phase 452, the CAN-XL H and CAN-XL L signals can be generated using a different physical layer than in CAN FD. Therefore, the bit rate in data phase 452 can be further increased compared to CAN FD. In data phase 452, the user station that is not the sender of frame 450 sets the third operating mode B452RX (FASTRX) in its transmitting / receiving device.

[0100] To signal a switch from operating mode B451 to operating mode B452TX (FASTTX) or operating mode B452RX (FAST RX), the communication control unit 11 performs pulse width modulation (PWM) on the transmit signal TxD. For this purpose, the communication control unit 11 uses one or more PWM symbols for each logic bit of the CAN XL frame 450. In principle, a PWM symbol consists of two phases, i.e., phase 0 and phase 1. Furthermore, the PWM symbol is limited by two identical edges, for example, by two rising edges.

[0101] If user station 10 acts as the sender of frame 450, then Figure 3 The phase error compensation module 15 (especially its insertion block 151) is used to insert the ADS field 1510 into frame 450. Furthermore, the phase error compensation module 15 (especially its signaling block 152) can perform pulse width modulation (PWM), as described later for the transition between operating modes B 451 (SLOW) and B 452TX (FAST_TX).

[0102] Figure 6The time t indicates the final digital transmission signal TxD obtained within the range of the transition from arbitration phase 451 to data phase 452 in frame 450 (in other words, during the transition from phase 451 to phase 452). In frame 450, the ADS field 1510 is inserted after bit resXL. This transmission signal TxD is serially transmitted to the transmitting / receiving device 12 by the communication control device 11, which is the sender of frame 450, as described in more detail later. Up to and including bit AL1, the bits of frame 450 have a bit duration t_bt1. From bit DH1 (the first bit of data phase 452), the bits of frame 450 have a bit duration t_bt2. Figure 6 In the example, the bit duration t_b2 is shorter than the bit duration t_bt1.

[0103] As in Figure 1 As shown in the figure, in this embodiment, the AL1 bit is sent with a logic value of 1.

[0104] Figure 7 The diagram illustrates the state generated by the transmitted signal TxD during time t, which appears serially at terminal TXD between the communication control device 11 and the transmitting / receiving device 12. The communication control device 11 (e.g., phase error compensation module 15, particularly signaling block 152) performs this in data phase 452. Figure 6 The transmitted signal TxD is pulse width modulated (PWM). More precisely, Figure 6 The pulse width modulation (PWM) of the transmitted signal TxD begins at bit AL1. During the arbitration phase 451 prior to bit AL1, no pulse width modulation (PWM) is performed on the transmitted signal TxD.

[0105] At the end of arbitration phase 451, the transmitting / receiving device 12 determines, based on the high frequency of the signal edge at the TXD terminal, whether it wants to switch from the arbitration phase operating mode B_451 to one of the fast operating modes B_452_TX (FAST_TX) or B_452_RX (FAST_RX), or remain there. The transmitting / receiving device 12 determines, based on the value of the first PWM symbol or the first S symbols, whether it wants to switch to operating mode B_452_TX (FAST_TX) or operating mode B_452_RX (FAST_RX). S is a natural number greater than or equal to 1. Due to the executed PWM encoding, the signal at terminal TXD is delayed relative to the TxD signal by a duration T_V1. Based on the operating mode to which the transmitting / receiving device is to be switched, and regardless of the value of the AL1 bit, signaling block 152 generates the first S PWM symbols.

[0106] exist Figure 7In the example above, with the PWM symbol SB_D0, 0 is longer than 1, which corresponds to the bit with logic 0 in data phase 452 in the transmit signal TxD. With the PWM symbol SB_D1, 1 is longer than 0, which corresponds to the bit with logic 1. Of course, the PWM symbols SB_D0 and SB_D1 can be defined differently, especially in the exact opposite way described above.

[0107] Furthermore, in Figure 7 In this example, the first two PWM symbols in the signal at terminal TXD have a logic value of 0 (SB_D0). Transmitter-receiver devices 12 and 32 evaluate these first two PWM symbols to determine which operating mode they need to switch to. Figure 7 In this example, the transmitting / receiving devices 12 and 32 of the transmitting node need to switch to operating mode B_452_TX (FAST_TX) based on two PWM symbols with a logic value of 0. The switch to operating mode B_452_RX (FAST_RX) is signaled by using at least one additional value of the first two PWM symbols in the AL1 bit.

[0108] As in Figure 7 As shown, the communication control device 11 (e.g., phase error compensation module 15, especially signaling block 152) performs... Figure 6 The pulse width modulation (PWM) immediately following the AL1 bit of the transmit signal TxD causes all subsequent PWM symbols of the AL1 bit to be transmitted with a logic value of 1. Therefore, only the symbol SB_D1 exists in the second part of the AL1 bit, which is the part after the signal notifies the transmit-receive devices 12, 32 of the operation mode B_452 for the data phase 452.

[0109] After data phase 452, pulse width modulation (PWM) of the transmit signal TxD ends because, as described above, PWM of the transmit signal TxD is not performed during arbitration phase 451. The PWM encoding is stopped, and therefore the transition from operating mode B_452_TX (FAST_TX) or operating mode B_452_RX (FAST_RX) to operating mode B_451 (SLOW) is signaled by the absence of multiple edges.

[0110] Figure 8 The following illustrates the time variation of the signal TxD_TC: This signal TxD_TC has been transmitted from the transmitting / receiving device 12... Figure 7 It is decoded in the state at terminal TXD. Figure 8In this example, the transmitting / receiving device 12 switches its operating mode B_451 to operating mode B_452_TX (FAST_TX) in bit AL1. In operating mode B_451, frame 450 has bits with a bit duration t_bt1, and in operating mode B_452_TX (FAST_TX), frame 450 has bits with a bit duration t_bt2. Furthermore, using a different physical layer than in operating mode B_452_TX (as described above), the bits of frame 450 can be transmitted to bus 40 in operating mode B_451.

[0111] The transmitting / receiving device 12 will therefore Figure 7 The state at terminal TXD is decoded according to Figure 8 The signal TxD_TC. For the AL1 bit, the logic value is 0 for the first part AL1_0. Figure 8 The second and last part of the AL1 bit, AL1_1, yields the logical value 1.

[0112] Each PWM symbol in SB_D0 and SB_D1 at terminal TXD can be decoded only at the end of the corresponding PWM symbol SB_D0 or SB_D1. Therefore, the decoding in the transmitting / receiving device 12 inserts an additional delay duration T_V2 into the signal TxD_TC to be serially transmitted onto bus 40. The delay duration T_V2 is equal to the duration of the symbol length of one of the PWM symbols SB_D0 and SB_D1, as shown in... Figure 8 As shown in the diagram, the phase error T_P generated in the user station during transmission due to PWM encoding and decoding is T_P = T_V1 + T_V2.

[0113] In the sending / terminating device 12 Figure 7 The state at terminal TXD has been decoded according to Figure 8 After the signal TxD_TC, the transmitting / receiving device 12 sends the signal TxD_TC as a differential voltage VDIFF to the bus 40.

[0114] Figure 9 The following variation of signal RxD_E is illustrated with respect to time t: The receiving user station (receiving node) (especially its communication control device) anticipates the signal RxD_E at its RXD terminal. In this case, the receiving user station (receiving node) (especially its communication control device) does not anticipate a predetermined value for bit AL1, as in... Figure 9As illustrated by the shaded line. In other words, the value of bit AL1 can be either logic 1 or logic 0. Furthermore, the receiving user station (receiving node) (especially its communication control device) samples bit DH1 at sampling time t1, that is, samples the first bit of data phase 452.

[0115] according to Figure 9 ,exist Figure 8 There is a large phase error T_P1 = T_V1 + T_V2 + "phase error due to clock tolerance" between the expected received signal RxD_E and the actual received signal. Figure 8 The signals TxD_TC are the same. T_P1 is... Figure 9 The start distance of DH1 bit in Figure 8 The starting interval of the DH1 bit in the code. In this case, however, it can be ignored and... Figures 6 to 9 The signal propagation time, especially the signal propagation time via bus 40, is not shown in the figure because the signal propagation time has no effect on the phase error T_P1.

[0116] Despite the large phase error T_P1, the receiving node correctly samples bit DH1 (i.e., the first bit of data phase 452) as logic 1. This is because bit AL1 has already been transmitted as logic 1 in its final part, AL1_1, as shown in... Figure 8 and Figure 9 As can be identified in the comparison.

[0117] Furthermore, starting from the DH1 bit position, the receiving node allows 1 to N bits of logic 1 to be sampled directly and sequentially. N is a natural number greater than or equal to 1. In other words, after receiving the DH1 bit as logic 1, if the receiving node samples the other zero to N-1 bits of logic 1 in the second communication phase 452 before detecting the falling edge in the ADS field, the receiving node allows it. For the bit rate ratio that is being strived to achieve in CAN XL (as described above regarding the task to be solved) and the expected phase error, a value of N = 5 is advantageous or meaningful.

[0118] The next falling edge after the DH1 bit signals the start of the DL1 bit to the receiving nodes. All receiving nodes synchronize to the next falling edge after the DH1 bit.

[0119] Therefore, as in Figures 6 to 9 As shown, Figure 3In this embodiment, the phase error compensation module 15 is configured such that the ADS field has an AL1 bit at its beginning, the AL1 bit being transmitted as a logic 1 at least in its last portion AL1_1, which may, for example, correspond to more than 50% of the AL1 bits. Based on the signaling in the first portion AL1_1 of the AL1 bits, the transmitting / receiving device 12 performs a mode transition from operating mode B_451 (SLOW) to operating mode B_452_TX (FAST_TX).

[0120] As a result, the ADS field is constructed to ensure that not only the first bit DH1 of the data phase 452 can be correctly sampled, but also that synchronization is implemented between the sending and receiving nodes so that all bits of the data phase starting from the DL1 bit can be correctly sampled.

[0121] Figures 10 to 12 A time-varying process according to a second embodiment is shown, which differs from the following aspects. Figures 6 to 10 The process of change over time.

[0122] Unlike the first embodiment, the second embodiment does not perform a mode switching between the transmitting and receiving devices 12 and 32. This is particularly applicable to the transitions between communication phases 451 and 452. Therefore, in Figure 10 The transmitted signal TxD is not pulse width modulation (PWM) used to encode the signaling, and the communication control devices 11 and 31 (especially their protocol controllers) have generated the transmitted signal TxD.

[0123] Therefore, according to Figure 11 The signal TxD_TC and Figure 10 The transmitted signal TxD is the same. When the transmit-receive devices 12 and 32 act as transmitting nodes, they drive the signal TxD_TC as a differential voltage VDIFF onto the bus 40. Since no PWM encoding and therefore no decoding is performed, no one-time phase error T_P is generated between the transmitted signal TxD_TC and the transmitted signal TxD in the transmit-receive devices 12 and 32. Figures 10 to 12 The signal propagation time is not shown because it has no effect on the phase error T_P0 and is therefore not important here.

[0124] In order to robustly perform the transition from the first communication stage 451 to the second communication stage 452 despite the possibility of a large phase error T_P0 between the transmitting and receiving nodes, the communication control devices 11, 31 (especially their protocol controllers) take the following actions.

[0125] As in Figure 10 As shown, the communication control devices 11, 31 (especially their protocol controllers) insert at least one additional bit directly after bit DH1, or insert 1 to M additional bits, which have the same value as the first bit DH1 of data phase 452. Figure 10 In the example, communication control devices 11 and 31 (especially their protocol controllers) directly insert bit DH2, i.e., M = 1 additional bits, after bit DH1. M is a natural number greater than or equal to 1. Each of the M bits has a bit time t_bt2. Therefore, bit AL1 is transmitted entirely as a logic value of 1, as if using... Figure 11 As shown by the signal TxD_TC, the transmitting-receiving devices 12 and 32 can drive the signal TxD_TC as a differential voltage VDIFF onto the bus 40.

[0126] Figure 12 The following variation of signal RxD_E is illustrated with respect to time t: The receiving user station (receiving node) (especially its communication control device) anticipates the presence of signal RxD_E at its RXD terminal. In this case, the receiving user station (receiving node) (especially its communication control device) does not anticipate a predetermined value for bit AL1, as in... Figure 12 As illustrated by the shading. In other words, the value of bit AL1 can be either logic 1 or logic 0.

[0127] according to Figure 12 ,exist Figure 12 There is a large phase error T_P0 ("phase error due to clock tolerance") between the expected received signal RxD_E and the actual received signal. Figure 11 The signals TxD_TC are the same. T_P0 is... Figure 11 The start distance of DH1 bit in Figure 12 The initial interval of the DH1 bit. The phase error T_P0 is considered large because it is large compared to the bit time t_bt2 of the second communication phase. In this case, however, it is not considered and Figures 10 to 12 The signal propagation time, especially the signal propagation time via bus 40, is not shown, because the signal propagation time has no effect on the phase error T_P0.

[0128] As a consequence of the phase error T_P0, the receiving user station (receiving node) (especially its communication control unit) samples bit DH1 (the first bit of data phase 452) at sampling time t1. Therefore, the receiving node samples bit DH1, while bit DH2 is transmitted, as in... Figure 12 As shown in the image.

[0129] However, starting from the DH1 bit position, the receiving node allows 1 to N bits to be sampled sequentially with a logic value of 1. The receiving node can skip these N-1 additional bits directly following the DH1 bit by synchronization. N is a natural number greater than or equal to 1. For the bit rate ratio that is being achieved in CAN XL (as described above regarding the task to be solved) and the expected phase error, a value of N = 1 is advantageous or meaningful.

[0130] Despite the phase error T_P0, the receiving node correctly samples bit DH1 (the first bit of data phase 452) as logic 1. This is because, after bit DH1, another bit DH2 with the same logic value is transmitted.

[0131] As in the first embodiment, the next falling edge after the DH1 bit defines the start of the DL1 bit. All receiving nodes synchronize to the next falling edge after the DH1 bit.

[0132] The configuration scheme described above for communication control devices 11 and 31 can compensate for the phase error T_P0, which is formed, for example, by having the transmitting and receiving nodes each use clock sources with tolerances. This eliminates the problem if the slower receiving node is significantly "lagging" behind the transmitting node due to the clock source's tolerance. The phase error T_P0 may be up to several data stage bits, depending on the bit rate ratio of the data stage bit rate to the arbitration stage bit rate.

[0133] Therefore, there is no problem that the receiving node attempts to sample the DH1 bit only after the DH1 bit in the transmitted signal (TxD_TC) has passed.

[0134] Furthermore, the bus system 1 in both embodiments operates in the same way.

[0135] Therefore, compared to current technologies, the logic level of the first bit in data phase 452 is extended in both directions so that both the sampling point t1 of the fast receiver or receiving node and the sampling point t1 of the slow receiver or receiving node correctly sample the value of the first bit DH1 in data phase 452 as 1. Here, to extend backward, i.e., towards the end of frame 450, at least one new bit DH2 is directly inserted after the DH1 bit, the at least one new bit DH2 having the same value as the first bit DH1 of data phase 452. The receiver or receiving node can skip the at least one bit DH2 by synchronization. Alternatively or additionally, to extend forward, i.e., towards the beginning of frame 450, at least the latter or final portion of the AL1 bit AL1_1 having the same value as the DH1 bit can be transmitted.

[0136] All the foregoing construction schemes of user stations 10, 20, 30, bus system 1, and the methods implemented therein can be used individually or in all possible combinations. In particular, all features of the foregoing embodiments and / or all features of modifications of these embodiments can be combined arbitrarily. Additionally or alternatively, the following modifications are contemplated in particular.

[0137] Even though the invention has been described for the sake of example using a CAN bus system, it can be applied to any communication network and / or communication method, employing two distinct communication phases in which different bus states are generated for each phase. In particular, the invention can be used when developing other serial communication networks (such as Ethernet and / or 100Base-T1 Ethernet, fieldbus systems, etc.).

[0138] In particular, the bus system 1 according to these embodiments can be a communication network in which data can be transmitted serially at two different bit rates. Advantageously, but not mandatory, is that exclusive, conflict-free access to a common channel by user stations 10, 20, and 30 is guaranteed in the bus system 1, at least for a defined period of time.

[0139] Of course, the ADS field may have more bits than the bits mentioned in the embodiments described therein.

[0140] The number and layout of user stations 10, 20, and 30 in the bus system 1 of these embodiments are arbitrary. In particular, user station 20 in bus system 1 can be omitted. It is possible that one or more of user stations 10 or 30 exist in bus system 1. It is conceivable that all user stations in bus system 1 are constructed identically, i.e., only user station 10 exists, or only user station 30 exists.

Claims

1. A user station (10; 30) for a serial bus system (1), comprising: A communication control device (11; 31) is configured to control communication between the user station (10; 20; 30) and at least one other user station (10; 20; 30) of the bus system (1), and to generate a transmission signal (TxD) for the transmitting / receiving device (12; 32) of the user station (10; 30), such that the bit time (t_bt1) of the signal transmitted to the bus (40) in the first communication phase (451) for the message (45) exchanged between the user stations (10, 20, 30) of the bus system (1) is distinguishable from the bit time (t_bt2) of the signal transmitted in the second communication phase (452). The communication control device (11; 31) is configured to generate the transmission signal (TxD) according to the frame (450) and insert a field (ADS) with a rising edge and a subsequent falling edge into the frame (450) for transitioning from the first communication phase (451) to the second communication phase (452). The communication control device (11; 31) is configured to perform pulse width modulation on the transmitted signal (TxD) in the field (ADS) and the second communication phase (452) so as to signal to the transmitting / receiving device (12; 32) by means of the pulse width modulation in the field (ADS) that the transmitting / receiving device (12; 32) should switch its operating mode from the operating mode (B 451) of the first communication phase (451) to a different operating mode (B 452 TX; 452 RX) of the second communication phase (452); The communication control device (11; 31) is configured to perform pulse width modulation on the first bit (AL1) at the beginning of the field (ADS) of the transmit signal (TxD) that signals the switching of the operating mode, such that at least the last part of the first bit (AL1) of the field (ADS) has a logic value of 1; and The communication control device (11; 31) is configured such that, if the transmitting / receiving device (12; 32) should not switch its operating mode from the operating mode (B 451) of the first communication stage (451) to the operating mode (B 452 TX; B 452 RX) of the second communication stage (452), it does not perform pulse width modulation on the transmit signal (TxD) that signals the switching of operating modes, and inserts at least one additional bit having the same value as the second bit (DH1) of the field (ADS) directly after the second bit (DH1) of the field (ADS), which is the first bit (DH1) of the second communication stage (452). The field (ADS) is made to have a predetermined length between the rising edge and the subsequent falling edge, and a sampling time (t1) is arranged between the rising edge and the subsequent falling edge such that at the sampling time (t1), the communication control device (21; 31; 11) of the at least one other user station (10; 20; 30) of the bus system (1) will sample the first bit (DH1) of the second communication phase (452).

2. The subscriber station (10; 30) according to claim 1, wherein The field (ADS) of the predetermined length has at least three bits of the bit time (t_bt2) with the second communication stage (452).

3. The subscriber station (10; 30) according to claim 1, wherein The falling edge defines the start of a predetermined bit (DL1) of the second communication phase (452).

4. The subscriber station (10; 30) according to any one of the preceding claims 1-3, wherein The communication control device (11) is configured to insert the field (ADS) as a bit sequence with a logic value of 1110.

5. The user station (10; 30) according to any one of claims 1-3 above. wherein The communication control device (11) is configured to insert, in the field (ADS), the bit with the bit time (t_bt1) of the first communication phase (451) and immediately thereafter the bit with the bit time (t_bt2) of the second communication phase (452) (DH1) before the falling edge. The communication control device (11) is configured such that, immediately following the bit (DH1) of the bit time (t_bt2) of the second communication stage (452), an additional M number of bits of the bit time (t_bt2) of the second communication stage (452) are inserted, each of the M bits of the bit time (t_bt2) of the second communication stage (452) having the same logic value as the first bit (DH1) of the second communication stage (452). Where M is a natural number greater than or equal to 1.

6. The user station (10; 30) according to any one of claims 1-3 above. wherein The communication control device (11) is configured to act as a receiving node in the second communication phase (452), such that the communication control device (11) acts only as a receiver of the frame (450) on the bus (40), but not as a sender of the frame (450) on the bus (40). The communication control device (11) is configured such that, in the field (ADS), starting from and including the sampling time (t1) at which the communication control device (21; 31; 11) samples the first bit (DH1) of the second communication stage (452), and before the falling edge of the field (ADS), N bits having the bit time (t_bt2) of the second communication stage (452) are allowed, each of the N bits having the bit time (t_bt2) of the second communication stage (452) having a logic value of 1. Where N is a natural number greater than or equal to 1, and The communication control device (11) is configured to use the falling edge of the field (ADS) to synchronize with the communication on the bus (40).

7. The user station (10; 30) according to any one of claims 1-3 above. It further includes a transmitting / receiving device (12; 32) for transmitting the transmitting signal (TxD) to the bus (40) of the bus system (1).

8. The user station (10; 30) according to claim 7. wherein The communication control device (11) is configured to signal the transmitting / receiving device (12; 32) directly after the rising edge of the field (ADS) by means of pulse width modulation in the transmitted signal (TxD), that the transmitting / receiving device (12; 32) must switch its operating mode from the operating mode (B_451) of the first communication stage (452) to a different operating mode (B_452_TX; 452_RX) of the second communication stage (452).

9. The user station (10; 30) according to claim 7, wherein, The communication control device (11; 31) is configured to signal the transmitting / receiving device (12; 32) with S directly successive PWM symbols (SB_D0; SB_1) in the transmitted signal (TxD) to which operating mode of the second communication stage (452) the transmitting / receiving device (12; 32) must switch its operating mode, where S is a natural number greater than or equal to 1.

10. The user station (10; 30) according to claim 7, wherein, The communication control device (11; 31) is configured to transmit at least the last portion (AL1_1) of the bit (AL1) having the bit time (t_bt1) of the first communication phase (451), the last portion (AL1_1) having the same logical value as the first bit (DH1) in the field (ADS) having the bit time (t_bt2) of the second communication phase (452).

11. The user station (10; 30) according to any one of claims 1 to 3. Furthermore, it has a transmitting / receiving device (22) for transmitting the transmitted signal (TxD) to the bus (40) of the bus system (1). The transmitting / receiving device (22) is configured to operate in a manner (B_451) for transmitting and receiving the frame (450) in the first communication phase (451), sending the entire frame (450) onto the bus (40).

12. The user station (10; 30) according to any one of claims 1-3 above. in, Establish the frame (450) for the message (45) in compatibility with CAN FD, and In the first communication phase (451), it is negotiated which of the user stations (10, 20, 30) of the bus system (1) will obtain at least temporarily exclusive, conflict-free access to the bus (40) in the subsequent second communication phase (452).

13. A bus system (1) having: Bus (40), and At least two user stations (10; 20; 30) are interconnected via the bus (40) such that the at least two user stations (10; 20; 30) can communicate with each other serially, and at least one of the at least two user stations (10; 20; 30) is a user station (10; 30) according to any one of claims 1-12.

14. A method for communication in a serial bus system (1), wherein the method is implemented using a user station (10; 30) of the bus system (1), the user station (10; 30) having a communication control device (11; 31) and a transmitting / receiving device (12; 22; 32), wherein the method comprises the steps of: The communication control device (11; 31) is used to control the communication between the user station (10; 30) and at least one other user station (10; 20; 30) of the bus system (1), such that the bit time (t_bt1) of the signal sent to the bus (40) in the first communication phase (451) for the message (45) exchanged between the user stations (10, 20, 30) of the bus system (1) is distinguishable from the bit time (t_bt2) of the signal sent in the second communication phase (452). The transmitting / receiving device (12; 32) transmits the transmitting signal (TxD) to the bus (40) of the bus system (1). The communication control device (11; 31) generates the transmission signal (TxD) for the transmitting / receiving device (12; 32) of the user station (10; 30) according to the frame (450), and inserts a field (ADS) with a rising edge and a subsequent falling edge into the frame (450) for transitioning from the first communication phase (451) to the second communication phase (452). The communication control device (11; 31) performs pulse width modulation on the transmitted signal (TxD) in the field (ADS) and the second communication stage (452) so as to signal to the transmitting / receiving device (12; 32) by means of the pulse width modulation in the field (ADS) that the transmitting / receiving device (12; 32) should switch its operating mode from the operating mode (B 451) of the first communication stage (451) to a different operating mode (B 452 TX; 452 RX) of the second communication stage (452); The communication control device (11; 31) performs pulse width modulation on the transmit signal (TxD) that signals the switching of the operating mode, in the first bit (AL1) at the beginning of the field (ADS), such that at least the last part of the first bit (AL1) of the field (ADS) has a logic value of 1; and If the transmitting / receiving device (12; 32) should not switch its operating mode from the operating mode (B 451) of the first communication stage (451) to the operating mode (B 452 TX; B 452 RX) of the second communication stage (452), then the communication control device (11; 31) does not perform pulse width modulation on the transmission signal (TxD) that signals the switching of operating modes, and directly inserts at least one additional bit having the same value as the second bit (DH1) of the field (ADS) after the second bit (DH1), which is the first bit (DH1) of the second communication stage (452). as well as The field (ADS) is made to have a predetermined length between the rising edge and the subsequent falling edge, and a sampling time (t1) is arranged between the rising edge and the subsequent falling edge such that at the sampling time (t1), the communication control device (21; 31; 11) of the at least one other user station (10; 20; 30) of the bus system (1) will sample the first bit (DH1) of the second communication phase (452).

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