Method for screening high-temperature static current failure wafer at room temperature
By screening wafers that fail at high temperatures due to static current at room temperature, and using static current distribution curves to identify wafers at risk of high-temperature failure, this method solves the problem of not being able to effectively screen out defective products in existing technologies, and reduces the cost of high-temperature testing and packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CRM ICBG (WUXI) CO LTD
- Filing Date
- 2021-12-15
- Publication Date
- 2026-05-19
AI Technical Summary
Existing room-temperature wafer testing cannot effectively screen out defective chips for high-temperature applications, leading to the need for additional high-temperature wafer testing or post-packaging testing, which increases costs and inconvenience.
By performing wafer testing at room temperature to obtain static current distribution curves, it is determined whether the current value corresponding to the set quantile exceeds the warning current value, thus screening out wafers with high-temperature static current failure risk, and optionally performing high-temperature wafer testing verification.
This technology enables the screening of wafers that fail due to high-temperature static current at room temperature, reducing the number of full inspections required for high-temperature wafer testing and lowering testing and packaging costs.
Smart Images
Figure CN116264168B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of wafer testing, and in particular to a method for screening wafers that fail due to high-temperature static current at room temperature. Background Technology
[0002] The static current of a chip is one to two orders of magnitude higher at high temperatures than at room temperature. Due to abnormal fluctuations in semiconductor manufacturing processes, especially those affecting the front-end substrate furnace process, the static current of a chip that is normal at room temperature will increase rapidly at high temperatures.
[0003] Existing room-temperature wafer testing (CP testing) cannot screen out defective chips for high-temperature applications, necessitating the addition of a high-temperature wafer testing (CP testing) or a post-packaging high-temperature finished product testing (FT testing). High-temperature wafer testing requires heating and cooling times, and the pins are easily damaged in high-temperature environments, thus hindering large-scale mass production and increasing the cost of high-temperature wafer testing. Post-packaging high-temperature finished product testing, on the other hand, increases the packaging and testing costs of defective products. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for screening wafers with high-temperature static current failure at room temperature, in order to solve the problem that existing room-temperature wafer testing cannot screen out defective chips for high-temperature applications.
[0005] To achieve the above and other related objectives, the present invention provides a method for screening wafers that fail at high-temperature static current at room temperature, the method comprising:
[0006] S1 performs room temperature wafer testing on the wafer and obtains the room temperature static current distribution curve;
[0007] S2 obtains the current value corresponding to the set quantile from the room temperature static current distribution curve, and determines whether the current value corresponding to the set quantile exceeds the warning current value.
[0008] If the value exceeds the limit, the wafer is determined to have a risk of high-temperature static current failure; otherwise, the wafer is determined not to have a risk of high-temperature static current failure.
[0009] Optionally, the method further includes: S3 a step of performing high-temperature wafer testing on wafers with a risk of high-temperature static current failure.
[0010] Optionally, the method further includes: S4, a step of correcting the set quantile and / or the warning current value.
[0011] Optionally, the method for correcting the set quantile includes:
[0012] S41 obtains the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk, and obtains the quantile corresponding to the high-temperature specification current value from the high-temperature static current distribution curve.
[0013] S42 repeats S41 at least once to obtain the quantiles corresponding to different wafers, and corrects the set quantiles based on the multiple quantiles.
[0014] Optionally, the method for correcting the warning current value includes:
[0015] S41 obtains the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk, and obtains the quantile corresponding to the high-temperature specification current value from the high-temperature static current distribution curve.
[0016] S42 obtains the current value corresponding to the quantile from the room temperature static current distribution curve of the wafer with high temperature static current failure risk.
[0017] S43 repeats S41 and S42 at least once to obtain current values corresponding to different wafers, and corrects the warning current value based on multiple said current values.
[0018] Optionally, the method for correcting the set quantile and the warning current value includes:
[0019] S41 obtains the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk, and obtains the quantile corresponding to the high-temperature specification current value from the high-temperature static current distribution curve.
[0020] S42 obtains the current value corresponding to the quantile from the room temperature static current distribution curve of the wafer with high temperature static current failure risk.
[0021] S43 repeats S41 and S42 at least once to obtain the quantile and current value corresponding to different wafers, and corrects the set quantile based on the multiple quantiles, while correcting the warning current value based on the multiple current values.
[0022] Optionally, the method further includes the step of: S0 obtaining the set quantile and the warning current value.
[0023] Optionally, the method for obtaining the set quantile and the warning current value includes:
[0024] S01 performs room temperature wafer testing on at least two wafers to obtain the median and standard deviation of the room temperature quiescent current, and determines whether each wafer has a risk of high temperature quiescent current failure based on the median and standard deviation.
[0025] S02 performs high-temperature wafer testing on wafers with high-temperature static current failure risk, obtains high-temperature static current distribution curves, and obtains quantiles corresponding to high-temperature specification current values from the high-temperature static current distribution curves, and obtains the set quantiles based on the quantiles.
[0026] S03 obtains the current value corresponding to the set quantile from the room temperature static current distribution curve of the wafer with high temperature static current failure risk, and obtains the warning current value based on the current value.
[0027] Alternatively, methods for determining whether each wafer is at risk of high-temperature quiescent current failure based on the median and standard deviation include:
[0028] Obtain the current value corresponding to the initial quantile from the room temperature static current distribution curve of each wafer, and determine whether the difference between the current value corresponding to the initial quantile and the median is greater than 3 times the standard deviation.
[0029] If the value is greater than 0, the corresponding wafer is determined to have a risk of high-temperature static current failure; otherwise, the corresponding wafer is determined not to have a risk of high-temperature static current failure.
[0030] Alternatively, methods for determining whether each wafer is at risk of high-temperature quiescent current failure based on the median and standard deviation include:
[0031] Obtain the current value corresponding to the slope abrupt change singularity from the room temperature static current distribution curve of each wafer, and determine whether the difference between the current value corresponding to the slope abrupt change singularity and the median is greater than 3 times the standard deviation.
[0032] If the value is greater than 0, the corresponding wafer is determined to have a risk of high-temperature static current failure; otherwise, the corresponding wafer is determined not to have a risk of high-temperature static current failure.
[0033] As described above, the present invention provides a method for screening wafers with high-temperature static current failure at room temperature. This method enables the screening of wafers with high-temperature static current failure at the wafer level through room temperature wafer testing, transforming high-temperature wafer testing from full inspection to random sampling verification. This reduces the testing cost of high-temperature wafer testing, as well as the packaging and testing costs of high-temperature finished products. Attached Figure Description
[0034] Figure 1 The flowchart shown is a process described in this invention.
[0035] Figure 2 The diagram shows the static current distribution curve at room temperature for a wafer.
[0036] Figure 3 The diagram shows the high-temperature static current distribution curve of the wafer.
[0037] Figure 4The diagram shows a method to determine whether the current value corresponding to a set quantile exceeds the warning current value based on the static current distribution curve at room temperature. Detailed Implementation
[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0040] like Figure 1 As shown, this embodiment provides a method for screening wafers that fail due to high-temperature static current at room temperature. The method includes at least steps S1 and S2.
[0041] In step S1, the wafer is subjected to room temperature wafer testing, and the room temperature static current distribution curve is obtained.
[0042] When performing room-temperature wafer testing, each die on the wafer needs to be tested to obtain the corresponding room-temperature quiescent current for each die, thus generating a room-temperature quiescent current distribution curve for the entire wafer. The horizontal axis of the room-temperature quiescent current distribution curve represents the quiescent current value, and the vertical axis represents the percentage of die distribution, i.e., the quantile (e.g., quantile). Figure 2 (As shown). It should be noted that room temperature wafer testing will screen out some defective products, while the wafers involved in the method described in this embodiment are all good products that have passed room temperature wafer testing.
[0043] In step S2, the current value corresponding to the set quantile is obtained from the room temperature static current distribution curve, and it is determined whether the current value corresponding to the set quantile exceeds the warning current value; if it exceeds, the wafer is determined to have a high-temperature static current failure risk; otherwise, the wafer is determined not to have a high-temperature static current failure risk (e.g., ...). Figure 4 As shown, if the quantile is set to 80 and the warning current value is 5μA, then the wafers shown by curves 4 and 5 in the figure are judged to have a risk of high-temperature static current failure.
[0044] The yield rate of wafers meeting specifications for static current at room temperature is very high, but the distribution varies, with some areas converging, indicating better overall uniformity (e.g., ...). Figure 2 As shown in curve 1), some are dispersed, that is, the overall uniformity is poor (e.g., Figure 2 As shown in curve 2), this embodiment uses the judgment in step S2 to screen out wafers with poor overall uniformity by utilizing this distribution difference; and for wafers with poor overall uniformity, the static current increases more significantly at high temperatures, posing a potential risk of high-temperature static current failure (e.g., Figure 3 (As shown).
[0045] Furthermore, the method also includes step S3. In step S3, a high-temperature wafer test is performed on the wafer with the risk of high-temperature quiescent current failure to achieve failure verification.
[0046] When performing high-temperature wafer testing on wafers at risk of high-temperature quiescent current failure, it is also necessary to test each die on the wafer to verify its failure. In practical applications, the accuracy of failure verification is related to the set quantile and the warning current value. If the set quantile and the warning current value are designed reasonably, the accuracy of failure verification will be very high. That is, when performing failure verification through high-temperature wafer testing, the verification results will show that most of the selected wafers do indeed have the risk of high-temperature quiescent current failure.
[0047] Furthermore, the method also includes step S4. In step S4, the set quantile and / or the warning current value are corrected to utilize large data sample statistics to make the set quantile and / or the warning current value more accurate, thereby improving the screening accuracy of the method described in this embodiment. It should be noted that "correcting the set quantile and / or the warning current value" in this step means "correcting only one of them, or correcting both at the same time."
[0048] In one example, only the set quantile may be modified. In this case, the modification method involved includes steps S41 and S42.
[0049] In step S41, the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk is obtained, and the quantile corresponding to the high-temperature specification current value is obtained from the high-temperature static current distribution curve.
[0050] In step S3, when performing high-temperature wafer testing on a wafer at risk of high-temperature static current failure, the high-temperature static current corresponding to different grains in the wafer can be obtained, thus yielding the high-temperature static current distribution curve for that wafer. The horizontal axis of the high-temperature static current distribution curve represents the static current value, and the vertical axis represents the distribution percentage of the grains, i.e., the quantile (e.g., quantile). Figure 3(As shown). The high-temperature specification current value refers to the maximum value of the high-temperature quiescent current when the design meets the application requirements (e.g., Figure 3 (100μA), this value can be found in the product design specifications for the maximum value of the high-temperature quiescent current.
[0051] In step S42, step S41 is repeated at least once to obtain the quantiles corresponding to different wafers, and the set quantiles are corrected based on the multiple quantiles.
[0052] In practical applications, the set quantile can be corrected by the median or mean of multiple quantiles. If there are many wafers with a risk of high-temperature static current failure, the set quantile can be corrected by the median of multiple quantiles, that is, the median of multiple quantiles is used as the set quantile. If there are few wafers with a risk of high-temperature static current failure, the set quantile can be corrected by the mean of multiple quantiles, that is, the mean of multiple quantiles is used as the set quantile.
[0053] In another example, only the warning current value may be corrected. In this case, the correction method includes steps S41, S42 and S43.
[0054] In step S41, the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk is obtained, and the quantile corresponding to the high-temperature specification current value is obtained from the high-temperature static current distribution curve.
[0055] In step S3, when performing high-temperature wafer testing on a wafer at risk of high-temperature static current failure, the high-temperature static current corresponding to different grains in the wafer can be obtained, thus yielding the high-temperature static current distribution curve for that wafer. The horizontal axis of the high-temperature static current distribution curve represents the static current value, and the vertical axis represents the distribution percentage of the grains, i.e., the quantile (e.g., quantile). Figure 3 (As shown). The high-temperature specification current value refers to the maximum value of the high-temperature quiescent current when the design meets the application requirements (e.g., Figure 3 (100μA), this value can be found in the product design specifications for the maximum value of the high-temperature quiescent current.
[0056] In step S42, the current value corresponding to the quantile is obtained from the room-temperature static current distribution curve of the wafer with high-temperature static current failure risk. It should be noted that the quantile mentioned here refers to the quantile corresponding to the high-temperature specification current value in step S41.
[0057] When the wafer is tested at room temperature in step S1, the corresponding room temperature static current distribution curve of the wafer has already been obtained. Therefore, there is no need to test the wafer at room temperature again in this step. The room temperature static current distribution curve obtained in step S1 can be used directly.
[0058] In step S43, steps S41 and S42 are repeated at least once to obtain current values corresponding to different wafers, and the warning current value is corrected based on multiple current values.
[0059] In practical applications, the warning current value can be corrected using the median or average of multiple current values. If there are a large number of wafers at risk of high-temperature static current failure, the warning current value can be corrected using the median of multiple current values, that is, the median of multiple current values is used as the warning current value. If there are a small number of wafers at risk of high-temperature static current failure, the warning current value can be corrected using the average of multiple current values, that is, the average of multiple current values is used as the warning current value.
[0060] In another example, the set quantile and the warning current value can be corrected simultaneously. In this case, the correction method includes steps S41, S42 and S43.
[0061] In step S41, the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk is obtained, and the quantile corresponding to the high-temperature specification current value is obtained from the high-temperature static current distribution curve.
[0062] In step S3, when performing high-temperature wafer testing on a wafer at risk of high-temperature static current failure, the high-temperature static current corresponding to different grains in the wafer can be obtained, thus yielding the high-temperature static current distribution curve for that wafer. The horizontal axis of the high-temperature static current distribution curve represents the static current value, and the vertical axis represents the distribution percentage of the grains, i.e., the quantile (e.g., quantile). Figure 3 (As shown). The high-temperature specification current value refers to the maximum value of the high-temperature quiescent current when the design meets the application requirements (e.g., Figure 3 (100μA), this value can be found in the product design specifications for the maximum value of the high-temperature quiescent current.
[0063] In step S42, the current value corresponding to the quantile is obtained from the room-temperature static current distribution curve of the wafer with high-temperature static current failure risk. It should be noted that the quantile mentioned here refers to the quantile corresponding to the high-temperature specification current value in step S41.
[0064] When the wafer is tested at room temperature in step S1, the corresponding room temperature static current distribution curve of the wafer has already been obtained. Therefore, there is no need to test the wafer at room temperature again in this step. The room temperature static current distribution curve obtained in step S1 can be used directly.
[0065] In step S43, steps S41 and S42 are repeated at least once to obtain the quantiles and current values corresponding to different wafers, and the set quantile is corrected based on the multiple quantiles. At the same time, the warning current value is corrected based on the multiple current values.
[0066] In practical applications, the set quantile can be corrected using the median or mean of multiple quantiles. If the number of wafers at risk of high-temperature static current failure is large, the set quantile can be corrected using the median of multiple quantiles; that is, the median of multiple quantiles is used as the set quantile. If the number of wafers at risk of high-temperature static current failure is small, the set quantile can be corrected using the mean of multiple quantiles; that is, the mean of multiple quantiles is used as the set quantile. Similarly, the warning current value can be corrected using the median or mean of multiple current values. If the number of wafers at risk of high-temperature static current failure is large, the warning current value can be corrected using the median of multiple current values; that is, the median of multiple current values is used as the warning current value. If the number of wafers at risk of high-temperature static current failure is small, the warning current value can be corrected using the mean of multiple current values; that is, the mean of multiple current values is used as the warning current value.
[0067] Furthermore, the method further includes step S0, obtaining the set quantile and the warning current value. Even further, the method for obtaining the set quantile and the warning current value includes steps S01, S02, and S03.
[0068] In step S01, at least two wafers are subjected to room temperature wafer testing to obtain the median and standard deviation of the room temperature quiescent current, and each wafer is determined to have a risk of high temperature quiescent current failure based on the median and standard deviation.
[0069] When performing room-temperature wafer testing, each die on the wafer needs to be tested to obtain the corresponding room-temperature quiescent current for each die, thus obtaining the room-temperature quiescent current distribution curve for each wafer. To obtain the median, the median of the room-temperature quiescent current for each wafer can be calculated first, and then the median of multiple medians can be calculated to obtain the final median. Alternatively, the median of the room-temperature quiescent current for multiple wafers can be calculated directly, which has no substantial impact on this embodiment. To obtain the standard deviation, the mean of the room-temperature quiescent current for each wafer can be calculated first, and then the standard deviation for each wafer can be calculated from the mean. Finally, the mean of multiple standard deviations can be calculated to obtain the final standard deviation. Alternatively, the mean of the room-temperature quiescent current for multiple wafers can be calculated directly, and then the standard deviation can be calculated directly from the mean, which has no substantial impact on this embodiment.
[0070] In one example, a method for determining whether each wafer has a high-temperature static current failure risk based on the median and standard deviation includes: obtaining the current value corresponding to the initial quantile from the room-temperature static current distribution curve of each wafer, and determining whether the difference between the current value corresponding to the initial quantile and the median is greater than 3 times the standard deviation; if it is greater, the corresponding wafer is determined to have a high-temperature static current failure risk; otherwise, the corresponding wafer is determined not to have a high-temperature static current failure risk. In practical applications, the initial quantile can be set to 75, or it can be set to 80 or 90, etc.; this value only affects the number of wafers sampled for high-temperature wafer testing in the early stages, but as the sample size increases, the initially obtained set quantile and warning current will be continuously corrected, thereby improving accuracy.
[0071] In another example, a method for determining whether each wafer has a risk of high-temperature static current failure based on the median and standard deviation includes: obtaining the current value corresponding to the slope abrupt change singularity from the room-temperature static current distribution curve of each wafer, and determining whether the difference between the current value corresponding to the slope abrupt change singularity and the median is greater than 3 times the standard deviation; if it is greater, the corresponding wafer is determined to have a risk of high-temperature static current failure, otherwise, the corresponding wafer is determined not to have a risk of high-temperature static current failure.
[0072] In step S02, a high-temperature wafer test is performed on the wafer with the risk of high-temperature static current failure to obtain a high-temperature static current distribution curve, and the quantile corresponding to the high-temperature specification current value is obtained from the high-temperature static current distribution curve, and the set quantile is obtained based on the quantile.
[0073] When performing high-temperature wafer testing, each die on the wafer needs to be tested to obtain the high-temperature quiescent current for each die, thus generating a high-temperature quiescent current distribution curve for that wafer. The horizontal axis of the high-temperature quiescent current distribution curve represents the quiescent current value, and the vertical axis represents the distribution percentage of the die, i.e., the quantile. The high-temperature specification current value refers to the maximum high-temperature quiescent current required to meet application requirements; this value can be found in the maximum high-temperature quiescent current specified in the product design specification.
[0074] When the number of wafers with the risk of high-temperature static current failure is 1, the quantile corresponding to the high-temperature specification current value is the set quantile; when the number of wafers with the risk of high-temperature static current failure is greater than or equal to 2, the set quantile is the median or mean of multiple quantiles.
[0075] In step S03, the current value corresponding to the set quantile is obtained from the room temperature static current distribution curve of the wafer with high temperature static current failure risk, and the warning current value is obtained based on the current value.
[0076] When the wafer is tested at room temperature in step S01, the room temperature static current distribution curve of the wafer has already been obtained. Therefore, there is no need to test the wafer at room temperature again in this step. The room temperature static current distribution curve obtained in step S01 can be used directly.
[0077] When there is only one wafer at risk of high-temperature static current failure, the current value corresponding to the set quantile is the warning current value; when there are two or more wafers at risk of high-temperature static current failure, the warning current value is the median or average of multiple current values.
[0078] In the specific implementation process, when applying the method described in this embodiment to wafer testing, steps S0, S1, S2, S3 and S4 can be executed sequentially to screen out wafers with high-temperature static current failure. This embodiment utilizes the proportional relationship between high-temperature and room-temperature static current to deduce the distribution trend of high-temperature static current from the room-temperature static current distribution, and performs high-temperature sampling inspection on a small number of out-of-specification wafers. The high-temperature database accumulated from the sampled wafers can be used for statistical calculations to iteratively correct the set quantiles and warning current values, making the model more accurate.
[0079] In summary, the method for screening wafers with high-temperature static current failure at room temperature according to the present invention can achieve the screening of wafers with high-temperature static current failure through room-temperature wafer testing at the wafer level. This transforms high-temperature wafer testing from full inspection to random sampling verification, thereby reducing the testing costs of high-temperature wafer testing, as well as the packaging and testing costs of high-temperature finished products. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for screening wafers that fail due to high-temperature static current at room temperature, characterized in that, The method includes: S0 retrieves the set quantile; S1 performs room temperature wafer testing on the wafer and obtains the room temperature static current distribution curve; S2 obtains the current value corresponding to the set quantile from the room temperature static current distribution curve, and determines whether the current value corresponding to the set quantile exceeds the warning current value. If the value exceeds the limit, the wafer is determined to have a risk of high-temperature static current failure; otherwise, the wafer is determined to have no risk of high-temperature static current failure. The method for obtaining the set quantile includes: S01 performs room temperature wafer testing on at least two wafers to obtain the median and standard deviation of the room temperature quiescent current, and determines whether each wafer has a risk of high temperature quiescent current failure based on the median and standard deviation. S02 performs high-temperature wafer testing on wafers with high-temperature static current failure risk, obtains high-temperature static current distribution curves, and obtains quantiles corresponding to high-temperature specification current values from the high-temperature static current distribution curves, and obtains the set quantiles based on the quantiles.
2. The method for screening wafers that fail at high-temperature static current at room temperature according to claim 1, characterized in that, The method further includes: S3, a step of performing high-temperature wafer testing on wafers with a risk of high-temperature static current failure.
3. The method for screening wafers that fail at high-temperature static current at room temperature according to claim 2, characterized in that, The method further includes: S4, a step of correcting the set quantile and / or the warning current value.
4. The method for screening wafers that fail at high-temperature static current at room temperature according to claim 3, characterized in that, The method for correcting the set quantiles includes: S41 obtains the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk, and obtains the quantile corresponding to the high-temperature specification current value from the high-temperature static current distribution curve. S42 repeats S41 at least once to obtain the quantiles corresponding to different wafers, and corrects the set quantiles based on the multiple quantiles.
5. The method for screening wafers that fail at high-temperature static current at room temperature according to claim 3, characterized in that, The method for correcting the warning current value includes: S41 obtains the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk, and obtains the quantile corresponding to the high-temperature specification current value from the high-temperature static current distribution curve. S42 obtains the current value corresponding to the quantile from the room temperature static current distribution curve of the wafer with high temperature static current failure risk. S43 repeats S41 and S42 at least once to obtain current values corresponding to different wafers, and corrects the warning current value based on multiple said current values.
6. The method for screening wafers that fail at high-temperature static current at room temperature according to claim 3, characterized in that, The method for correcting the set quantile and the warning current value includes: S41 obtains the high-temperature static current distribution curve of the wafer with high-temperature static current failure risk, and obtains the quantile corresponding to the high-temperature specification current value from the high-temperature static current distribution curve. S42 obtains the current value corresponding to the quantile from the room temperature static current distribution curve of the wafer with high temperature static current failure risk. S43 repeats S41 and S42 at least once to obtain the quantile and current value corresponding to different wafers, and corrects the set quantile based on the multiple quantiles, while correcting the warning current value based on the multiple current values.
7. The method for screening high-temperature static current failure wafers at room temperature according to any one of claims 1-6, characterized in that, S0 also acquires the warning current value.
8. The method for screening wafers that fail at high-temperature static current at room temperature according to claim 7, characterized in that, The method for obtaining the warning current value includes: S03 obtains the current value corresponding to the set quantile from the room temperature static current distribution curve of the wafer with high temperature static current failure risk, and obtains the warning current value based on the current value.
9. The method for screening high-temperature static current failure wafers at room temperature according to claim 1, characterized in that, Methods for determining whether each wafer is at risk of high-temperature static current failure based on median and standard deviation include: Obtain the current value corresponding to the initial quantile from the room temperature static current distribution curve of each wafer, and determine whether the difference between the current value corresponding to the initial quantile and the median is greater than 3 times the standard deviation. If the value is greater than 0, the corresponding wafer is determined to have a risk of high-temperature static current failure; otherwise, the corresponding wafer is determined not to have a risk of high-temperature static current failure.
10. The method for screening wafers with high-temperature static current failure at room temperature according to claim 1, characterized in that, Methods for determining whether each wafer is at risk of high-temperature static current failure based on median and standard deviation include: Obtain the current value corresponding to the slope abrupt change singularity from the room temperature static current distribution curve of each wafer, and determine whether the difference between the current value corresponding to the slope abrupt change singularity and the median is greater than 3 times the standard deviation. If the value is greater than 0, the corresponding wafer is determined to have a risk of high-temperature static current failure; otherwise, the corresponding wafer is determined not to have a risk of high-temperature static current failure.