Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate, and at least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction, and a thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with gate oxide layers of different thicknesses and a method for manufacturing the same. Background Technology

[0002] In power devices with high-voltage handling capabilities, double-diffused MOS (DMOS) transistors continue to receive significant attention. Common DMOS transistors include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors. Due to their high operating bandwidth and efficiency, as well as their planar structure that facilitates integration with other integrated circuits, LDMOS transistors are widely used in high-voltage operating environments, such as CPU power supplies, power management systems, AC / DC converters, and high-power or high-frequency power amplifiers. A key feature of LDMOS transistors is the use of a large-area lateral diffusion drift region with low doping concentration to mitigate the high voltage between the source and drain terminals, thus enabling LDMOS transistors to achieve a high breakdown voltage. However, as the requirements for related products become increasingly stringent, improving the electrical performance, reliability, and / or density of high-voltage semiconductor components through design adjustments in structure and / or manufacturing processes remains a continuous area of ​​focus for researchers in the field. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, wherein a portion of the gate structure is disposed in a trench of a semiconductor substrate and the gate structure has a gate oxide layer of different thicknesses, thereby achieving the effect of reducing the area occupied by the semiconductor device and / or improving the electrical performance of the semiconductor device.

[0004] An embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate, and the gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate, and at least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed in a vertical direction between the second portion of the gate electrode and the semiconductor substrate, and the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0005] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a trench in a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate, and at least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed in a vertical direction between the second portion of the gate electrode and the semiconductor substrate, and the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0007] Figures 2 to 7 This is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein...

[0008] Figure 3 for Figure 2 A diagram illustrating the subsequent situation;

[0009] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0010] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0011] Figure 6 for Figure 5 A diagram illustrating the subsequent situation;

[0012] Figure 7 for Figure 6 A diagram illustrating the subsequent situation.

[0013] Figure 8This is a schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0014] Figure 9 and Figure 10 This is a schematic diagram of a method for fabricating a semiconductor device according to a second embodiment of the present invention, wherein... Figure 10 for Figure 9 A diagram illustrating the subsequent situation.

[0015] Explanation of main component symbols

[0016] 10 Semiconductor substrate

[0017] 10A Active (Active) Region

[0018] 12. Isolation Structure

[0019] 20 Pad oxide layer

[0020] 20P patterned oxide layer

[0021] 20S Second Gate Oxide Layer

[0022] 22 Drift Zone

[0023] 22A First Drift Zone

[0024] 22B Second Drift Zone

[0025] 24 Shielding layer

[0026] 30 trenches

[0027] 40 First gate oxide layer

[0028] 50 Gate material layer

[0029] 50G gate electrode

[0030] 60 Spacer wall structure

[0031] 70 Source / Drain Region

[0032] 70A First Source / Drain Region

[0033] 70B Second Source / Drain Region

[0034] 80 Patterned shielding layer

[0035] 91 Etching process

[0036] 92 Patterning process

[0037] 101 Semiconductor Device

[0038] 102 Semiconductor Device

[0039] BT1 bottom

[0040] BT2 bottom

[0041] BT3 bottom

[0042] D1 Vertical direction

[0043] D2 Horizontal direction

[0044] GS gate structure

[0045] P11 Part 1

[0046] P12 Part 2

[0047] P21 Part 1

[0048] P22 Part 2

[0049] S1 upper surface

[0050] S2 bottom surface

[0051] SW1 sidewall

[0052] SW2 sidewall

[0053] SW3 sidewall

[0054] SW4 sidewall

[0055] T1 thickness

[0056] T2 thickness

[0057] T3 thickness Detailed Implementation

[0058] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0059] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0060] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0061] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the components of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed component, nor do they represent the order of one claimed component with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claimed component with a certain name to be clearly distinguished from another claimed component with the same name.

[0062] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term that includes etching.

[0063] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0064] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 1 As shown, the semiconductor device 101 includes a semiconductor substrate 10, a trench 30, and a gate structure GS. The trench 30 is disposed in the semiconductor substrate 10, and the gate structure GS is disposed on the semiconductor substrate 10. The gate structure GS includes a gate electrode 50G, a first gate oxide layer 40, and a second gate oxide layer 20S. A first portion P11 of the gate electrode 50G is disposed in the trench 30, and a second portion P12 of the gate electrode 50G is disposed outside the trench 30. The first gate oxide layer 40 is disposed between the gate electrode 50G and the semiconductor substrate 10, and at least a portion of the first gate oxide layer 40 is disposed in the trench 30. The second gate oxide layer 20S is disposed in a vertical direction D1 between the second portion P12 of the gate electrode 50G and the semiconductor substrate 10, and the thickness of the second gate oxide layer 20S (e.g., ...) is... Figure 1 The thickness T3 shown is greater than the thickness of the first gate oxide layer 40 (e.g., Figure 1(Thicknesses T1 and / or T2 shown). By disposing a portion of the gate structure GS in the trench 30 of the semiconductor substrate 10, the area occupied by the semiconductor device 101 in the vertical direction D1 can be relatively reduced, thereby increasing the number and / or density of semiconductor devices 101. Furthermore, the relatively thick second gate oxide layer 20S can be used to reduce the electric field at the edge of the gate structure GS, thereby improving the reliability and / or related electrical performance of the semiconductor device 101.

[0065] In some embodiments, the vertical direction D1 can be considered as the thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 may have an upper surface S1 and a bottom surface S2 opposite to each other in the vertical direction D1. In some embodiments, the trench 30 may be a structure recessed from the upper surface S1 of the semiconductor substrate 10 toward the bottom surface S2, and the gate structure GS may be disposed on one side of the upper surface S1. Furthermore, the horizontal direction (e.g., generally orthogonal to the vertical direction D1) is also considered. Figure 1 The horizontal direction D2 and other directions orthogonal to the vertical direction D1 shown herein may be generally parallel to the upper surface S1 and / or the bottom surface S2 of the semiconductor substrate 10, but are not limited thereto. The distance in the vertical direction D1 between a relatively high position and / or component and the bottom surface S2 of the semiconductor substrate 10 may be greater than the distance in the vertical direction D1 between a relatively low position and / or component and the bottom surface S2 of the semiconductor substrate 10. The lower part or bottom of each component may be closer to the bottom surface S2 of the semiconductor substrate 10 in the vertical direction D1 than the upper part or top of that component. Another component above a component may be considered relatively far from the bottom surface S2 of the semiconductor substrate 10 in the vertical direction D1, and another component below a component may be considered relatively close to the bottom surface S2 of the semiconductor substrate 10 in the vertical direction D1.

[0066] Further, in some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. Additionally, in some embodiments, the semiconductor device 101 may also include an isolation structure 12 at least partially disposed in the semiconductor substrate 10 to define one or more active regions 10A in the semiconductor substrate 10, and the trench 30 may be considered to be disposed in the active region 10A surrounded by the isolation structure 12 in the horizontal direction D2, but is not limited thereto. The isolation structure 12 may include a single layer or multiple layers of insulating material, such as oxide insulating material or other suitable insulating material, and the isolation structure 12 may be considered a shallow trench isolation (STI) structure, but is not limited thereto.

[0067] In some embodiments, the semiconductor device 101 may further include two drift regions 22 (e.g. Figure 1 The first drift region 22A and the second drift region 22B shown in the figure) and the two source / drain regions 70 (e.g. Figure 1 The first source / drain region 70A and the second source / drain region 70B are shown in the diagram. The first drift region 22A and the second drift region 22B can be disposed in the semiconductor substrate 10 and are respectively located on two opposite sides of the trench 30 in the horizontal direction D2, while the first source / drain region 70A and the second source / drain region 70B can be respectively disposed in the first drift region 22A and the second drift region 22B. In some embodiments, the two source / drain regions 70 can be a source region and a drain region respectively (for example, the first source / drain region 70A can be a source region and the second source / drain region 70B can be a drain region, or the second source / drain region 70B can be a source region and the first source / drain region 70A can be a drain region), and the semiconductor device 101 can be regarded as a double diffused drain metal-oxide semiconductor (DDDMOS) structure, but is not limited thereto.

[0068] In some embodiments, the drift region 22 may include a doped region formed by a doping fabrication process (e.g., an implantation process) on the semiconductor substrate 10. The semiconductor substrate 10 may be a semiconductor substrate having a first conductivity type or a region including the first conductivity type (e.g., a doped well region having the first conductivity type, not shown), while the drift region 22 may have a second conductivity type, and the second conductivity type may be complementary to the first conductivity type. For example, in this embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type, but this is not a limitation. In other words, in some embodiments, the semiconductor substrate 10 may be a p-type semiconductor substrate or a semiconductor substrate having a p-type well region, while the drift region 22 may be an n-type doped region; or the semiconductor substrate 10 may be an n-type semiconductor substrate or a semiconductor substrate having an n-type well region, while the drift region 22 may be a p-type doped region. In some embodiments, the source / drain region 70 may include a doped region formed in the semiconductor substrate 10 using a doping fabrication process (e.g., an implantation fabrication process). The conductivity type of the source / drain region 70 may be the same as that of the drift region 22, but the doping concentration of the source / drain region 70 may be higher than that of the drift region 22. For example, the source / drain region 70 may be an n-type heavily doped region, but it is not limited thereto.

[0069] In some embodiments, a first portion P11 of the gate electrode 50G may be disposed in the trench 30 and between two drift regions 22 in the horizontal direction D2. At least a portion of the first gate oxide layer 40 may be disposed in the horizontal direction D2 between the first portion P11 of the gate electrode 50G and each drift region 22. For example, a portion of the first gate oxide layer 40 may be disposed in the horizontal direction D2 between the first portion P11 of the gate electrode 50G and the first drift region 22A and directly contact the first portion P11 of the gate electrode 50G and the first drift region 22, while another portion of the first gate oxide layer 40 may be disposed in the horizontal direction D2 between the first portion P11 of the gate electrode 50G and the second drift region 22B and directly contact the first portion P11 of the gate electrode 50G and the second drift region 22B, but this is not a limitation.

[0070] In some embodiments, the first gate oxide layer 40 may be substantially conformally disposed on the surface of the trench 30. Therefore, the thickness T1 of the first gate oxide layer 40 disposed between the first portion P11 of the gate electrode 50G and the semiconductor substrate 10 in the vertical direction D1 may be substantially equal to the thickness T2 disposed between the first portion P11 of the gate electrode 50G and the drift region 22 in the horizontal direction D2, but is not limited thereto. By disposing at least a portion of the gate electrode 50G and the first gate oxide layer 40 in the trench 30 and conformally disposing the first gate oxide layer 40 on the surface of the trench 30, the overlapping area between the gate electrode 50G and the drift region 22 can extend along the sidewall of the trench 30. Therefore, the area occupied by the semiconductor device 101 and / or the gate structure GS in the vertical direction D1 can be relatively reduced under certain overlap area requirements. In some embodiments, the sidewalls of the trench 30 may be inclined sidewalls (i.e., not parallel to the vertical direction D1), and a portion of each drift region 22 may be disposed below the trench 30 in the vertical direction D1, but this is not a limitation. Furthermore, in some embodiments, the bottom of each drift region 22 (e.g., the bottom BT1 of the first drift region 22A and the bottom BT2 of the second drift region 22B) may be lower than the bottom BT3 of the trench 30 in the vertical direction D1, thereby improving the electrical performance (e.g., withstand voltage capability) of the semiconductor device 101, but this is not a limitation. In some embodiments, the aforementioned bottom BT1, bottom BT2, and bottom BT3 may be the bottommost portions of the first drift region 22A, the second drift region 22B, and the trench 30 in the vertical direction D1, respectively, and the bottom BT1, bottom BT2, and bottom BT3 may also be considered as the portions of the first drift region 22A, the second drift region 22B, and the trench 30 with the shortest distance to the bottom surface S2 of the semiconductor substrate 10, but this is not a limitation.

[0071] In some embodiments, the second gate oxide layer 20S may be disposed outside the trench 30 and located at opposite edges in the gate structure GS, for example, the second gate oxide layer 20S may be located at opposite ends of the gate structure GS in the horizontal direction D2, but is not limited thereto. Furthermore, the second gate oxide layer 20S may be disposed in the vertical direction D1 between the second portion P12 of the gate electrode 50G and each drift region 22. For example, a portion of the second gate oxide layer 20S may be disposed in the vertical direction D1 between the second portion P12 of the gate electrode 50G and the first drift region 22A, while another portion of the second gate oxide layer 20S may be disposed in the vertical direction D1 between the second portion P12 of the gate electrode 50G and the second drift region 22B, and the thickness T3 of the second gate oxide layer 20S may be greater than the thickness of the first gate oxide layer 40 (e.g., thickness T1 and / or thickness T2). Furthermore, the aforementioned thickness T1 can be considered as the length of the first gate oxide layer 40 disposed at the bottom of the trench 30 in the vertical direction D1, and the aforementioned thickness T3 can be considered as the length of the second gate oxide layer 20S in the vertical direction D1, but is not limited thereto.

[0072] In some embodiments, the first gate oxide layer 40 and the second gate oxide layer 20S can be formed using different fabrication processes. Therefore, the material composition of the first gate oxide layer 40 can be the same as or different from that of the second gate oxide layer 20S, depending on design requirements. For example, the first gate oxide layer 40 and the second gate oxide layer 20S can each comprise silicon oxide or other suitable oxide dielectric materials. In some embodiments, the first gate oxide layer 40 and the second gate oxide layer 20S have similar materials (e.g., both can be silicon oxide, but are not limited thereto). However, since the first gate oxide layer 40 and the second gate oxide layer 20S can be formed using different fabrication processes, they can therefore have different material properties (e.g., different densities, different lattice arrangements, different silicon-oxygen atom ratios, and / or different equivalent dielectric constants, etc.). In some embodiments, the second gate oxide layer 20S may be disposed outside the trench 30 and not disposed in the trench 30 at all, the first gate oxide layer 40 may be directly connected to the second gate oxide layer 20S, and the gate electrode 50G may completely cover the first gate oxide layer 40 and the second gate oxide layer 20S in the vertical direction D1, but is not limited thereto.

[0073] In some embodiments, the semiconductor device 101 may further include a spacer wall structure 60 disposed on the sidewall of the gate structure GS. The spacer wall structure 60 may include a single layer or multiple layers of dielectric material, such as silicon nitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the sidewall SW1 of the second portion P12 of the gate electrode 50G and the sidewall SW2 of the second gate oxide layer 20S may be substantially flush with each other and can be considered together as the sidewall of the gate structure GS. Therefore, the spacer wall structure 60 may be disposed on the sidewall SW1 of the second portion P12 of the gate electrode 50G and the sidewall SW2 of the second gate oxide layer 20S and directly contact the sidewalls SW1 and SW2, but is not limited thereto. In some embodiments, the gate electrode 50G may be substantially conformally disposed on the semiconductor substrate 10 and in the trench 30. Therefore, the upper surface of the gate electrode 50G may have a recessed surface corresponding to the trench 30 in the vertical direction D1, and the sidewall SW3 of this recessed surface may be considered as the inner sidewall of the gate structure GS, but is not limited thereto. Furthermore, the first portion P11 of the gate electrode 50G disposed in the trench 30 can be directly connected to the second portion P12 of the gate electrode 50G disposed outside the trench 30. In some embodiments, the spacer wall structure 60 described above may also be partially disposed on the inner sidewall (e.g., sidewall SW3) of the gate structure GS due to the manufacturing method, but this is not a limitation. In some embodiments, the gate electrode 50G may include a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate structure formed by stacking a work function layer and a low resistance layer, but this is not a limitation.

[0074] Please see Figures 1 to 7 . Figures 2 to 7 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein... Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 The following is a diagram illustrating the situation, and Figure 7 It is illustrated Figure 6 A schematic diagram of the subsequent situation. In some embodiments, Figure 1 It can be regarded as a drawing Figure 7 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 1As shown, the method for fabricating the semiconductor device 101 in this embodiment may include the following steps. First, a trench 30 is formed in a semiconductor substrate 10, and a gate structure GS is formed on the semiconductor substrate 10. The gate structure GS includes a gate electrode 50G, a first gate oxide layer 40, and a second gate oxide layer 20S. A first portion P11 of the gate electrode 50G is disposed in the trench 30, and a second portion P12 of the gate electrode 50G is disposed outside the trench 30. The first gate oxide layer 40 is disposed between the gate electrode 50G and the semiconductor substrate 10, and at least a portion of the first gate oxide layer 40 is disposed in the trench 30. The second gate oxide layer 20S is disposed in the vertical direction D1 between the second portion P12 of the gate electrode 50G and the semiconductor substrate 10, and the thickness T3 of the second gate oxide layer 20S is greater than the thickness T1 and / or the thickness T2 of the first gate oxide layer 40.

[0075] To further explain, the manufacturing method of this embodiment may include, but is not limited to, the following steps. For example... Figure 2 As shown, a pad oxide layer 20 is formed on a semiconductor substrate 10, while an isolation structure 12 may be formed in the semiconductor substrate 10 prior to the formation of the pad oxide layer 20. The pad oxide layer 20 may comprise silicon oxide or other suitable oxide dielectric materials, and the pad oxide layer 20 may be formed by suitable fabrication processes (e.g., oxidation fabrication processes and / or deposition fabrication processes). Furthermore, two drift regions 22 may be formed in the semiconductor substrate 10. The drift regions 22 may be formed in the active region 10A defined by the isolation structure 12, and thus the drift regions 22 may be surrounded by the isolation structure 12 in a horizontal direction (e.g., horizontal direction D2 and / or other directions orthogonal to the vertical direction D1). In some embodiments, the drift regions 22 may be formed in the semiconductor substrate 10 after the formation of the pad oxide layer 20, but this is not a limitation. In some embodiments, the pad oxide layer 20 may also be formed after the formation of the drift regions 22, depending on design requirements. In addition, in some embodiments, a doped well region (not shown) may be formed in the semiconductor substrate 10 as required by design. The doped well region may be formed in the semiconductor substrate 10 by a suitable doping process before the drift region 22 is formed, but is not limited thereto.

[0076] like Figures 2 to 3As shown, a shielding layer 24 can be formed on the pad oxide layer 20, and an etching process 91 can be performed on the pad oxide layer 20 and the semiconductor substrate 10 using the shielding layer 24 to form a trench 30. In other words, a portion of the pad oxide layer 20 and a portion of the semiconductor substrate 10 can be removed by the etching process 91, and the pad oxide layer 20 can be etched by the etching process 91 to become a patterned oxide layer 20P, and the patterned oxide layer 20P can be located outside the trench 30. In some embodiments, the shielding layer 24 may include silicon nitride or other suitable shielding materials, and the material composition of the shielding layer 24 may be different from the material composition of the pad oxide layer 20 and the semiconductor substrate 10, thereby providing the desired etch selectivity. In some embodiments, drift regions 22 may be formed in the semiconductor substrate 10 after the formation of the pad oxide layer 20 and before the etching process 91. A portion of each drift region 22 may be removed by the etching process 91 to form a trench 30. Two drift regions 22 may be located on opposite sides of the trench 30 in the horizontal direction D2, and a portion of each drift region 22 may be exposed by the trench 30. Then, as Figures 3 to 4 As shown, the shielding layer 24 can be removed after the trench 30 is formed.

[0077] like Figures 4 to 5 As shown, a first gate oxide layer 40 can be formed. In some embodiments, the first gate oxide layer 40 can be formed by an oxidation fabrication process such as in-situ steam generation (ISSG), a deposition fabrication process such as atomic layer deposition (ALD), or other suitable methods. For example, when the first gate oxide layer 40 is formed by an oxidation fabrication process, the first gate oxide layer 40 can be formed on the semiconductor substrate 10 exposed by the trench 30 and the drift region 22, and is not directly formed on the upper surface of the patterned oxide layer 20P. The first gate oxide layer 40 can be connected to the side of the patterned oxide layer 20P, but is not limited thereto. Furthermore, in some embodiments, the patterned oxide layer 20P can be patterned in a subsequent fabrication process to become the second gate oxide layer described above. Therefore, the thickness of the first gate oxide layer 40 (e.g., thickness T1 and / or thickness T2) can be less than the thickness of the patterned oxide layer 20P (e.g., thickness T3).

[0078] like Figures 5 to 6As shown, a gate material layer 50 can be formed on the semiconductor substrate 10. The gate material layer 50 can be partially formed in the trench 30 and partially formed outside the trench 30 (e.g., formed on the patterned oxide layer 20P), and the patterned oxide layer 20P can be located between the gate material layer 50 and the semiconductor substrate 10 in the vertical direction D1. In other words, the gate material layer 50 can be formed in the step of forming the trench 30 (e.g., ...). Figure 3 The first gate oxide layer 40 is formed after the etching process 91 shown, while the first gate oxide layer 40 can be formed after the etching process 91 and before the step of forming the gate material layer 50. In some embodiments, the gate material layer 50 may be formed substantially conformally on the patterned oxide layer 20P and in the trench 30, so that the upper surface of the gate material layer 50 may have a recessed surface corresponding to the trench 30 in the vertical direction D1, but is not limited thereto. The gate material layer 50 may include a non-metallic conductive material (e.g., doped polysilicon) or other suitable conductive material. In some embodiments, the gate material layer 50 may include multiple material layers (not shown), such as a conductive material layer and a dielectric material layer stacked together, and when the dielectric material layer is disposed on the conductive material layer, this dielectric material layer may be regarded as a gate capping layer, but is not limited thereto. Then, a patterned shielding layer 80 may be formed on the gate material layer 50, and a patterning process 92 may be performed on the gate material layer 50 and the patterned oxide layer 20P using the patterned shielding layer 80 as a shield.

[0079] like Figures 6 to 7 As shown, in some embodiments, the patterning process 92 may include one or more etching steps to etch the gate material layer 50 and the patterned oxide layer 20P, which are not covered by the patterned shielding layer 80, respectively, and the patterned shielding layer 80 may be removed after the patterning process 92. The gate material layer 50 may be patterned by the patterning process 92 to become the gate electrode 50G, and the patterned oxide layer 20P may be patterned by the patterning process 92 to become the second gate oxide layer 20S. In some embodiments, since the gate electrode 50G and the second gate oxide layer 20S can be formed by patterning the same shield (e.g., the patterned shielding layer 80) using the same shield, the sidewall SW1 of the gate electrode 50G and the sidewall SW2 of the second gate oxide layer 20S may be substantially flush with each other and may be considered together as the sidewalls of the gate structure GS, but this is not a limitation. Furthermore, in this invention, the method for forming the gate structure GS may include, but is not limited to, the methods described above. Figures 2 to 7 The steps shown are limited. In other words, other methods may be used to form a design as needed. Figure 7 and Figure 1 The gate structure GS shown is illustrated.

[0080] like Figure 7 and Figure 1 As shown, after forming the gate structure GS, a spacer structure 60 can be formed on the sidewalls (e.g., sidewalls SW1 and SW2) of the gate structure GS. Therefore, the spacer structure 60 can be located on the sidewall SW1 of the second portion P12 of the gate electrode 50G and the sidewall SW2 of the second gate oxide layer 20S. Then, the spacer structure 60 can be used as a shield to perform a doping process on the drift region 22 to form the source / drain region 70 in the drift region 22. In some embodiments, the spacer structure 60 can be formed by etching back the spacer material layer formed on the gate structure GS and the semiconductor substrate 10. Therefore, the spacer structure 60 can also be partially formed on the inner sidewall (e.g., sidewall SW3) of the gate structure GS, but is not limited thereto. In other words, the spacer structure 60 can also be formed on the sidewall of the gate structure GS using other suitable methods, but not on the inner sidewall of the gate structure GS.

[0081] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same components in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0082] Please see Figure 8 . Figure 8 The illustration shows a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 8 As shown, in the semiconductor device 102, a first portion P21 of the first gate oxide layer 40 may be disposed in the trench 30, and a second portion P22 of the first gate oxide layer 40 may be disposed in the vertical direction D1 between the second portion P12 of the gate electrode 50G and the second gate oxide layer 20S. In some embodiments, the first gate oxide layer 40 disposed outside the trench 30 may cover the inner sidewall and upper surface of the second gate oxide layer 20S and be in direct contact with the second gate oxide layer 20S, and the first gate oxide layer 40 disposed outside the trench 30 may be directly connected to the first portion P21 of the first gate oxide layer 40 disposed inside the trench 30. In some embodiments, the sidewall SW1 of the second portion P12 of the gate electrode 50G, the sidewall SW2 of the second gate oxide layer 20S, and the sidewall SW4 of the second portion P22 of the first gate oxide layer 40 can be substantially aligned with each other and can be regarded as the sidewalls of the gate structure GS. Therefore, the spacer wall structure 60 can be disposed on the sidewalls SW1, SW2, and SW4 and directly contact the sidewalls SW1, SW2, and SW4, but is not limited thereto.

[0083] Please see Figures 8 to 10 . Figure 9 and Figure 10 The illustration shows a schematic diagram of a method for manufacturing a semiconductor device 102 according to a second embodiment of the present invention. Figure 10 It is illustrated Figure 9 A schematic diagram of the subsequent situation. In some embodiments, Figure 8 It can be regarded as a drawing Figure 10 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 9 As shown, in some embodiments, the first gate oxide layer 40 can be formed by a deposition process (e.g., atomic layer deposition or other suitable deposition methods). Therefore, the first gate oxide layer 40 can be formed on the patterned oxide layer 20P and on the semiconductor substrate 10 and drift region 22 exposed by the trench 30. The first gate oxide layer 40 can cover the sides and top surface of the patterned oxide layer 20P and be directly connected to it, but is not limited thereto. After the first gate oxide layer 40 is formed, a gate material layer 50 and a patterned shielding layer 80 can be formed, and the patterned shielding layer 80 is used as a shield to perform a patterning process 92 on the gate material layer 50, the first gate oxide layer 40, and the patterned oxide layer 20P.

[0084] like Figures 9 to 10 As shown, in some embodiments, the patterning fabrication process 92 may include one or more etching steps to etch the gate material layer 50, the first gate oxide layer 40, and the patterned oxide layer 20P, which are not covered by the patterned shielding layer 80. In some embodiments, after the patterning fabrication process 92, the sidewalls SW1 of the gate electrode 50G, SW2 of the second gate oxide layer 20S, and SW4 of the second portion P22 of the first gate oxide layer 40 may be substantially flush with each other and may be considered together as the sidewalls of the gate structure GS, but are not limited thereto. Figure 10 and Figure 8 As shown, after forming the gate structure GS, a spacer structure 60 and a source / drain region 70 may be formed. In some embodiments, the spacer structure 60 may be formed on the sidewalls of the gate structure GS (e.g., sidewalls SW1, SW4, and SW2) and directly contact the sidewalls of the gate structure GS, but this is not a limitation.

[0085] In summary, in the semiconductor device and its fabrication method of the present invention, by disposing a portion of the gate structure in a trench of the semiconductor substrate, the area occupied by the semiconductor device in the vertical direction can be relatively reduced, thereby increasing the number and / or density of semiconductor devices. Furthermore, the relatively thick second gate oxide layer can be used to reduce the electric field at the edge of the gate structure, thereby improving the reliability and / or related electrical performance of the semiconductor device.

[0086] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, comprising: a semiconductor substrate; a trench disposed in the semiconductor substrate; and a gate structure disposed on the semiconductor substrate, wherein the gate structure comprises: a gate electrode, wherein a first portion of the gate electrode is disposed in the trench and a second portion of the gate electrode is disposed outside the trench; a first gate oxide layer disposed between the gate electrode and the semiconductor substrate, wherein at least a portion of the first gate oxide layer is disposed in the trench; and a second gate oxide layer disposed in a vertical direction between the second portion of the gate electrode and the semiconductor substrate, wherein a thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer, and sidewalls of the second portion of the gate electrode and sidewalls of the second gate oxide layer are flush with each other in the vertical direction.

2. The semiconductor device of claim 1, further comprising: two drift regions disposed in the semiconductor substrate and located on two opposite sides of the trench in a horizontal direction, respectively.

3. The semiconductor device of claim 2, wherein the first portion of the gate electrode is disposed between the two drift regions in the horizontal direction.

4. The semiconductor device of claim 3, wherein a portion of the first gate oxide layer is disposed between the first portion of the gate electrode and each of the drift regions in the horizontal direction.

5. The semiconductor device of claim 2, wherein the second gate oxide layer is disposed between the second portion of the gate electrode and each of the drift regions in the vertical direction.

6. The semiconductor device of claim 2, wherein a portion of each of the drift regions is disposed below the trench in the vertical direction.

7. The semiconductor device of claim 1, wherein a first portion of the first gate oxide layer is disposed in the trench and a second portion of the first gate oxide layer is disposed in the vertical direction between the second portion of the gate electrode and the second gate oxide layer.

8. The semiconductor device of claim 1, further comprising: a spacer structure disposed on sidewalls of the gate structure, wherein the spacer structure is disposed on sidewalls of the second portion of the gate electrode and sidewalls of the second gate oxide layer.

9. The semiconductor device of claim 1, wherein a material composition of the first gate oxide layer is different from a material composition of the second gate oxide layer.

10. The semiconductor device of claim 1, wherein the vertical direction is a thickness direction of the semiconductor substrate.

11. A method for fabricating a semiconductor device, comprising: forming a trench in a semiconductor substrate; and forming a gate structure on the semiconductor substrate, wherein the gate structure comprises: a gate electrode, wherein a first portion of the gate electrode is disposed in the trench and a second portion of the gate electrode is disposed outside the trench; a first gate oxide layer disposed between the gate electrode and the semiconductor substrate, wherein at least a portion of the first gate oxide layer is disposed in the trench; and a second gate oxide layer disposed in a vertical direction between the second portion of the gate electrode and the semiconductor substrate, wherein a thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer, and sidewalls of the second portion of the gate electrode and sidewalls of the second gate oxide layer are flush with each other in the vertical direction. ​ a second gate oxide layer disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction, wherein a thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer, and sidewalls of the second portion of the gate electrode and sidewalls of the second gate oxide layer are cut flush with each other in the vertical direction.

12. The method of claim 11, wherein the method of forming the gate structure comprises: forming a pad oxide layer on the semiconductor substrate; and performing an etching fabrication process on the pad oxide layer and the semiconductor substrate to form the trench, wherein the pad oxide layer is etched by the etching fabrication process to become a patterned oxide layer.

13. The method of claim 12, wherein the method of forming the gate structure further comprises: forming a gate material layer on the semiconductor substrate after the etching fabrication process, wherein the gate material layer is partially formed in the trench and partially formed outside the trench, and the patterned oxide layer is located between the gate material layer and the semiconductor substrate in the vertical direction; and performing a patterning fabrication process on the gate material layer and the patterned oxide layer, wherein the gate material layer is patterned by the patterning fabrication process to become the gate electrode, and the patterned oxide layer is patterned by the patterning fabrication process to become the second gate oxide layer.

14. The method of claim 13, wherein the method of forming the gate structure further comprises: forming the first gate oxide layer after the etching fabrication process and before forming the gate material layer.

15. The method of claim 12, further comprising: forming two drift regions in the semiconductor substrate after forming the pad oxide layer and before the etching fabrication process, wherein a portion of each of the drift regions is removed by the etching fabrication process to form the trench, and the two drift regions are located on two opposite sides of the trench in a horizontal direction.

16. The method of claim 15, wherein a bottom of each of the drift regions is lower than a bottom of the trench in the vertical direction.

17. The method of claim 15, wherein the first portion of the gate electrode is located between the two drift regions in the horizontal direction, and a portion of the first gate oxide layer is located between the first portion of the gate electrode and each of the drift regions in the horizontal direction.

18. The method of claim 15, wherein the second gate oxide layer is located between the second portion of the gate electrode and each of the drift regions in the vertical direction.

19. The method of claim 11, wherein a first portion of the first gate oxide layer is located in the trench, and a second portion of the first gate oxide layer is located between the second portion of the gate electrode and the second gate oxide layer in the vertical direction.

20. The method of claim 11, further comprising: A spacer structure is formed on the sidewalls of the gate structure, wherein the spacer structure is located on the sidewalls of the second portion of the gate electrode and on the sidewalls of the second gate oxide layer.

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