Power controller with soft entry and soft exit and control method

Abstract

A power controller and a control method for a power converter with soft turn-on and soft turn-off. The power converter includes an inductor element and a power switch for controlling an inductor current flowing through the inductor element. The power controller includes a voltage mode controller and a current mode controller. The voltage mode controller controls an on-time of the power switch based on a feedback signal and a sawtooth signal. The feedback signal is generated based on an output voltage of the power converter. The current mode controller controls the on-time based on a current limit signal and a current sense signal to limit the current sense signal. The current sense signal represents the inductor current. The current mode controller includes a limit signal generator for providing the current limit signal based on the feedback signal and a triangular wave signal and determining a soft turn-on time and a soft turn-off time. The limit signal generator increases the current limit signal over time during the soft turn-on time and decreases the current limit signal over time during the soft turn-off time.

Description

TECHNICAL FIELD

[0001] The present application generally relates to a control method of a switching power converter and a related controller, and more particularly, to a power controller and a control method with soft entry and soft exit in a power saving mode. BACKGROUND

[0002] In the modern society, energy saving is always a concern. The conversion efficiency of a power converter is always a focus. Not only the conversion efficiency in heavy load is concerned, but also the conversion efficiency in light load or no load is concerned. The power converter must be able to save power as much as possible to increase the conversion efficiency.

[0003] For high power applications, LLC resonant power converter is a switching power supply with excellent conversion efficiency. LLC resonant power converter can make its main two power switches to switch at zero voltage, which reduces the conduction loss. Therefore, in heavy load or medium load, the conversion efficiency is quite high.

[0004] However, the switching frequency of LLC resonant power converter increases as the load decreases. Therefore, in no load, the switching loss is high, which makes the conversion efficiency low. SUMMARY

[0005] The present application provides a control method for a power converter. The power converter includes a power switch and an inductor. The power switch is used to control an inductor current flowing through the inductor. A current detection signal represents the inductor current. When operating in a non-power saving mode, an on-time of the power switch is controlled according to a feedback signal and a sawtooth signal, so that the power converter operates in a voltage control mode. The feedback signal is generated according to an output voltage of the power converter. When operating in a power saving mode, the power switch is continuously switched for a cluster time, and maintained off for an interrupt time. The cluster time includes a soft entry time and a soft exit time. A current limit signal is compared with the current detection signal to control the on-time to limit the current detection signal. In the soft entry time, the current limit signal is increased with time. In the soft exit time, the current limit signal is decreased with time.

[0006] This invention provides a power controller suitable for a power converter. The power converter includes an inductor and a power switch. The power switch controls an inductor current flowing through the inductor. The power controller includes a voltage-mode controller and a current-mode controller. The voltage-mode controller controls an on-time of the power switch based on a feedback signal and a sawtooth signal. The feedback signal is generated based on an output voltage of the power converter. The current-mode controller controls the on-time based on a current limit signal and a current detection signal to limit the current detection signal. The current detection signal represents the inductor current. The current-mode controller includes a limit signal generator that provides the current limit signal based on the feedback signal and a triangular wave signal, and determines a soft-entry time and a soft-exit time. During the soft-entry time, the limit signal generator increases the current limit signal over time, and during the soft-exit time, the limit signal generator decreases the current limit signal over time. Attached Figure Description

[0007] Figure 1 This is a dual-output LLC resonant power converter 100 implemented according to the present invention.

[0008] Figure 2 This shows the LLC controller 102 implemented according to the present invention.

[0009] Figure 3 The control method M01 according to the present invention is applicable to LLC controller 102.

[0010] Figure 4 Displays some signal waveforms of the LLC controller 102 in non-power-saving mode.

[0011] Figure 5 show Figure 2 Limiting signal generator 222 in the middle.

[0012] Figure 6 The display shows some signal waveforms of the LLC controller 102 when operating in power-saving mode.

[0013] Figure 7 It corresponds to the input power supply V IN The current detection signal V at 110V CS Waveform.

[0014] Figure 8 The display shows some signal waveforms of the LLC controller 102 during the process of exiting the power saving mode.

[0015] [Symbol Explanation]

[0016] 100 LLC resonant power converter

[0017] 102 LLC controller

[0018] 108 detection circuit

[0019] 210H upper arm control circuit

[0020] 210L lower arm control circuit

[0021] 212 voltage mode controller

[0022] 214 current mode controller

[0023] 216 sawtooth generator

[0024] 218 comparator

[0025] 220 minimum on time generator

[0026] 222 limit signal generator

[0027] 223 comparator

[0028] 224 burst frequency controller

[0029] 226 up / down controller

[0030] 227 blanker

[0031] 228 up / down counter

[0032] 230 digital to analog converter

[0033] 1041, 1042 load

[0034] 1061, 1062 feedback circuit

[0035] 1064 power saving signal path

[0036] BI enter pulse

[0037] BO exit pulse

[0038] BST burst pin

[0039] CA capacitor

[0040] CL capacitor

[0041] CO1, CO2 output capacitor

[0042] CODE count

[0043] CODE MAX maximum signal

[0044] CODEMIN minimum signal

[0045] D1, D2 diode

[0046] FB1, FB2 feedback pin

[0047] f BST cluster frequency

[0048] GND IN ground line

[0049] HS upper arm switch

[0050] I D1 , I D2 induced current

[0051] I Lr inductive current

[0052] LP primary winding

[0053] Lr, Lm inductance

[0054] LS lower arm switch

[0055] LS1, LS2 secondary winding

[0056] M01 control method

[0057] ND connection point

[0058] PS SEC power saving signal

[0059] RA resistance

[0060] RSNT resonant circuit

[0061] S02, S04, S06, S08, S10, S12, S14, S16 step

[0062] SCM pulse

[0063] S LG lower arm control signal

[0064] S HG upper arm control signal

[0065] SMIN minimum on-time pulse

[0066] SVM pulse

[0067] SVON pulse

[0068] t0 time

[0069] T BI soft entry time

[0070] T BO Soft-off time

[0071] T BRK Interrupt time

[0072] T BST Cluster time

[0073] TF transformer

[0074] TON HG , TON LG On time

[0075] T PSCYC Pre-set period

[0076] V BST Cluster signal

[0077] V CS Current detection signal

[0078] VCSL HG Current limit signal

[0079] VCSL HGMAX Cluster maximum current signal

[0080] V FB1 , V FB2 Feedback signal

[0081] V IN Input power supply

[0082] V O1 , V O2 Output power supply

[0083] VRAMP triangular wave signal

[0084] VSAW HG Sawtooth signal DETAILED DESCRIPTION

[0085] In this specification, there are some same symbols, which represent elements having the same or similar structure, function, principle, and can be known by those skilled in the art according to the teachings of this specification. For the simplicity of this specification, the same symbol elements will not be restated.

[0086] Although the present application is exemplified by a dual-output LLC resonant power converter, the present application is not limited thereto. In other embodiments, the present application can also be used in any other type of resonant power converter or pulse-width-modulation (PWM) power converter.

[0087] In one embodiment of the present application, a power controller controls an upper arm switch and a lower arm switch in an LLC resonant power converter. The upper arm switch and the lower arm switch are power switches. A transformer is an inductive element. The power controller controls the upper arm switch according to a feedback signal, which is generated according to an output voltage of the LLC resonant power converter. The power controller receives a current detection signal, which represents an inductor current flowing through the transformer.

[0088] When the LLC resonant power converter drives a heavy load, it operates in a non-power saving mode. The power controller controls an on-time of the power switches according to the feedback signal and a sawtooth signal, so that the power converter operates in a voltage-control mode.

[0089] When the LLC resonant power converter drives no load (i.e. no load), it operates in a burst mode as a power saving mode. The power controller causes the upper arm switch to switch continuously for a burst time and to maintain off for an interrupt time. The burst time has a soft burst-in time at the beginning and a soft burst-out time at the end. During the soft burst-in time and the soft burst-out time, the power controller controls the on-time of the upper arm switch in a current-control mode, i.e. compares a current limit signal with the current detection signal to control the upper arm switch. During the soft burst-in time, the power controller increases the current limit signal with time to achieve soft burst-in. During the soft burst-out time, the power controller decreases the current limit signal with time to achieve soft burst-out.

[0090] In one embodiment of the present application, the sum of the burst time and the interrupt time is a fixed preset period, which is the inverse of a burst frequency. Soft burst-in and soft burst-out can avoid sudden energy change when entering and leaving the burst time, which can cause uncomfortable audio noise.

[0091] Figure 1 A dual-output LLC resonant power converter 100 is implemented according to the present application. The LLC resonant power converter 100 converts an input power V IN into output powers V O1 and V O2 to power loads 1041 and 1042 respectively.

[0092] An upper arm switch HS and a lower arm switch LS are electrically connected in series between the input power V IN and a ground line GND INBetween these components, a resonant circuit RSNT is driven, causing RSNT to oscillate. The resonant circuit RSNT includes a transformer TF and a capacitor CL. The primary winding LP of the transformer TF is inductively coupled to the two secondary windings LS1 and LS2. The inductances Lr and Lm in the transformer TF represent the series leakage inductance and parallel leakage inductance of the primary winding LP, respectively. The primary winding LP and the capacitor CL are connected in series through the connection point ND. In other embodiments, the resonant circuit RSNT can have different architectures and is not limited to these. Figure 1 The structure is as follows. Both the upper arm switch HS and the lower arm switch LS can control the inductor current I flowing through the inductor Lr. Lr .

[0093] When the resonant circuit RSNT oscillates, the secondary windings LS1 and LS2 will generate an induced current I. D1 with I D2 Through rectification by diodes D1 and D2, an output power supply V can be established across output capacitors CO1 and CO2. O1 With V O2 .

[0094] Output power V O1 With V O2 Feedback signals V can be generated through feedback circuits 1061 and 1062 respectively. FB1 With V FB2 LLC controller 102 provides upper arm control signal S HG With lower arm control signal S LG These control the upper arm switch HS and the lower arm switch LS respectively. Based on the feedback signals V on feedback pins FB1 and FB2... FB1 With V FB2 The LLC controller 102 can determine the ON time (TON) of the upper arm switch HS and the lower arm switch LS. HG With TON LG That is, the conduction time of the upper arm switch HS and the lower arm switch LS.

[0095] The LLC resonant power converter 100 includes a detection circuit 108, which includes a resistor RA and a capacitor CA, connected to each other as follows: Figure 1 As shown in the example, the detection circuit 108 is connected to the connection point ND to detect the voltage across the capacitor CL in the resonant circuit RSNT, thereby generating a current detection signal V. CS It can represent the inductor current I. Lr Current detection signal V CS This is just one type of detection signal. In other embodiments, the detection circuit 108 may have a different architecture, providing a signal different from the current detection signal V. CS The detection signal.

[0096] exist Figure 1 In this circuit, the secondary side circuit can provide a power-saving signal PS according to system requirements. SEC A cluster signal V is generated on the primary side via the power-saving signal channel 1064. BST The LLC controller 102 is instructed to enter a power-saving mode via the cluster pin (BST). For example, when the secondary-side circuitry requires the entire LLC resonant power converter 100 to enter a power-saving mode, the cluster signal V is activated through the power-saving signal channel 1064. BST It is a fixed value greater than 1V; to enter a non-power-saving mode, the secondary-side circuit makes the cluster signal V... BST Less than 1V.

[0097] For example, feedback circuits 1061 and 1062, as well as power-saving signal channel 1064, each have an optocoupler for transmitting signals between the isolated primary and secondary sides.

[0098] Figure 2 The LLC controller 102 implemented according to the present invention includes an upper arm control circuit 210H and a lower arm control circuit 210L. For the sake of simplicity, Figure 2 The image only shows details about the upper arm control circuit 210H, while in the embodiment, the lower arm control circuit 210L may share some of the circuitry in the upper arm control circuit 210H.

[0099] The upper arm control circuit 210H includes a voltage-mode controller 212 and a current-mode controller 214. The lower arm control signal S... LG After a dead time has elapsed since the lower arm switch LS was closed, the voltage-mode controller 212 and the current-mode controller 214 each generate pulses SVM and SCM to turn on the upper arm switch HS. The pulse widths of SVM and SCM are respectively the voltage-mode turn-on time TON. VM With current mode turn-on time TON CM .from Figure 2 It can be seen that the opening time TON of the upper arm switch HS is... HG It will be the voltage mode activation time TON VM With current mode turn-on time TON CM The shorter one.

[0100] The voltage-mode controller 212 includes, but is not limited to, a sawtooth wave generator 216, a comparator 218, a minimum on-time generator 220, and a shut-off device 227. The voltage-mode controller 212 operates based on a feedback signal V. FB2 and the sawtooth signal VSAW provided by the sawtooth wave generator 216HG to generate a pulse SVON for controlling the turn-on time TON of the upper arm switch HS HG The comparator 218 compares the sawtooth signal VSAW HG with the feedback signal V FB2 The minimum turn-on time generator 220 provides a minimum turn-on time pulse SMIN defining a minimum turn-on time TON MIN The shutoff 227 passes the pulse SVON when the bunch signal V BST is identified to operate in a non-power saving mode; and blocks the pulse SVON when the bunch signal V HG is identified to operate in a power saving mode. It will be explained later that in the non-power saving mode, the turn-on time TON HG of the upper arm control signal S MIN is not less than the minimum turn-on time TON HG ; and in the power saving mode, the turn-on time TON HG of the upper arm control signal S MIN is not more than the minimum turn-on time TON FB2 .

[0101] The current mode controller 214 has, but is not limited to, a limit signal generator 222 and a comparator 223. The limit signal generator 222 provides a current limit signal VCSL BST in accordance with the feedback signal V HG and the bunch signal V HG The comparator 223 generates a pulse SCM by comparing the current limit signal VCSL CS with the current detection signal V BST .

[0102] Figure 3 It is shown that the control method M01 in accordance with the present application is applicable to the LLC controller 102.

[0103] Please refer to Figure 2 and Figure 3 . The step S02 judges whether to enter the power saving mode. For example, Figure 2 the LLC controller 102 in the LLC resonant power converter 100 in the present application identifies that the LLC resonant power converter 100 is to enter the power saving mode when the bunch signal V BST is greater than 1V. The LLC controller 102 can also identify that the LLC resonant power converter 100 is to enter the power saving mode when both the feedback signal V FB1 and V FB2 are low, for example, are both lower than 1V. When the bunch signal V BST is greater than 1V, the LLC controller 102 provides a preset bunch maximum current signal VCSL BST in accordance with the bunch signal V HGMAX .This is used to roughly limit the maximum current sensing signal V in power-saving mode. CS In power-saving mode, steps S04 and S06 follow step S02 until step S08 confirms the need to exit power-saving mode. In one embodiment, if the cluster signal V BST Less than 1V, and the feedback signal V FB1 With V FB2 Both are too high. Step S10 continues with step S02, maintaining operation in a non-power-saving mode.

[0104] Step S10 operates in non-power-saving mode, causing the current mode on-time TON to be reduced. CM The maximum also makes the voltage mode on-time TON VM Not less than the minimum on time TON MIN Please see. Figure 2 and Figure 4 , Figure 4 This displays some signal waveforms of the LLC controller 102 during operation in non-power-saving mode. In normal non-power-saving mode, Figure 2 Current limiting signal VCSL HG Very high, the opening time TON of the upper arm switch HS is high. HG The time will be determined by the pulse SVON generated by the voltage mode controller 212, but will not be less than the minimum on-time TON. MIN In other words, the start time is TON. HG Roughly composed of sawtooth signal VSAW HG With feedback signal V FB2 The decision, as Figure 4 As shown. This is called voltage control mode. Although Figure 4 The on-time TON of the lower arm switch LS is not displayed. LG It is also caused by another sawtooth signal and feedback signal V FB1 The decision is made when the feedback signal V... FB2 When fixed, the start time is TON. HG It is also fixed and does not change with the input power supply V. IN It changes with the voltage value.

[0105] Figure 5 show Figure 2 The limiting signal generator 222 in the middle. The limiting signal generator 222 has a cluster frequency controller 224, an up / down counter 226, an up / down counter 228, and a digital-to-analog converter 230. The cluster frequency controller 224 is based on the feedback signal V FB2The input pulse BI and output pulse BO are provided to the up / down counter 226. The up / down counter 226 controls the up / down counter 228 based on various signals, causing it to count up, count down, or stop counting. The up / down counter 228 can have an overflow prevention function. When the count CODE reaches its maximum or minimum value, the up / down counter 228 automatically stops counting and releases the maximum value signal CODE. MAX Or minimum value signal CODE MIN The up / down controller 226 is notified. The digital-to-analog converter 230 converts the count CODE into an analog current limit signal VCSL. HG In one embodiment, another digital-to-analog converter may also generate a current-limiting signal VCSL based on a count CODE. LG To control the opening time TON of the lower arm switch LS. LG With current detection signal V CS .

[0106] Figure 6 The display shows some signal waveforms of the LLC controller 102 when operating in power-saving mode. (Similar to...) Figure 6 As shown, the LLC controller 102 uses cluster mode as a power-saving mode. Cluster mode allows the upper arm switch HS and the lower arm switch LS to continuously switch cluster times T. BST Then maintain the interrupt time T. BRK And let the clustering time T BST With interruption time T BRK Alternating, like Figure 6 As shown. LLC controller 102 enables a clustering time T BST With an interruption time T BRK The sum is approximately equal to a fixed preset period T. PSCYC It is equal to the cluster frequency f of the triangular wave signal VRAMP. BST The reciprocal of. For example, the cluster frequency f BST It is approximately 800Hz, with a preset period T. PSCYC Approximately 1.25 ms. Fixed clustering frequency f BST This allows the device that supplies power to the transformer TF, such as the LLC controller 102, to operate in each preset cycle T. PSCYC The internal power supply will be guaranteed to prevent the LLC controller 102 from waiting for too long and failing due to power depletion.

[0107] As previously mentioned, in power-saving mode, Figure 2 The interruptor 227 blocks the pulse SVON, so the pulse width of the pulse SVM is fixed to the minimum on-time TON. MIN Therefore, the upper arm control signal S HGthe turn-on time TON of the upper arm switch HS HG not greater than the minimum turn-on time TON MIN .

[0108] Figure 6 the cluster time T BST the soft turn-in time T BI and the soft turn-out time T BO . During the soft turn-in time T BI , the current limit signal VCSL HG increases with time, the turn-on time TON of the upper arm switch HS HG and the turn-on time TON of the lower arm switch LS LG also gradually increase with the switching cycle. During the soft turn-out time T BO , the current limit signal VCSL HG decreases with time, the turn-on time TON HG and the turn-on time TON LG also gradually decrease with the switching cycle. The soft turn-in and the soft turn-out can avoid the sudden energy change that can cause the unpleasant audio noise when the cluster time T BST .

[0109] Please refer to Figure 3 , Figure 5 and Figure 6 . Figure 5 The cluster frequency controller 224 internally provides a triangular wave signal VRAMP with a fixed cluster frequency f BST and decides whether to generate the turn-in pulse BI and the turn-out pulse BO according to the feedback signal V FB2 and the triangular wave signal VRAMP (steps S04 and S06).

[0110] When the feedback signal V FB2 is higher than the triangular wave signal VRAMP, the cluster frequency controller 224 provides the turn-in pulse BI to start the soft turn-in time T BI , executes step S12 to implement the soft turn-in. Step S12 enables the pulse width modulation (PWM), that is, makes the upper and lower arm switches HS and LS start to stagger the turn-on to start the cluster time T BST . Step S12 also makes the current limit signal VCSL HG start to increase with time until it is greater than or equal to the cluster maximum current signal VCSL HGMAX . Step S12 also makes the turn-on time TON of the upper arm switch HS HG not greater than the minimum turn-on time TON MIN . For example, when the turn-in pulse BI is received,Figure 5 up-down counter 226 starts up-counting with the up-arm control signal S HG as a clock, and gradually increases the count CODE. The digital-to-analog converter 230 converts the count CODE into an analog current limit signal VCSL HG . Therefore, the current limit signal VCSL HG will increase with time. When the up-down counter 226 finds that the current limit signal VCSL HG is greater than or equal to the cluster maximum current signal VCSL HGMAX (corresponding to the cluster signal V BST ), the up-down counter 226 stops up-counting of the up-down counter 228, and ends the soft-entry time T BI . Thereafter, both the count CODE and the current limit signal VCSL HG are maintained constant, as shown in Figure 6 . Figure 2 The blocker 227 blocks the pulse SVON, so that the on-time TON HG of the up-arm control signal S HG is not greater than the minimum on-time TON MIN .

[0111] When the feedback signal V FB2 is lower than the triangular wave signal VRAMP, the cluster frequency controller 224 provides an exit pulse BO, starts a soft-exit time T BO , and performs step S14 to implement soft-exit. Step S14 causes the on-time TON HG of the up-arm switch HS to be not greater than the minimum on-time TON MIN ; causes the current limit signal VCSL HG to start decreasing with time until it is less than or equal to a preset minimum current signal; and disables PWM, i.e., causes the up-arm and down-arm switches HS and LS to stop interleaved on, or both to be maintained off, when the current limit signal VCSL HG is less than or equal to the preset minimum current signal. For example, Figure 2 The blocker 227 blocks the pulse SVON, so that the on-time TON HG of the up-arm control signal S HG is not greater than the minimum on-time TON MIN . When the exit pulse BO is received, Figure 5 the up-down counter 226 starts down-counting with the up-arm control signal S HG as a clock, and gradually decreases the count CODE. Therefore, the current limit signal VCSL HG will decrease with time. When the up-down counter 226 finds that the count CODE is less than or equal to the minimum code signal CODEMIN , the count CODE has reached the minimum, the up and down counters 228 are stopped and the PWM is disabled, causing both the upper and lower arm switches HS and LS to remain off, and the soft entry time T Figure 6 BRK The minimum count CODE corresponds to the minimum current limit signal VCSL HG , which is the preset minimum current signal.

[0112] After the soft entry time T BI and before the next soft exit time T BO , the PWM is enabled and the on-time TON HG of the upper arm control signal S HG is determined by the constant current limit signal VCSL HG , but not more than the minimum on-time TON MIN . During the interrupt time T BRK , i.e. after the soft exit time T BO and before the soft entry time T BI , the PWM is disabled and both the upper and lower arm switches HS and LS remain off, as shown in Fig. 4. Figure 6

[0113] Figure 6 It is shown that the current detection signal V CS may reach the current limit signal VCSL HG , indicating that the on-time TON HG of the upper arm control signal S HG is determined by the current mode controller 214, but the present application is not limited thereto. Figure 7 It is shown that during the cluster time T BST , the current detection signal V CS may not reach the current limit signal VCSL HG . As previously described, in the power saving mode, the on-time TON HG of the upper arm control signal S HG will not be more than the minimum on-time TON MIN defined in the voltage mode controller 212. Therefore, it is possible that at the last stage of the soft entry time T BI , the current mode on-time TON CM defined by the current mode controller 214 has exceeded the minimum on-time TON MIN , and the on-time TON HG can only be maintained at the minimum on-time TON MIN . In other words, the current detection signal V CS may not reach the current limit signal VCSL HG ​​,as Figure 7 As shown. For example, Figure 6 and 7 These correspond to the input power supply V. IN These are the signal waveforms at 237V and 110V. High input power supply V. IN It is relatively easy to make the current detection signal V CS Top current limit signal VCSL HG .

[0114] Step S08 determines whether to exit power saving mode. For example, Figure 2 The LLC controller 102 in the cluster signal V BST When it is less than 1V, and the feedback signal V FB1 With V FB2 If both values ​​are greater than 1V, it is determined that the LLC resonant power converter 100 needs to exit the power-saving mode. If there is no need to exit the power-saving mode, steps S04 and S06 continue to be executed; if it is determined that the power-saving mode needs to be exited, step S16 continues to be executed.

[0115] Step S16 is essentially the switching process from power-saving mode to non-power-saving mode. First, step S16 enables the PWM, which means that the upper and lower arm switches HS and LS begin to alternately activate. In one embodiment, the upper / lower counting controller 226 executes step S16, causing the upper / lower counter 228 to count down first, until the count CODE reaches its minimum (which can be determined by the minimum value signal CODE). MIN When this is known, the up and down counter 228 starts counting up until the count CODE reaches its maximum (which can be determined by the maximum value signal CODE). MAX Only after learning this did the upper and lower counters 228 stop counting. Figure 8 The cluster signal V is displayed at time t0. BST The voltage drops to approximately 0V, so step S16 begins, exiting power-saving mode. (Similar to...) Figure 8 As shown, because the up / down counter 228 counts down first and then up, the current limit signal VCSL... HG First, the voltage decreases in steps. Then, after reaching approximately 0V, it increases in steps, eventually settling at a fixed value corresponding to the highest value of the counter. Figure 8 In the middle, the current detection signal V CS The peak value initially follows the current limit signal VCSL. HG The change is limited by the feedback signal V. FB2 The determined opening time TON HG (that is, the on-time TON under voltage control mode) HG Therefore, the final current detection signal V CS The peak value will not follow the current limit signal VCSL HG .

[0116] Although in the above embodiments, the increase and decrease of the current limit signal VCSL HG is generated by the up / down counter 228 in cooperation with the digital-to-analog converter 230, the present application is not limited thereto. In an embodiment, the limit signal generator 222 can charge or discharge a capacitor with a current source, and the resulting capacitor voltage can be used as the current limit signal VCSL HG . For example, in the soft entry time T BI , a current source charges a capacitor, so the capacitor voltage gradually rises to be used as the current limit signal VCSL HG , achieving soft entry. In the soft exit time T BO , another current source discharges the capacitor, so the capacitor voltage gradually falls to be used as the current limit signal VCSL HG , achieving soft exit.

[0117] In embodiments of the present application, because of the soft entry and soft exit, it is possible that there is no annoying audio noise in the power saving mode. Moreover, the fixed burst frequency can make the operating power of the LLC controller 102 more stable.

[0118] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A control method for a power converter, the power converter comprising a power switch and an inductor, the power switch being used to control an inductor current flowing through the inductor, the control method comprising: providing a current detection signal representing the inductor current; when operating in a non-power saving mode, controlling an on-time of the power switch according to a feedback signal and a sawtooth signal to cause the power converter to operate in a voltage control mode, wherein the feedback signal is generated according to an output voltage of the power converter; and when operating in a power saving mode, performing the following steps: causing the power switch to be continuously switched for a burst time and maintaining an off-interrupt time, the burst time comprising a soft-in time and a soft-out time; comparing a current limit signal with the current detection signal to control the on-time to limit the current detection signal; during the soft-in time, increasing the current limit signal over time; and during the soft-out time, decreasing the current limit signal over time. when operating in the non-power saving mode, the on-time is not less than a minimum on-time, and when operating in the power saving mode, the on-time is not greater than the minimum on-time.

2. The control method of claim 1, wherein, when operating in the power saving mode, a sum of the burst time and the off-interrupt time is a fixed preset value.

3. The control method of claim 1, wherein, 4. The control method of claim 1, comprising: during the soft-in time, increasing the current limit signal with switching of the power switch.

5. The control method of claim 1, comprising: during the soft-out time, decreasing the current limit signal with switching of the power switch.

6. A power controller for a power converter, the power converter comprising an inductor and a power switch, the power switch being used to control an inductor current flowing through the inductor, the power controller comprising: a voltage mode controller controlling an on-time of the power switch according to a feedback signal and a sawtooth signal, wherein the feedback signal is generated according to an output voltage of the power converter; and a current mode controller controlling the on-time according to a current limit signal and a current detection signal to limit the current detection signal, wherein the current detection signal represents the inductor current, comprising: during the soft-in time, the limit signal generator increasing the current limit signal over time, and during the soft-out time, the limit signal generator decreasing the current limit signal over time. The limiting signal generator provides the current limiting signal according to the feedback signal and the triangular wave signal, and determines the soft entry time and the soft exit time, wherein, the limit signal generator comprising:

7. The power controller of claim 6, wherein, a burst frequency controller providing a soft-in signal and a soft-out signal according to the feedback signal and the triangular wave signal to indicate a start of the soft-in time and the soft-out time, respectively; an up-down counter providing a count; an up-down number controller controlling the up-down counter according to the soft-in signal and the soft-out signal; and a digital-to-analog converter providing the current limit signal according to the count. the up-down number controller providing a burst maximum current signal according to a burst signal, and during the soft-in time, the limit signal generator increasing the current limit signal over time until the burst maximum current signal. ​ 8. The power controller of claim 7, wherein, ​ 9. The power controller of claim 6, wherein, During the soft turn-off time, the limiting signal generator decreases the current limiting signal over time to a preset minimum current signal.

10. The power controller of claim 6, wherein, The triangular wave signal has a preset fixed frequency.

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