Array substrate, method for preparing same, and display device

Abstract

An array substrate, a manufacturing method thereof, and a display device. The array substrate includes a plurality of gate lines (20) and a plurality of data lines (50) disposed on a substrate (11). The plurality of gate lines (20) extend along a first direction, and the plurality of data lines (50) extend along a second direction. A plurality of sub-pixels are defined by the intersection of the plurality of gate lines (20) and the plurality of data lines (50). Each sub-pixel includes a thin film transistor (10), a pixel electrode (80), and a common electrode (90). The common electrode (90) in one sub-pixel is connected to the common electrode (90) in an adjacent sub-pixel through a common connection portion (110). The common connection portion (110) and the gate line (20) have a first overlapping region. In the first direction, the first overlapping region has a first width, and in the second direction, the first overlapping region has a second width. The first width is less than the second width.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technologies, and particularly relates to an array substrate, a method for manufacturing the same, and a display device. Background Art

[0002] Liquid Crystal Displays (LCDs) have been rapidly developed due to their small size, low power consumption, and no radiation. A liquid crystal display panel includes a Thin Film Transistor (TFT) substrate of a cell and a Color Filter (CF) substrate. Liquid Crystal (LC) molecules are disposed between the array substrate and the color filter substrate. By controlling the common electrode and the pixel electrode, an electric field for driving the liquid crystal to deflect is formed to achieve grayscale display. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0004] In one aspect, the present disclosure provides an array substrate, including a plurality of gate lines and a plurality of data lines disposed on a substrate. The plurality of gate lines extend along a first direction and are sequentially arranged in a second direction. The plurality of data lines extend along the second direction and are sequentially arranged in the first direction. A plurality of sub-pixels are defined by the intersection of the plurality of gate lines and the plurality of data lines. Each sub-pixel includes at least a thin film transistor, a pixel electrode, and a common electrode. The first direction intersects with the second direction. The common electrode in at least one sub-pixel is connected to the common electrode in an adjacent sub-pixel in the second direction through a common connection portion. A first overlapping region is formed between the positive projection of the common connection portion on the substrate and the positive projection of the gate line on the substrate. In the first direction, the first overlapping region has a first width, and in the second direction, the first overlapping region has a second width. The first width is less than the second width.

[0005] In an exemplary embodiment, the first width is 10% to 20% of the second width.

[0006] In an exemplary embodiment, the first width is 5 μm to 8 μm.

[0007] In an exemplary embodiment, the pixel electrode in at least one sub-pixel includes at least a pixel base portion and a pixel comb portion. The pixel comb portion includes a plurality of pixel strip electrodes, and the plurality of pixel strip electrodes are disposed on a side of the pixel base portion away from the gate line; the common electrode in at least one sub-pixel includes at least a common base portion and a common comb portion. The common comb portion includes a plurality of common strip electrodes, and the plurality of common strip electrodes are disposed on a side of the common base portion close to the gate line; a first end of the plurality of pixel strip electrodes is connected to the pixel base portion, and a second end of the plurality of pixel strip electrodes extends in a direction toward the common base portion; a first end of the plurality of common strip electrodes is connected to the common base portion, and a second end of the plurality of common strip electrodes extends in a direction toward the pixel base portion; in the first direction, the pixel strip electrodes and the common strip electrodes are alternately arranged.

[0008] In an exemplary embodiment, the pixel electrode in at least one sub-pixel further includes a pixel connection portion. The pixel connection portion is disposed on a side of the pixel base portion close to the gate line and is connected to the drain electrode of the thin film transistor through a via hole; a first distance between an edge of the pixel connection portion close to the common connection portion and an edge of the common connection portion close to the pixel connection portion is from 20 μm to 50 μm, and the first distance is a dimension in the first direction.

[0009] In an exemplary embodiment, the common electrode in at least one sub-pixel further includes a common shielding portion. The common shielding portion of the present sub-pixel is connected to the common base portion of the sub-pixel in the next row through the common connection portion.

[0010] In an exemplary embodiment, there is a second distance between an edge of the common base portion of the present sub-pixel away from the sub-pixel in the previous row and an edge of the gate line of the sub-pixel in the previous row close to the present sub-pixel. There is a third distance between an end of the pixel strip electrode close to the common base portion and an edge of the common base portion close to the pixel strip electrode. The second distance is greater than the third distance, and the second distance and the third distance are dimensions in the second direction.

[0011] In an exemplary embodiment, the second distance is from 5 μm to 7 μm.

[0012] In an exemplary embodiment, the third distance is from 3.5 μm to 4.5 μm.

[0013] In an exemplary embodiment, a fourth distance between an end of the pixel comb portion of the present sub-pixel close to the gate line of the sub-pixel in the previous row and an edge of the gate line of the sub-pixel in the previous row close to the pixel comb portion of the present sub-pixel is from 9.0 μm to 11.5 μm.

[0014] In an exemplary embodiment, the first substrate further includes a black matrix shielding region, and a positive projection of the black matrix shielding region on the substrate includes positive projections of the gate lines and the data lines on the substrate; in the second direction, a fifth distance between a first edge of the black matrix shielding region closer to the gate line and an edge of the gate line closer to the first edge is 5 μm to 7 μm.

[0015] In an exemplary embodiment, at least one sub-pixel further includes a common electrode line extending along the first direction, and the common electrode is connected to the common electrode line through a via hole.

[0016] In an exemplary embodiment, at least one sub-pixel further includes a common connection line extending along the second direction, and the common electrode is connected to both the common electrode line and the common connection line through via holes.

[0017] In an exemplary embodiment, at least one sub-pixel further includes at least one shielding line, a first end of the shielding line is connected to the common electrode line, and a second end of the shielding line extends in a direction away from the common electrode line.

[0018] In an exemplary embodiment, at least one sub-pixel further includes a gate connection line extending along the second direction, and the gate connection line is connected to the gate line.

[0019] In an exemplary embodiment, at least one sub-pixel further includes a gate connection electrode, and the gate connection electrode is connected to both the gate connection line and the gate line through via holes respectively.

[0020] On the other hand, the present disclosure also provides a display device, including a first substrate and a second substrate disposed opposite to each other, the first substrate includes the array substrate as described above, the second substrate at least includes a black matrix, and a positive projection of the black matrix on the substrate includes positive projections of the gate lines and the data lines on the substrate; in the second direction, a fifth distance between a first edge of the black matrix closer to the gate line and an edge of the gate line closer to the first edge is 5 μm to 7 μm.

[0021] In yet another aspect, the present disclosure also provides a method for manufacturing an array substrate, including:

[0022] Forming a plurality of gate lines and a plurality of data lines on a substrate, the plurality of gate lines extend along a first direction and are sequentially arranged in a second direction, the plurality of data lines extend along the second direction and are sequentially arranged in the first direction, a plurality of sub-pixels defined by intersections of the plurality of gate lines and the plurality of data lines, the sub-pixels at least include thin film transistors, and the first direction and the second direction intersect;

[0023] A pixel electrode and a common electrode are formed. The common electrode in at least one sub-pixel is connected to the common electrode in an adjacent sub-pixel in the second direction through a common connection portion. A positive projection of the common connection portion on the substrate and a positive projection of the gate line on the substrate have a first overlapping region. In the first direction, the first overlapping region has a first width, and in the second direction, the first overlapping region has a second width, and the first width is less than the second width.

[0024] Other aspects will be apparent after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are used to provide an understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation to the technical solutions of the present disclosure.

[0026] Figure 1 is a schematic cross-sectional structure diagram of a display device;

[0027] Figure 2 is a schematic plan view structure diagram of a display device;

[0028] Figure 3 is a schematic plan view structure diagram of an array substrate;

[0029] Figure 4 is a schematic plan view structure diagram of an array substrate according to an exemplary embodiment of the present disclosure;

[0030] Figure 5 is Figure 4 a schematic plan view structure diagram of the pixel electrode in

[0031] Figure 6 is Figure 4 a schematic plan view structure diagram of the common electrode in

[0032] Figure 7 is a schematic diagram of the array substrate of the present disclosure after forming the first conductive layer pattern;

[0033] Figure 8 is a schematic diagram of the array substrate of the present disclosure after forming the semiconductor layer pattern;

[0034] Figure 9 is a schematic diagram of the array substrate of the present disclosure after forming the second conductive layer pattern;

[0035] Figure 10 is a schematic diagram of the array substrate of the present disclosure after forming the second insulating layer pattern;

[0036] Figure 11 is a schematic diagram of the array substrate of the present disclosure after forming the third conductive layer pattern;

[0037] Figure 12 is Figure 11 a plan view of the third conductive layer in

[0038] Figure 13 is Figure 11 an enlarged view of region C in

[0039] Figure 14 is Figure 13 a cross-sectional view taken along the A-A direction in

[0040] Figure 15 a schematic plan view of a display device according to an exemplary embodiment of the present disclosure.

[0041] Description of reference numerals:

[0042] 10 - thin film transistor; 11 - substrate; 12 - active layer;

[0043] 13 - source electrode; 14 - drain electrode; 15 - first insulating layer;

[0044] 16 - second insulating layer; 20 - gate line; 21 - opening;

[0045] 22 - gate protrusion; 30 - common electrode line; 31 - groove;

[0046] 32 - common protrusion; 40 - shielding line; 50 - data line;

[0047] 60 - gate connection line; 70 - common connection line; 80 - pixel electrode;

[0048] 81 - pixel base part; 82 - pixel comb part; 83 - pixel connection part;

[0049] 90 - common electrode; 91 - common base part; 92 - common comb part;

[0050] 93 - common shielding part; 100 - first substrate; 101 - first base;

[0051] 102 - first structural layer; 110 - common connection part; 120 - gate connection electrode;

[0052] 200 - second substrate; 201 - second base; 202 - second structural layer;

[0053] 300 - liquid crystal layer; 400 - black matrix. Detailed implementation manners

[0054] To make the objectives, technical solutions, and advantages of the present disclosure more clear and understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the forms and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0055] The drawing ratios in the present disclosure can be used as a reference in actual processes, but are not limited thereto. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the array substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0056] The ordinal numbers such as "first", "second", and "third" in this specification are set to avoid confusion of components, rather than to limit in terms of quantity.

[0057] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", and "outer" are used to describe the positional relationships of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationships of the components are appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0058] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be construed in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0059] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current mainly flows.

[0060] In this specification, the first pole may be the drain electrode and the second pole may be the source electrode, or the first pole may be the source electrode and the second pole may be the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be switched with each other, and the "source terminal" and "drain terminal" can be switched with each other.

[0061] In this specification, "electrically connected" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0062] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it also includes a state where the angle is 85° or more and 95° or less.

[0063] In this specification, "film" and "layer" can be switched with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0064] In this specification, triangles, rectangles, trapezoids, pentagons, hexagons, etc. are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There may be some small deformations due to tolerances, and there may be chamfers, rounded edges, and deformations, etc.

[0065] "About" in this disclosure means not strictly defining the boundary and allowing values within the range of process and measurement errors.

[0066] With the maturity of TFT-LCD technology, large-size and extra-large-size high-resolution liquid crystal display devices have developed rapidly in recent years, and their market share has gradually increased. As the size of the liquid crystal display device increases, problems such as horizontal and vertical stripes gradually increase, which have a greater impact on product quality and yield. For example, in a 65-inch full-screen liquid crystal display device, there are defects of horizontal and vertical stripes in the L0 state when the device is powered on. Research has found that the appearance of horizontal and vertical stripe defects in the L0 state when the device is powered on is to a certain extent due to the large overlapping area between the common electrode and the black matrix. The large overlapping area between the common electrode and the black matrix results in a relatively large coupling capacitance between the common electrode and the black matrix. When the device is powered on, the instantaneous change of the common voltage on the common electrode (such as from 0V to -8.7V) causes the black matrix to be coupled and charged. Since the charged black matrix will pull the pixel electrodes at the edge of the black matrix, light leakage occurs in the L0 state, and macroscopically, it is manifested as horizontal and vertical stripes when the device is powered on. Although using a high-resistance black matrix can improve the horizontal and vertical stripe defects to a certain extent, there is a situation where it is difficult to eliminate the charges in the high-resistance black matrix. Once the black matrix is coupled and charged, it will be difficult for the horizontal and vertical stripes to disappear.

[0067] Figure 1 It is a schematic cross-sectional structure diagram of a display device. As Figure 1 shown, the display device may include a first substrate 100 and a second substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the first substrate 100 and the second substrate 200. The first substrate 100 may include a first structural layer 102 disposed on the side of the first base 101 facing the second substrate 200, and the second substrate 200 may include a second structural layer 202 disposed on the side of the second base 201 facing the first substrate 100. LCDs can be classified into twisted nematic (TN) display mode, in-plane switching (IPS) display mode, fringe field switching (FFS) display mode, advanced super dimension switching (ADS) display mode, etc. according to the display mode. For the ADS display mode, in an exemplary embodiment, the first structural layer 102 may include gate lines, data lines, thin film transistors, pixel electrodes, and common electrodes, and the second structural layer 202 may include a black matrix and a light filtering unit.

[0068] Figure 2 It is a schematic plan view structure diagram of a display device. As Figure 2As shown, the display device may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a third sub-pixel P3 that emits light of a third color. The three sub-pixels may each include a thin film transistor, a pixel electrode, and a common electrode. In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel that emits red (R) light, the second sub-pixel P2 may be a green sub-pixel that emits green (G) light, and the third sub-pixel P3 may be a blue sub-pixel that emits blue (B) light. The shape of the sub-pixels in the pixel unit may be rectangular, diamond-shaped, pentagonal, hexagonal, etc. The sub-pixels in the pixel unit may be arranged in a horizontal side-by-side, vertical side-by-side, or pyramid arrangement. The present disclosure does not limit this. In an exemplary embodiment, the pixel unit may include four sub-pixels. The present disclosure does not limit this.

[0069] Figure 3 is a schematic plan view of an array substrate. As Figure 3 shown, in an exemplary embodiment, the array substrate includes a display area and a border area. The display area may include a plurality of gate lines (S1 to Sm) and a plurality of data lines (D1 to Dn). The plurality of gate lines may extend in the horizontal direction and be sequentially arranged in the vertical direction. The plurality of data lines may extend in the vertical direction and be sequentially arranged in the horizontal direction. The plurality of mutually intersecting gate lines and data lines define a plurality of regularly arranged sub-pixels Pxij, where i and j may be natural numbers. In an exemplary embodiment, at least one sub-pixel Pxij may include a thin film transistor, a pixel electrode, and a common electrode. The thin film transistor is respectively connected to the gate line, the data line, and the pixel electrode.

[0070] In an exemplary embodiment, the array substrate may further include a plurality of common electrode lines (E1 to Eo). The plurality of common electrode lines may extend in the horizontal direction and be sequentially arranged in the vertical direction. The plurality of common electrode lines are correspondingly connected to the common electrodes in the plurality of sub-pixels Pxij.

[0071] In an exemplary embodiment, the plurality of gate lines are led out to the border area and connected to a scan driver. The plurality of data lines are led out to the border area and connected to a data driver. At least a part of the scan driver and the data driver may be formed on the array substrate.

[0072] In an exemplary embodiment, an external control device (such as a timing controller) may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, and the data driver may use the received grayscale value and control signal to generate data voltages to be provided to data signal lines D1, D2, D3, ……, and Dn. For example, the data driver may sample the grayscale value using a clock signal and apply data voltages corresponding to the grayscale value to data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The external control device may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and the scan driver may use the clock signal, the scan start signal, etc. to generate scan signals to be provided to scan signal lines S1, S2, S3, ……, and Sm. For example, the scan driver may sequentially provide scan signals having conductive level pulses to scan signal lines S1 to Sm, where m may be a natural number. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that a scan start signal provided in the form of a conductive level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal.

[0073] Figure 4 FIG. is a schematic plan view of an array substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the array substrate may include a plurality of gate lines 20, a plurality of common electrode lines 30, and a plurality of data lines 50 disposed on a substrate. The gate lines 20 and the common electrode lines 30 may extend along a first direction X, the plurality of gate lines 20 and the plurality of common electrode lines 30 may be sequentially disposed along a second direction Y, respectively, the data lines 50 may extend along the second direction Y, and the plurality of data lines 50 may be sequentially disposed along the first direction X. A plurality of mutually intersecting gate lines 20 and data lines 50 define a plurality of regularly arranged sub-pixels, and the first direction X and the second direction X intersect. In an exemplary embodiment, the plurality of sub-pixels may form a plurality of pixel rows and a plurality of pixel columns. One pixel row may include a plurality of sub-pixels spaced along the first direction X, the plurality of pixel rows may be spaced along the second direction Y, one pixel column may include a plurality of sub-pixels spaced along the second direction Y, and the plurality of pixel columns may be spaced along the first direction X. Figure 4 It mainly shows the lower region of the sub-pixel in the i-th row and the j-th column and the upper region of the sub-pixel in the (i + 1)-th row and the j-th column to illustrate the structure of a sub-pixel. In the following description, this sub-pixel generally refers to the sub-pixel in the i-th row and the j-th column, the upper row sub-pixel generally refers to the sub-pixel in the (i - 1)-th row and the j-th column, and the lower row sub-pixel generally refers to the sub-pixel in the (i + 1)-th row and the j-th column.

[0074] In an exemplary embodiment, at least one sub-pixel may include at least a thin-film transistor 10, a pixel electrode 80, and a common electrode 90. The thin-film transistor 10 may be connected to a gate line 20, a data line 50, and the pixel electrode 80 respectively. The common electrode 90 may be connected to a common electrode line 30. The thin-film transistor 10 is configured to receive a data voltage transmitted by the data line 50 and output it to the pixel electrode 80 under the control of the gate line 20, and control an electric field for driving the liquid crystal to deflect to be formed between the pixel electrode 80 and the common electrode 90, so as to achieve grayscale display.

[0075] Figure 5 For Figure 4 the schematic plan view of the pixel electrode in Figure 4 and Figure 5 shown, in an exemplary embodiment, the pixel electrode 80 in this sub-pixel may at least include a pixel base portion 81, a pixel comb portion 82, and a pixel connection portion 83 that are connected to each other. The pixel base portion 81 may be in a strip shape extending along the first direction X, and may be located in the lower region of this sub-pixel (the region close to the next row of sub-pixels). The pixel comb portion 82 may include a plurality of pixel strip electrodes arranged at intervals along the first direction X. The plurality of pixel strip electrodes are arranged on the side of the pixel base portion 81 away from the gate line 20 and extend in a direction away from the gate line 20. The pixel connection portion 83 may be arranged on the side of the pixel base portion 81 close to the gate line 20 and is connected to the drain electrode of the thin-film transistor 10 through a via hole.

[0076] Figure 6 For Figure 4 the schematic plan view of the common electrode in Figure 4 and Figure 6 shown, in an exemplary embodiment, the common electrode 90 in this sub-pixel may at least include a common base portion 91, a common comb portion 92, and a common shielding portion 93 that are connected to each other. The common base portion 91 may be in a strip shape extending along the first direction X, and may be located in the upper region of this sub-pixel (the region close to the previous row of sub-pixels). The common comb portion 92 may include a plurality of common strip electrodes arranged at intervals along the first direction X. The plurality of common strip electrodes are arranged on the side of the common base portion 91 close to the gate line 20 and extend in a direction close to the gate line 20. The common shielding portion 93 may be located on one side or both sides of the common comb portion 92 in the first direction X.

[0077] In an exemplary embodiment, the sub-pixel may further include a common connection portion 110 configured to connect the common electrodes 90 in adjacent sub-pixels in the second direction Y. For example, the common shielding portion 93 in the upper row of sub-pixels may be connected to the common base portion 91 in the present sub-pixel through the common connection portion 110. Further, for example, the common shielding portion 93 in the present sub-pixel may be connected to the common base portion 91 in the lower row of sub-pixels through the common connection portion 110.

[0078] In an exemplary embodiment, it can be considered that the common electrode 90 of the sub-pixel includes a common base portion 91, a common comb-shaped portion 92, a common shielding portion 93, and a common connection portion 110 that are connected to form an integral structure, and the common electrodes 90 in adjacent sub-pixels in the second direction Y are an integral structure connected to each other.

[0079] In an exemplary embodiment, the orthographic projection of the common connection portion 110 in the sub-pixel on the substrate and the orthographic projection of the gate line 20 in the sub-pixel on the substrate have a first overlapping region. The first overlapping region has a first width M1 in the first direction X and a second width M2 in the second direction Y. In an exemplary embodiment, the first width M1 is less than the second width M2.

[0080] In an exemplary embodiment, the first width M1 of the first overlapping region may be the width of the common connection portion 110 in the first direction X, the second width M2 may be the width of the gate line 20 in the second direction Y, and the first width M1 may be about 10% to 20% of the second width M2. For example, the first width M1 may be about 15% of the second width M2.

[0081] In an exemplary embodiment, the first width M1 may be about 5 μm to 8 μm, and the second width M2 may be about 30 μm to 50 μm.

[0082] In an exemplary embodiment, the first distance L1 between the edge of the pixel connection portion 83 in the sub-pixel close to the common connection portion 110 and the edge of the common connection portion 110 in the sub-pixel close to the pixel connection portion 83 may be about 20 μm to 50 μm, and the first distance L1 may be a dimension in the first direction X.

[0083] In an exemplary embodiment, the second distance L2 between the edge of the common base portion 91 in the sub-pixel far from the upper row of sub-pixels and the edge of the gate line 20 in the upper row of sub-pixels close to the present sub-pixel may be about 5 μm to 7 μm, or the second distance L2 between the edge of the common base portion 91 in the lower row of sub-pixels far from the present sub-pixel and the edge of the gate line 20 in the present sub-pixel close to the lower row of sub-pixels may be about 5 μm to 7 μm, and the second distance L2 may be a dimension in the second direction Y.

[0084] In an exemplary embodiment, a third distance L3 between an end of the pixel comb portion 82 in the sub-pixel close to the common base portion 91 and an edge of the common base portion 91 in the sub-pixel close to the pixel comb portion 82 may be approximately 3.5 μm to 4.5 μm. The third distance L3 may be a dimension in the second direction Y. In an exemplary embodiment, the second distance L2 may be greater than the third distance L3.

[0085] In an exemplary embodiment, a fourth distance L4 between an end of the pixel comb portion 82 in the sub-pixel close to the gate line 20 in the upper row of sub-pixels and an edge of the gate line 20 in the upper row of sub-pixels close to the pixel comb portion 82 in the sub-pixel may be approximately 9.0 μm to 11.5 μm. Alternatively, a fourth distance L4 between an end of the pixel comb portion 82 in the lower row of sub-pixels close to the gate line 20 in the sub-pixel and an edge of the gate line 20 in the sub-pixel close to the pixel comb portion 82 in the lower row of sub-pixels may be approximately 9.0 μm to 11.5 μm. The fourth distance L4 may be a dimension in the second direction Y.

[0086] In an exemplary embodiment, the common electrode line 30 in the sub-pixel may be disposed on a side of the gate line 20 away from the lower row of sub-pixels, and the common electrode line 30 is connected to the common electrode 90 in the sub-pixel through a via hole.

[0087] In an exemplary embodiment, at least one sub-pixel may further include a common connection line 70. The common connection line 70 may extend along the second direction Y, and the common electrode 90 of the sub-pixel may be connected to both the common electrode line 30 and the common connection line 70 through via holes.

[0088] In an exemplary embodiment, at least one sub-pixel may further include a gate connection line 60. The gate connection line 60 may extend along the second direction Y, and the gate connection line 60 may be connected to the gate line 20.

[0089] In an exemplary embodiment, at least one sub-pixel may further include a gate connection electrode 120. The gate connection electrode 120 may be connected to the gate line 20 and the gate connection line 60 respectively through via holes.

[0090] In an exemplary embodiment, at least one sub-pixel may further include at least one shielding line. A first end of the shielding line is connected to the common electrode line, and a second end of the shielding line extends in a direction away from the gate line 20 and the common electrode line 30.

[0091] In an exemplary embodiment, the shielding line may be located on at least one side of the data line 50.

[0092] In an exemplary embodiment, the shielding line may be located on at least one side of the common connection line 70.

[0093] In an exemplary embodiment, the gate lines 20, the common electrode lines 30, and the shielding lines may be disposed in the same layer and formed simultaneously through the same patterning process.

[0094] In an exemplary embodiment, the data lines 50, the gate connection lines 60, and the common connection lines 70 may be disposed in the same layer and formed simultaneously through the same patterning process.

[0095] In an exemplary embodiment, the pixel electrodes 80, the common electrodes 90, and the gate connection electrodes 120 may be disposed in the same layer and formed simultaneously through the same patterning process.

[0096] An exemplary illustration is provided below through the preparation process of the array substrate. The "patterning process" as referred to in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out using any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out using any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out using any one of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process throughout the manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process throughout the manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as referred to in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the array substrate. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0097] In an exemplary embodiment, taking the lower region of the sub-pixel in the i-th row and the j-th column and the upper region of the sub-pixel in the (i + 1)-th row and the j-th column as an example, the preparation of the array substrate may include the following operations.

[0098] (1) Form a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film through a patterning process, and forming a first conductive layer pattern on the substrate 10. The first conductive layer pattern includes at least the gate lines 20, the common electrode lines 30, and the shielding lines 40, as Figure 7 shown.

[0099] In an exemplary embodiment, the gate line 20 and the common electrode line 30 may be linear with the main body extending along the first direction X. The gate line 20 of each sub-pixel may be disposed on the lower side of the sub-pixel (the side closer to the sub-pixels in the next row in the sub-pixel), and the common electrode line 30 may be disposed on the side of the gate line 20 away from the sub-pixels in the next row. The main body portion of the common electrode line 30 may be parallel to the main body portion of the gate line 20.

[0100] In an exemplary embodiment, the gate line 20 and the common electrode line 30 may be provided with equal widths or non-equal widths. The width refers to the dimension perpendicular to the extending direction (the second direction Y) of the gate line 20 or the common electrode line 30.

[0101] In an exemplary embodiment, at least one opening 21 may be provided on the gate line 20. The opening 21 may be disposed in the region where the gate line 20 overlaps with the subsequently formed data line. The width of the gate line 20 in the region where the opening 21 is located may be smaller than the width of the gate line 20 in other regions, so as to reduce the overlapping area between the gate line 20 and the subsequently formed data line. It is equivalent to that the gate line 20 has a width reduction design in the overlapping region with the data line, which can reduce the parasitic capacitance between the gate line 20 and the data line and improve the electrical performance of the display panel.

[0102] In an exemplary embodiment, at least one gate protrusion 22 may be provided on the gate line 20. The gate protrusion 22 may be disposed in the region where the gate line 20 overlaps with the subsequently formed gate connection line. It is equivalent to that the gate line 20 has a width increase design in the overlapping region with the gate connection line, which is beneficial to the connection between the gate connection line and the gate line 20 through the gate connection electrode.

[0103] In an exemplary embodiment, at least one groove 31 may be provided on the side of the common electrode line 30 close to the gate line 20. The groove 31 may be disposed in the region where the common electrode line 30 overlaps with the subsequently formed data line, so as to reduce the overlapping area between the common electrode line 30 and the subsequently formed data line. It is equivalent to that the common electrode line 30 has a width reduction design in the overlapping region with the data line, which can reduce the parasitic capacitance between the common electrode line 30 and the data line and improve the electrical performance of the display panel.

[0104] In an exemplary embodiment, at least one common protrusion 32 may be provided in at least one groove 31. The common protrusion 32 may be disposed in the region where the common electrode line 30 overlaps with the subsequently formed common connection line, which is beneficial to the connection between the common electrode line 30 and the common connection line through the via hole.

[0105] In an exemplary embodiment, a plurality of shielding lines 40 may be disposed on a side of the common electrode line 30 away from the gate line 20. A first end of the plurality of shielding lines 40 is connected to the common electrode line 30, and a second end of the plurality of shielding lines 40 extends in a direction away from the gate line 20 and the common electrode line 30.

[0106] In an exemplary embodiment, the extending direction of the plurality of shielding lines 40 may be the same as the extending direction of the data lines to be formed subsequently, so that the shielding lines 40 may be respectively disposed on one side or both sides of the data lines in the first direction X, realizing shielding of the data lines by the shielding lines 40 to improve the electrical performance of the display panel.

[0107] In an exemplary embodiment, the extending direction of the shielding lines 40 in this sub-pixel and the extending direction of the shielding lines 40 in the next row of sub-pixels may be mirror-symmetrical with respect to the first direction X, and the extending direction of the shielding lines 40 in the previous row of sub-pixels and the extending direction of the shielding lines 40 in this sub-pixel may be mirror-symmetrical with respect to the first direction X.

[0108] (2) Form a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor layer film on the substrate on which the foregoing pattern is formed, patterning the semiconductor layer film through a patterning process to form a first insulating layer covering the first conductive layer pattern, and a semiconductor layer pattern disposed on the first insulating layer. The semiconductor layer pattern at least includes an active layer disposed in each sub-pixel, as Figure 8 shown.

[0109] In an exemplary embodiment, the shapes and positions of the active layers 12 in each sub-pixel may be the same, which may simplify the structure of the thin film transistor.

[0110] In an exemplary embodiment, the orthographic projection of the active layer 12 on the substrate may be within the range of the orthographic projection of the gate line 20 on the substrate, and the overlapping region between the gate line 20 and the active layer 12 may serve as the gate electrode of each sub-pixel.

[0111] (3) Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film through a patterning process to form a second conductive layer pattern. The second conductive layer pattern at least includes: data lines 50, gate connection lines 60, common connection lines 70, source electrodes 13, and drain electrodes 14, as Figure 9 shown.

[0112] In an exemplary embodiment, the data line 50, the gate connection line 60, and the common connection line 70 may be in a broken line shape with the main body portion extending along the second direction Y, and the extending directions of the respective broken lines in the data line 50, the gate connection line 60, and the common connection line 70 may be substantially the same.

[0113] In an exemplary embodiment, the data line 50 may be disposed on one side (right side) of the sub-pixel in the first direction X, the gate connection line 60 may be disposed on one side (left side) in the opposite direction of the first direction X of the sub-pixel, and the common connection line 70 may be disposed on one side of the gate connection line 60 in the first direction X. In an exemplary embodiment, a data line 50 may be disposed in each sub-pixel, and a gate connection line 60 and a common connection line 70 may be disposed in some sub-pixels, that is, only a data line 50 is disposed in some sub-pixels, and a data line 50, a gate connection line 60, and a common connection line 70 are disposed in some other sub-pixels. The data line 50 is configured to be connected to a thin film transistor in the sub-pixel to provide a data signal to the thin film transistor, the gate connection line 60 is configured to be connected to the gate line 20 in the sub-pixel to provide a gate driving signal to the gate line 20, and the common connection line 70 is configured to be connected to the common electrode line 30 in the sub-pixel, so that a plurality of common electrode lines 30 extending along the first direction X and a plurality of common connection lines 70 extending along the second direction Y form a grid-like common grid line, improving the uniformity of the common electrodes of the display panel.

[0114] In an exemplary embodiment, the data line 50, the gate connection line 60, and the common connection line 70 may be provided with equal widths or non-equal widths, and the width refers to the dimension perpendicular to the extending direction of the data line 50, the gate connection line 60, or the common connection line 70.

[0115] In an exemplary embodiment, at least one gate connection protrusion 61 may be disposed on the side of the gate connection line 60 facing the common connection line 70, and the positive projection of the gate connection protrusion 61 on the substrate at least partially overlaps with the positive projection of the gate protrusion 22 on the gate line 20 on the substrate, so as to facilitate the connection between the gate connection line 70 and the gate line 20 through a connection electrode.

[0116] In an exemplary embodiment, at least one common connection protrusion 71 may be disposed on the side of the common connection line 70 facing the gate connection line 60, and the positive projection of the common connection protrusion 71 on the substrate at least partially overlaps with the positive projection of the common protrusion 32 on the common electrode line 30 on the substrate, so as to facilitate the connection between the common connection line 70 and the common electrode line 30 through a via hole.

[0117] In an exemplary embodiment, the source electrode 13 of each sub-pixel is disposed on one side in the opposite direction of the first direction X of the data line 50, and is integrally connected to the data line 50. The drain electrode 14 of each sub-pixel is separately disposed, and the positive projection of the drain electrode 14 on the substrate at least partially overlaps with the positive projection of the common electrode line 30 on the substrate. One end of the source electrode 13 and one end of the drain electrode 14 are respectively disposed on the active layer 12, and a conductive channel is formed between the source electrode 13 and the drain electrode 14. The gate electrode, the active layer 12, the source electrode 13, and the drain electrode 14 constitute the thin film transistor 10.

[0118] In an exemplary embodiment, for a sub-pixel provided with the gate connection line 60 and the common connection line 70, one shielding line 40 may be disposed on one side in the opposite direction of the first direction X of the data line 50, and another shielding line 40 may be disposed on one side of the first direction X of the common connection line 70, that is, the data line 50, the gate connection line 60, and the common connection line 70 are located between the two shielding lines 40.

[0119] In an exemplary embodiment, for a sub-pixel not provided with the gate connection line 60 and the common connection line 70, one shielding line 40 may be disposed on one side in the opposite direction of the first direction X of the data line 50, and another shielding line 40 may be disposed on one side of the first direction X of the data line 50, that is, the data line 50 is located between the two shielding lines 40.

[0120] (4) Form a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the foregoing pattern is formed, and patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the second conductive pattern. The second insulating layer pattern includes a plurality of vias, as Figure 10 shown.

[0121] In an exemplary embodiment, for a sub-pixel provided with the gate connection line 60 and the common connection line 70, the plurality of vias may at least include: a first via K1, a second via K2, a third via K3, a fourth via K4, and a fifth via K5. For a sub-pixel not provided with the gate connection line 60 and the common connection line 70, the plurality of vias may at least include: a first via K1 and a second via K2.

[0122] In an exemplary embodiment, the positive projection of the first via K1 on the substrate may be within the range of the positive projection of the drain electrode 14 on the substrate. The second insulating layer in the first via K1 is etched away to expose the surface of the drain electrode 14. The first via K1 is configured to connect the pixel electrode formed subsequently to the drain electrode 14 through the via.

[0123] In an exemplary embodiment, the orthographic projection of the second via K2 on the substrate may be within the range of the orthographic projection of the common electrode line 30 on the substrate. The second insulating layer and the first insulating layer in the second via K2 are etched away to expose the surface of the common electrode line 30. The second via K2 is configured to enable the common electrode formed subsequently to be connected to the common electrode line 30 through this via.

[0124] In an exemplary embodiment, on the one hand, the orthographic projection of the third via K3 on the substrate may at least partially overlap with the orthographic projection of the common connection protrusion 71 on the common connection line 70 on the substrate. On the other hand, the orthographic projection of the third via K3 on the substrate may at least partially overlap with the orthographic projection of the common protrusion 32 on the common electrode line 30 on the substrate. The second insulating layer and the first insulating layer in the third via K3 are etched away to expose the surfaces of the common connection protrusion 71 and the common protrusion 32 simultaneously. The third via K3 is configured to enable the common electrode formed subsequently to be connected to the common connection protrusion 71 (common connection line 70) and the common protrusion 32 (common electrode line 30) through this via simultaneously.

[0125] In an exemplary embodiment, the orthographic projection of the fourth via K4 on the substrate may at least partially overlap with the orthographic projection of the gate protrusion 22 on the gate line 20 on the substrate. The second insulating layer and the first insulating layer in the fourth via K4 are etched away to expose the surface of the gate protrusion 22. The fourth via K4 is configured to enable the gate connection electrode formed subsequently to be connected to the gate protrusion 22 (gate line 20) through this via.

[0126] In an exemplary embodiment, the orthographic projection of the fifth via K5 on the substrate may at least partially overlap with the orthographic projection of the gate connection protrusion 61 on the gate connection line 60 on the substrate. The second insulating layer in the fourth via K4 is etched away to expose the surface of the gate connection protrusion 61. The fifth via K5 is configured to enable the gate connection electrode formed subsequently to be connected to the gate connection protrusion 61 (gate connection line 60) through this via.

[0127] In an exemplary embodiment, the shape of the plurality of vias may be any one or more of the following: square, rectangle, circle, and ellipse.

[0128] (5) Form the third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the third conductive thin film through a patterning process to form the third conductive layer pattern. The third conductive layer pattern at least includes: the pixel electrode 80, the common electrode 90, and the gate connection electrode 120, as Figure 11 、 Figure 12 、 Figure 13 and Figure 14 shown, Figure 12 is Figure 11Plan view of the third conductive layer Figure 13 is Figure 11 an enlarged view of region C in Figure 14 is Figure 13 a cross-sectional view taken along line A-A in

[0129] In an exemplary embodiment, the pixel electrode 80 in the sub-pixel may at least include a pixel base portion 81, a pixel comb portion 82, and a pixel connection portion 83 that are connected to each other. The pixel base portion 81 may be in a strip shape extending along the first direction X and may be located in the lower region (the region close to the sub-pixels in the next row) of the sub-pixel. The pixel comb portion 82 may include a plurality of pixel strip electrodes arranged at intervals along the first direction X. The plurality of pixel strip electrodes are provided on a side of the pixel base portion 81 away from the gate line 20. The first ends of the plurality of pixel strip electrodes are respectively connected to the pixel base portion 81, and the second ends of the plurality of pixel strip electrodes respectively extend in a direction away from the gate line 20. The pixel connection portion 83 may be in a rectangular shape and may be provided on a side of the pixel base portion 81 close to the gate line 20. The orthographic projection of the pixel connection portion 83 on the substrate at least partially overlaps the orthographic projection of the drain electrode of the thin film transistor 10 on the substrate, and the pixel connection portion 83 is connected to the drain electrode of the thin film transistor 10 through a first via K1.

[0130] In an exemplary embodiment, the common electrode 90 in the sub-pixel may at least include a common base portion 91, a common comb portion 92, a common shielding portion 93, and a common connection portion 110 that are connected to each other. The common base portion 91 may be in a strip shape extending along the first direction X and may be located in the upper region (the region close to the sub-pixels in the previous row) of the sub-pixel. The common comb portion 92 may include a plurality of common strip electrodes arranged at intervals along the first direction X. The plurality of common strip electrodes are provided on a side of the common base portion 91 close to the gate line 20. The first ends of the plurality of common strip electrodes are respectively connected to the common base portion 91, and the second ends of the plurality of common strip electrodes respectively extend in a direction close to the gate line 20. The common shielding portion 93 may be located on one or both sides of the common comb portion 92 in the first direction X. The common connection portion 110 is configured to connect the common electrodes 90 in adjacent sub-pixels in the second direction Y. For example, the common shielding portion 93 in the previous row of sub-pixels may be connected to the common base portion 91 in the sub-pixel through the common connection portion 110. Also, for example, the common shielding portion 93 in the sub-pixel may be connected to the common base portion 91 in the next row of sub-pixels through the common connection portion 110.

[0131] In an exemplary embodiment, the pixel base portion 81 and the common base portion 91 may be respectively located on the upper and lower sides of the sub-pixel. A plurality of pixel strip electrodes extend in the direction of the common base portion 91, and a plurality of common strip electrodes extend in the direction of the pixel base portion 81. The pixel comb-shaped portion 82 with a comb structure and the common comb-shaped portion 92 with a comb structure are inserted into each other. The pixel strip electrodes and the common strip electrodes are alternately arranged in the first direction X, that is, one pixel strip electrode is located between two adjacent common strip electrodes in the first direction X, and one common strip electrode is located between two adjacent pixel strip electrodes in the first direction X, which can ensure that a horizontal electric field is formed between the pixel electrode 80 and the common electrode 90.

[0132] In an exemplary embodiment, the common shielding portion 93 may be in a strip shape extending along the second direction Y, and the extending direction of the common shielding portion 93 is substantially the same as the extending direction of the data line 50.

[0133] In an exemplary embodiment, for the sub-pixel provided with the gate connection line 60 and the common connection line 70, the common shielding portion 93 may be connected to the common connection protrusion 71 and the common protrusion 32 respectively through the third via K3, so as to realize the connection of the common electrode 90 to the common electrode line 30 and the common connection line 70 respectively, so that a plurality of common electrode lines 30 extending along the first direction X and a plurality of common connection lines 70 extending along the second direction Y are connected to each other to form a grid-shaped common grid line. The common voltage is provided to the common electrode 90 by the grid-shaped common grid line, so that the common electrodes of all sub-pixels have the same potential, and the uniformity of the common voltage of the display panel is improved. In an exemplary embodiment, the orthographic projection of the common shielding portion 93 on the substrate overlaps at least partially with the orthographic projection of the shielding line 40 on the substrate, the orthographic projection of the common shielding portion 93 on the substrate overlaps at least partially with the orthographic projection of the data line 50 on the substrate, the orthographic projection of the common shielding portion 93 on the substrate overlaps at least partially with the orthographic projection of the gate connection line 60 on the substrate, and the orthographic projection of the common shielding portion 93 on the substrate overlaps at least partially with the orthographic projection of the common connection line 70 on the substrate.

[0134] In an exemplary embodiment, for the sub-pixel without the gate connection line 60 and the common connection line 70, the orthographic projection of the common shielding portion 93 on the substrate overlaps at least partially with the orthographic projection of the shielding line 40 on the substrate, and the orthographic projection of the common shielding portion 93 on the substrate overlaps at least partially with the orthographic projection of the data line 50 on the substrate.

[0135] In an exemplary embodiment, the common connection portion 110 of the sub-pixel may be in a strip shape extending along the second direction Y. The first end of the common connection portion 110 is connected to the common shielding portion 93 in the sub-pixel, and the second end of the common connection portion 110 extends along the opposite direction of the second direction Y and is connected to the common base portion 91 in the sub-pixels of the next row, so that the common electrodes 90 in adjacent sub-pixels in a pixel column form an integrally connected structure.

[0136] In an exemplary embodiment, the common connection portion 110 may be connected to the common electrode line 30 through the second via K2, and the common voltage is provided to the common electrode 90 by the common electrode line 30.

[0137] In an exemplary embodiment, the gate connection electrode 120 may be rectangular. On the one hand, the positive projection of the gate connection electrode 120 on the substrate at least partially overlaps with the positive projection of the gate protrusion 22 on the gate line 20 on the substrate, and the gate connection electrode 120 is connected to the gate protrusion 22 through the fourth via K4. On the other hand, the positive projection of the gate connection electrode 120 on the substrate at least partially overlaps with the positive projection of the gate connection protrusion 61 on the gate connection line 60 on the substrate, and the gate connection electrode 120 is connected to the gate connection protrusion 61 through the fifth via K5. Since the gate protrusion 22 is connected to the gate line 20 and the gate connection protrusion 61 is connected to the gate connection line 60, and the gate connection electrode 120 is connected to both the gate protrusion 22 and the gate connection protrusion 61 through vias, the gate line 20 is connected to the gate connection line 60 through the gate connection electrode 120, and the gate driving circuit can output a gate driving signal to the gate line 20 through the gate connection line 60.

[0138] In this way, the preparation of the array substrate of the exemplary embodiment of the present disclosure is completed. Each sub-pixel includes a thin film transistor 10, a pixel electrode 80, and a common electrode 90. The thin film transistor 10 may include a gate electrode, an active layer, a source electrode, and a drain electrode. The gate electrode is connected to the gate line 20, the source electrode is connected to the data line 50, the drain electrode is connected to the pixel electrode 80, the common electrode 90 is connected to the common electrode line 30, and a horizontal electric field is formed between the pixel electrode 80 and the common electrode 90.

[0139] In an exemplary embodiment, the positive projection of the common connection portion 110 on the substrate and the positive projection of the gate line 20 on the substrate have a first overlapping area B. The first width M1 of the first overlapping area B may be the width of the common connection portion 110 in the first direction X, and the second width M2 may be the width of the gate line 20 in the second direction Y. The first width M1 is less than the second width M2.

[0140] In an exemplary embodiment, the first width M1 may be about 10% to 20% of the second width M2. For example, the first width M1 may be about 15% of the second width M2.

[0141] In an exemplary embodiment, the first width M1 may be approximately 5 μm to 8 μm, and the second width M2 may be approximately 30 μm to 50 μm. For example, the first width M1 may be approximately 6 μm, and the second width M2 may be approximately 38 μm.

[0142] In an array substrate, in order to reduce the influence of the jump voltage on the gate line 20 on the horizontal electric field, a design concept of covering the gate line 20 as much as possible with the common electrode 90 is usually adopted. Therefore, the width M1' of the common connection portion 110 in the array substrate is relatively large, about 100 μm or more, as shown by the dotted line in Figure 7 As shown. Since the area where the gate line 20 is located is the covering area of the black matrix, there is a relatively large overlapping area between the common electrode 90 and the black matrix in the array substrate. In the exemplary embodiment of the present disclosure, by reducing the first width of the common connection portion, the overlapping area between the common electrode and the black matrix is effectively reduced, the coupling capacitance between the common electrode and the black matrix is effectively reduced, the probability of the black matrix being coupled and charged is reduced, the light leakage in the power-on L0 state is avoided, and the appearance of horizontal and vertical stripe defects in the power-on L0 state is avoided. By only retaining the necessary width of the common connection portion in the area where the gate line is located, compared with the existing structure, the overlapping area between the common electrode and the black matrix in this area is reduced by about 80%, and the coupling capacitance between the common electrode and the black matrix is only about 20% of the existing structure, effectively avoiding the appearance of horizontal and vertical stripe defects in the power-on L0 state.

[0143] In an exemplary embodiment, the orthographic projection of the common connection portion 110 on the substrate at least partially overlaps with the orthographic projection of the drain electrode of the thin film transistor 10 on the substrate, and the orthographic projection of the pixel connection portion 83 on the substrate at least partially overlaps with the orthographic projection of the drain electrode of the thin film transistor 10 on the substrate. In the area overlapping with the drain electrode of the thin film transistor 10, the first distance L1 between the edge of the pixel connection portion 83 close to the common connection portion 110 and the edge of the common connection portion 110 in this sub-pixel close to the pixel connection portion 83 may be approximately 20 μm to 50 μm, and the first distance L1 may be the dimension in the first direction X. For example, the first distance L1 may be approximately 37.3 μm.

[0144] In an array substrate, in order to reduce the influence of the jump voltage on the drain electrode of the thin film transistor 10 on the horizontal electric field, a design concept of using the common electrode 90 to cover the drain electrode of the thin film transistor 10 as much as possible is usually adopted. Therefore, the first distance L1 between the common connection part and the pixel connection part in the array substrate is usually set to be 5 μm to 6 μm. It has been found through research that the smaller first distance L1 in the array substrate will cause a short circuit between the pixel electrode and the common electrode, affecting the process yield. By reducing the overlapping area between the common connection part and the drain electrode of the thin film transistor 10, the present disclosure not only increases the first distance L1 to 20 μm to 50 μm, effectively avoiding the short circuit between the pixel electrode and the common electrode and effectively improving the process yield, but also further reduces the overlapping area between the common electrode and the black matrix, which is more conducive to avoiding the appearance of horizontal and vertical stripe defects in the L0 state when turning on the machine.

[0145] As Figure 13 and Figure 14 shown, the array substrate may include a substrate 11, a gate line 20 disposed on the substrate, a first insulating layer 15 covering the gate line 20, a second insulating layer 16 disposed on the first insulating layer 15, and a pixel electrode 80 and a common electrode 90 disposed on the second insulating layer 16. In an exemplary embodiment, the positive projection of the common base portion 91 in this sub-pixel on the substrate may at least partially overlap with the positive projection of the gate line 20 in the upper row of sub-pixels on the substrate, or the positive projection of the gate line 20 in this sub-pixel on the substrate may at least partially overlap with the positive projection of the common base portion 91 in the lower row of sub-pixels on the substrate. There is a second distance L2 between the edge of the common base portion 91 in this sub-pixel away from the upper row of sub-pixels and the edge of the gate line 20 in the upper row of sub-pixels close to this sub-pixel, or there is a second distance L2 between the edge of the common base portion 91 in the lower row of sub-pixels away from this sub-pixel and the edge of the gate line 20 in this sub-pixel close to the lower row of sub-pixels. The second distance L2 may be a dimension in the second direction Y.

[0146] In an exemplary embodiment, there is a third distance L3 between the end of the pixel comb portion 82 in this sub-pixel close to the common base portion 91 and the edge of the common base portion 91 in this sub-pixel close to the pixel comb portion 82. The third distance L3 may be a dimension in the second direction Y.

[0147] In an exemplary embodiment, the second distance L2 may be greater than the third distance L3.

[0148] In an exemplary embodiment, the second distance L2 may be about 5 μm to 7 μm. For example, the second distance L2 may be about 5.5 μm.

[0149] In an exemplary embodiment, the third distance L3 may be approximately 3.5 μm to 4.5 μm. For example, the third distance L3 may be approximately 4.02 μm.

[0150] In an exemplary embodiment, a fourth distance L4 between an end of the pixel comb portion 82 in the sub-pixel close to the gate line 20 in the upper row of sub-pixels and an edge of the gate line 20 in the upper row of sub-pixels close to the pixel comb portion 82 in the sub-pixel may be approximately 9.0 μm to 11.5 μm, or a fourth distance L4 between an end of the pixel comb portion 82 in the lower row of sub-pixels close to the gate line 20 in the sub-pixel and an edge of the gate line 20 in the sub-pixel close to the pixel comb portion 82 in the lower row of sub-pixels may be approximately 9.0 μm to 11.5 μm. The fourth distance L4 may be a dimension in the second direction Y. For example, the fourth distance L4 may be approximately 9.52 μm.

[0151] In an exemplary embodiment, the array substrate may include a black matrix shielding region, and the orthographic projection of the black matrix shielding region on the substrate at least includes the orthographic projections of the thin film transistor 10, the gate line 20, and the data line 50 on the substrate. Figure 13 The region in the middle-lower dotted line frame is the region not shielded by the black matrix, and the region outside the dotted line frame is the black matrix shielding region. In an exemplary embodiment, in the second direction Y, a fifth distance L5 between a first edge 410 of the black matrix shielding region close to the gate line 20 and an edge of the gate line 20 close to the first edge 410 may be approximately 5 μm to 7 μm. For example, the fifth distance L5 may be approximately 6 μm.

[0152] In an array substrate, in order to increase the aperture ratio as much as possible, the distance between the edge of the common base portion and the edge of the gate line is small, and the second distance is usually less than 4 μm. It has been found through research that due to the large voltage mutation on the gate line, the voltage mutation on the gate line will cause disturbance to the pixel electrode, resulting in light leakage at the end of the pixel strip electrode. The present disclosure increases the second distance between the edge of the common base portion and the edge of the gate line, sets the second distance to be approximately 5 μm to 7 μm, increases the shielding of the common electrode to the gate line, effectively avoids the disturbance of the voltage mutation on the gate line to the pixel electrode, not only effectively avoids light leakage at the end of the pixel strip electrode, but also further improves the vertical and horizontal stripe phenomenon during startup. In addition, in order to ensure the aperture ratio, the present disclosure reduces the third distance between the pixel electrode and the common electrode, from about 5 μm in the traditional structure to about 4 μm, which can not only make the fourth distance between the gate line and the pixel electrode in the present disclosure equivalent to that in the traditional structure, but also increase the intensity of the horizontal electric field between the pixel electrode and the common electrode, effectively improving the ability of the horizontal electric field to resist the disturbance of the gate line signal and improving the display quality. The light leakage test shows that light leakage occurs in the existing structure when the voltage on the gate line is -40V, while light leakage in the structure of the present disclosure occurs only when the voltage on the gate line is -160V.

[0153] In an exemplary embodiment, the substrate may be made of glass, quartz, etc. The first conductive layer and the second conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first conductive layer may be referred to as the gate metal (GATE) layer, and the second conductive layer may be referred to as the source-drain metal (SD) layer. The third conductive layer may be a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may be a multi-layer composite structure, such as ITO / Ag / ITO, etc. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer may be referred to as the gate insulation (GI) layer, and the second insulating layer may be referred to as the passivation (PVX) layer. The active layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0154] The exemplary embodiment of the present disclosure further provides a display device. The display device may include a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate may be the aforementioned array substrate, and the second substrate may include a black matrix and a color filter unit.

[0155] Figure 15 It is a schematic plan view of the display device according to the exemplary embodiment of the present disclosure, showing the planar position relationship between the black matrix on the second substrate and the related structures on the first substrate. As Figure 15 shown, the orthographic projection of the black matrix 400 on the substrate includes the orthographic projections of the gate line 20, the common electrode line 30, and the data line 50 on the substrate. In the second direction Y, the fifth distance L5 between the first edge 410 of the black matrix 400 on the side close to the gate line 20 and the edge of the gate line 20 on the side close to the first edge 410 may be about 5 μm to 7 μm. For example, the fifth distance L5 may be about 6 μm.

[0156] In an exemplary embodiment, the display device of the present disclosure may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. The embodiments of the present invention are not limited thereto.

[0157] The exemplary embodiments of the present disclosure also provide a method for manufacturing an array substrate to fabricate the array substrate provided in the foregoing embodiments. In an exemplary embodiment, the method for manufacturing an array substrate may include:

[0158] Forming a plurality of gate lines and a plurality of data lines on a substrate, the plurality of gate lines extending along a first direction and arranged in sequence in a second direction, the plurality of data lines extending along the second direction and arranged in sequence in the first direction, a plurality of sub-pixels defined by the intersection of the plurality of gate lines and the plurality of data lines, the sub-pixels including at least thin film transistors, and the first direction intersecting with the second direction;

[0159] Forming a pixel electrode and a common electrode, the common electrode in at least one sub-pixel being connected to the common electrode in an adjacent sub-pixel in the second direction through a common connection portion, a first overlapping region being formed between a positive projection of the common connection portion on the substrate and a positive projection of the gate line on the substrate, the first overlapping region having a first width in the first direction and a second width in the second direction, and the first width being smaller than the second width.

[0160] Although the disclosed embodiments are as described above, the above content is only an embodiment adopted for the convenience of understanding the present disclosure and is not intended to limit the present invention. Any person skilled in the art can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. An array substrate includes a plurality of gate lines and a plurality of data lines disposed on a substrate. The plurality of gate lines extend along a first direction and are sequentially arranged in a second direction. The plurality of data lines extend along the second direction and are sequentially arranged in the first direction. A plurality of sub-pixels are defined by the intersection of the plurality of gate lines and the plurality of data lines. The sub-pixels at least include thin film transistors, pixel electrodes, and common electrodes. The first direction and the second direction intersect; the common electrodes in at least one sub-pixel are connected to the common electrodes in adjacent sub-pixels in the second direction through a common connection portion; the pixel electrodes in at least one sub-pixel at least include a pixel base portion and a pixel comb portion. The pixel comb portion includes a plurality of pixel strip electrodes, and the plurality of pixel strip electrodes are disposed on a side of the pixel base portion away from the gate lines; the common electrodes in at least one sub-pixel at least include a common base portion and a common comb portion. The common comb portion includes a plurality of common strip electrodes, and the plurality of common strip electrodes are disposed on a side of the common base portion close to the gate lines; a first end of the plurality of pixel strip electrodes is connected to the pixel base portion, and a second end of the plurality of pixel strip electrodes extends toward the common base portion; a first end of the plurality of common strip electrodes is connected to the common base portion, and a second end of the plurality of common strip electrodes extends toward the pixel base portion; in the first direction, the pixel strip electrodes and the common strip electrodes are alternately arranged; the pixel electrodes in at least one sub-pixel further include a pixel connection portion. The pixel connection portion is disposed on a side of the pixel base portion close to the gate lines and is connected to the drain electrode of the thin film transistor through a first via; the common electrodes in at least one sub-pixel further include a common shielding portion. The common shielding portion of this sub-pixel is connected to the common base portion of the sub-pixels in the next row through the common connection portion; at least one sub-pixel further includes a common electrode line extending along the first direction. The common electrode is connected to the common electrode line through a second via; the common connection portion includes a protruding portion facing the pixel connection portion. In a direction perpendicular to the array substrate, a positive projection of the second via on the substrate overlaps with a positive projection of the protruding portion on the substrate, and positive projections of the first via and the second via on the substrate overlap with a positive projection of the common electrode line on the substrate.

2. The array substrate according to claim 1, wherein, A positive projection of the common connection portion on the substrate and a positive projection of the gate line on the substrate have a first overlapping region. In the first direction, the first overlapping region has a first width, and in the second direction, the first overlapping region has a second width. The first width is less than the second width, and the first width is 10% to 20% of the second width.

3. The array substrate according to claim 1, wherein, The positive projection of the common connection portion on the substrate and the positive projection of the gate line on the substrate have a first overlapping region. In the first direction, the first overlapping region has a first width, and in the second direction, the first overlapping region has a second width. The first width is less than the second width, and the first width is 5 μm to 8 μm.

4. The array substrate according to claim 1, wherein, The first distance between the edge of the pixel connection portion close to the common connection portion and the edge of the common connection portion close to the pixel connection portion is 20 μm to 50 μm, and the first distance is a dimension in the first direction.

5. The array substrate according to claim 1, wherein, There is a second distance between the edge of the common base portion in this sub-pixel away from the sub-pixels in the upper row and the edge of the gate line in the sub-pixels in the upper row close to this sub-pixel. There is a third distance between the end of the pixel bar electrode close to the common base portion and the edge of the common base portion close to the pixel bar electrode. The second distance is greater than the third distance, and the second distance and the third distance are dimensions in the second direction.

6. The array substrate according to claim 5, wherein, The second distance is 5 μm to 7 μm.

7. The array substrate according to claim 5, wherein, The third distance is 3.5 μm to 4.5 μm.

8. The array substrate according to claim 1, wherein, The fourth distance between the end of the pixel comb portion in this sub-pixel close to the gate line in the sub-pixels in the upper row and the edge of the gate line in the sub-pixels in the upper row close to the pixel comb portion in this sub-pixel is 9.0 μm to 11.5 μm.

9. The array substrate according to claim 1, wherein, The array substrate further includes a black matrix shielding region. The positive projection of the black matrix shielding region on the substrate includes the positive projections of the gate line and the data line on the substrate. In the second direction, the fifth distance between the first edge of the black matrix shielding region close to the gate line and the edge of the gate line close to the first edge is 5 μm to 7 μm.

10. The array substrate according to claim 1, wherein, At least one sub-pixel further includes a common connection line extending along the second direction. The common electrode is connected to both the common electrode line and the common connection line through vias.

11. The array substrate according to claim 1, wherein, At least one sub-pixel further includes at least one shielding line. The first end of the shielding line is connected to the common electrode line, and the second end of the shielding line extends in a direction away from the common electrode line.

12. The array substrate according to any one of claims 1 to 9, wherein, At least one sub-pixel further includes a gate connection line extending along the second direction. The gate connection line is connected to the gate line.

13. The array substrate according to claim 12, wherein, At least one sub-pixel further includes a gate connection electrode, and the gate connection electrode is respectively connected to the gate connection line and the gate line through vias.

14. A display device includes a first substrate and a second substrate disposed opposite to each other. The first substrate includes the array substrate according to any one of claims 1 to 13. The second substrate includes at least a black matrix. The positive projection of the black matrix on the substrate includes the positive projections of the gate line and the data line on the substrate. In the second direction, the fifth distance between the first edge of the black matrix close to the gate line and the edge of the gate line close to the first edge is 5 μm to 7 μm.

15. A method for manufacturing an array substrate includes: A plurality of gate lines and a plurality of data lines are formed on a substrate. The plurality of gate lines extend along a first direction and are sequentially arranged in a second direction. The plurality of data lines extend along the second direction and are sequentially arranged in the first direction. A plurality of sub-pixels are defined by the intersection of the plurality of gate lines and the plurality of data lines. The sub-pixels at least include thin film transistors. The first direction and the second direction intersect. A pixel electrode and a common electrode are formed. The common electrode in at least one sub-pixel is connected to the common electrode in an adjacent sub-pixel in the second direction through a common connection portion. The pixel electrode in at least one sub-pixel at least includes a pixel base portion and a pixel comb portion. The pixel comb portion includes a plurality of pixel bar electrodes. The plurality of pixel bar electrodes are arranged on a side of the pixel base portion away from the gate line. The common electrode in at least one sub-pixel at least includes a common base portion and a common comb portion. The common comb portion includes a plurality of common bar electrodes. The plurality of common bar electrodes are arranged on a side of the common base portion close to the gate line. A first end of the plurality of pixel bar electrodes is connected to the pixel base portion, and a second end of the plurality of pixel bar electrodes extends in a direction towards the common base portion. A first end of the plurality of common bar electrodes is connected to the common base portion, and a second end of the plurality of common bar electrodes extends in a direction towards the pixel base portion. In the first direction, the pixel bar electrodes and the common bar electrodes are alternately arranged. The pixel electrode in at least one sub-pixel further includes a pixel connection portion. The pixel connection portion is arranged on a side of the pixel base portion close to the gate line and is connected to the drain electrode of the thin film transistor through a first via hole. The common electrode in at least one sub-pixel further includes a common shielding portion. The common shielding portion of the present sub-pixel is connected to the common base portion of the sub-pixels in the next row through the common connection portion. At least one sub-pixel further includes a common electrode line extending along the first direction. The common electrode is connected to the common electrode line through a second via hole. The common connection portion includes a protruding portion facing the pixel connection portion. In a direction perpendicular to the array substrate, a positive projection of the second via hole on the substrate overlaps with a positive projection of the protruding portion on the substrate. A positive projection of the first via hole on the substrate and a positive projection of the second via hole on the substrate overlap with a positive projection of the common electrode line on the substrate.

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