Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes providing a substrate having a high voltage region, a medium voltage region, and a low voltage region. A first transistor is formed in the high voltage region and a second transistor is formed in the low voltage region. The first transistor includes a first base disposed on the substrate, a first gate dielectric layer disposed on the first base, and a first gate electrode disposed on the first gate dielectric layer. The second transistor includes a fin structure disposed on the substrate and a second gate electrode disposed on the fin structure. A top surface of the first gate dielectric layer is substantially flush with a top surface of the fin structure.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for fabricating semiconductor devices, and more particularly, to a method for integrating high-voltage devices, medium-voltage devices, and low-voltage devices. BACKGROUND

[0002] With the current level of semiconductor technology, it is possible to integrate control circuits, memories, low-voltage operation circuits, high-voltage operation circuits and devices on a single chip, thereby reducing cost and improving operation efficiency. Among them, high-voltage devices such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT), and lateral-diffusion metal-oxide-semiconductor (LDMOS) are often used because of their high power switching efficiency. As known to those skilled in the art, the aforementioned high-voltage devices are often required to withstand high breakdown voltage and operate at low resistance.

[0003] In addition, as the size of the devices continues to shrink, the development of existing planar field effect transistor devices has reached the limit of the manufacturing process. In order to overcome the process limitations, non-planar field effect transistor devices, such as fin field effect transistor (Fin FET) devices, have become the mainstream development trend to replace planar transistor devices. Because the three-dimensional structure of the fin field effect transistor device can increase the contact area between the gate and the fin structure, the control of the gate over the carrier channel region can be further increased, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small size devices and suppressing the short channel effect (SCE). Furthermore, the fin field effect transistor device has a wider channel width under the same gate length, so it can double the drain drive current. Even the threshold voltage of the transistor device can be adjusted by adjusting the work function of the gate.

[0004] However, as the element size continues to shrink, there are still many challenges in integrating the existing high-voltage elements with low-voltage elements such as fin field effect transistors, such as control of leakage current and breakdown voltage. Therefore, how to improve the existing high-voltage element architecture is an important issue today. SUMMARY

[0005] One embodiment of the present application discloses a method for manufacturing a semiconductor device, which mainly provides a substrate having a high-voltage region, a medium-voltage region, and a low-voltage region, then forms a first transistor in the high-voltage region and a second transistor in the low-voltage region. The first transistor includes a first base disposed on the substrate, a first gate dielectric layer disposed on the first base, and a first gate electrode disposed on the first gate dielectric layer. The second transistor includes a fin structure disposed on the substrate and a second gate electrode disposed on the fin structure, wherein the top surface of the first gate dielectric layer is flush with the top surface of the fin structure.

[0006] Another embodiment of the present application discloses a semiconductor device, which mainly includes a substrate having a high-voltage region, a medium-voltage region, and a low-voltage region, a first transistor disposed in the high-voltage region, and a second transistor disposed in the low-voltage region. The first transistor includes a first base disposed on the substrate, a first gate dielectric layer disposed on the first base, and a first gate electrode disposed on the first gate dielectric layer. The second transistor includes a fin structure disposed on the substrate and a second gate electrode disposed on the fin structure, wherein the top surface of the first gate dielectric layer is flush with the top surface of the fin structure. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1 to 11 A schematic diagram of a method for manufacturing a semiconductor device according to one embodiment of the present application.

[0008] Explanation of main elements

[0009] 12: substrate

[0010] 14: high-voltage region

[0011] 16: medium-voltage region

[0012] 18: low-voltage region

[0013] 20: base

[0014] 22: base

[0015] 24: fin structure

[0016] 26: liner layer

[0017] 28: liner layer

[0018] 30: hard mask

[0019] 32: insulating layer

[0020] 34: doped region

[0021] 36: hard mask

[0022] 38: patterned mask

[0023] 40: recess

[0024] 42: gate dielectric layer

[0025] 44: hard mask

[0026] 46: patterned mask

[0027] 48: gate dielectric layer

[0028] 50: shallow trench isolation

[0029] 52: gate dielectric layer

[0030] 54: gate structure

[0031] 56: gate structure

[0032] 58: gate structure

[0033] 60: gate material layer

[0034] 62: hard mask

[0035] 64: hard mask

[0036] 66: gate electrode

[0037] 68: epitaxial layer

[0038] 70: source / drain region

[0039] 72: electrostatic discharge protection ring

[0040] 74: interlayer dielectric layer

[0041] 76: high dielectric constant dielectric layer

[0042] 78: work function metal layer

[0043] 80: low impedance metal layer

[0044] 82: hard mask

[0045] 84: contact plug

[0046] 114: high voltage element

[0047] 116: medium voltage element

[0048] 118: low voltage element DETAILED DESCRIPTION

[0049] Please refer to Figures 1 to 11 ,Figures 1 to 11 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 1 A top view of a semiconductor device fabricated according to an embodiment of the present invention. Figures 2 to 11 Then it is Figure 1 A cross-sectional schematic diagram of a semiconductor device is fabricated along tangents AA', BB', and CC'. (See diagram below.) Figures 1 to 2 As shown, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is first provided, on which three or more transistor regions are defined, such as a high-voltage region 14, a medium-voltage region 16, and a low-voltage region 18. The high-voltage region 14 contains a high-voltage element 114, the medium-voltage region 16 contains a medium-voltage element 116, and the low-voltage region 18 contains a low-voltage element 118. Figures 2 to 11 It is better to follow along Figure 1 A schematic diagram illustrating a method for fabricating semiconductor devices along the directions of tangent AA' in high-voltage region 14, BB' in medium-voltage region 16, and CC' in low-voltage region 18. In this embodiment, high-voltage region 14, medium-voltage region 16, and low-voltage region 18 may contain transistor regions of the same or different conductivity types, such as PMOS transistor regions and / or NMOS transistor regions, and the three regions are respectively intended for subsequent fabrication of gate structures with different threshold voltages. In this embodiment, a P-type deep well region can be first formed in high-voltage region 14 and medium-voltage region 16 using an ion implantation process, and an N-type deep well region can be formed in low-voltage region 18, but the conductivity type of each region is not limited to this.

[0050] Then, bases 20 and 22 are formed on the substrates 12 of the high-pressure region 14 and the medium-pressure region 16, respectively, and a plurality of fin structures 24 are formed on the substrate of the low-pressure region 18. According to a preferred embodiment of the present invention, the bases 20 and 22 and the fin structures 24 are preferably fabricated by sidewall image transfer (SIT) technology, the procedure of which generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equal-width patterned sacrificial layers or mandrels are formed on the substrate by photolithography and etching processes, so that their individual appearance is strip-shaped. Then, deposition and etching processes are performed sequentially to form spacers on each sidewall of the patterned sacrificial layer. The patterned sacrificial layer is then removed, and an etching process is performed under the cover of the spacers, so that the pattern formed by the spacers is transferred into the substrate, and then the desired patterned structure, such as a strip-shaped patterned fin structure, is obtained by a fin cut process.

[0051] In addition, the formation of the bases 20, 22 and the fin structure 24 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the bases 20, 22 and the fin structure 24. Alternatively, the bases 20, 22 and the fin structure 24 may also be formed by first fabricating a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding bases 20, 22 and the fin structure 24. These embodiments of forming the bases 20, 22 and the fin structure 24 are all within the scope of this invention.

[0052] In this embodiment, each base 20, 22 and the top surface of the fin structure 24 may have a pad layer 26, a pad layer 28 and a hard mask 30 on the substrate 12 during the above patterning process. The pad layer 26 preferably contains silicon oxide, the pad layer 28 preferably contains silicon nitride, and the hard mask 30 preferably contains silicon oxide, but are not limited to these.

[0053] Then as Figure 3 As shown, a flowable chemical vapor deposition (FCVD) process is used to form an insulating layer 32 made of silicon oxide on the substrates 20, 22 and the fin structure 24, filling the groove between the substrates 20, 22 and the fin structure 24. Then, a planarization process is performed, for example, by chemical mechanical polishing (CMP) to remove the hard mask 30 so that the top surface of the pad layer 28 is flush with the top surface of the insulating layer 32.

[0054] Subsequently, as Figure 4 As shown, the silicon nitride liner 28 is first removed by etching to expose the silicon oxide liner 26 underneath, making the top surfaces of the insulating layers 32 on both sides slightly higher than the top surface of the liner 26, and simultaneously forming grooves (not shown) directly above the liner 26. Then, an ion implantation process is performed to form doped regions 34 on both sides of the base 20 of the high-voltage region 14, wherein the doped regions 34 preferably serve as lightly doped drains for the subsequent high-voltage device 114. Next, a hard mask 36 is formed on the bases 20 and 22, fin structure 24, and insulating layer 32 of the high-voltage region 14, medium-voltage region 16, and low-voltage region 18, filling the grooves above the liner 26. In this embodiment, the hard mask 36 preferably contains silicon nitride, but is not limited to this.

[0055] Subsequently, as Figure 5As shown, a patterned mask 38, such as a patterned photoresist, is first formed on the hard mask 36 of the middle pressure region 16 and the low pressure region 18, and the patterned mask 38 has an opening exposing a portion of the surface of the hard mask 36 of the high pressure region 14. Then, an etching process is performed using the patterned mask 38 as a mask to remove a portion of the hard mask 36 of the high pressure region 14, a portion of the base 20, and a portion of the insulating layer 32 on both sides of the base 22 to form a recess 40.

[0056] As shown, a patterned mask 38, such as a patterned photoresist, is first formed on the hard mask 36 of the middle pressure region 16 and the low pressure region 18, and the patterned mask 38 has an opening exposing a portion of the surface of the hard mask 36 of the high pressure region 14. Then, an etching process is performed using the patterned mask 38 as a mask to remove a portion of the hard mask 36 of the high pressure region 14, a portion of the base 20, and a portion of the insulating layer 32 on both sides of the base 22 to form a recess 40. Figure 6

[0057] Then, another patterned mask (not shown), such as a patterned photoresist, is formed covering the insulating layer 32 of the high pressure region 14 and the middle pressure region 16, and the patterned mask has an opening exposing the top surface of the liner layer 26 and the insulating layer 32 of the low pressure region 18. An ion implantation process is then performed to implant dopants into the fin structure 24 of the low pressure region 18 to adjust the threshold voltage of the element. The patterned mask is then removed.

[0058] As shown, a patterned mask 38, such as a patterned photoresist, is first formed on the hard mask 36 of the middle pressure region 16 and the low pressure region 18, and the patterned mask 38 has an opening exposing a portion of the surface of the hard mask 36 of the high pressure region 14. Then, an etching process is performed using the patterned mask 38 as a mask to remove a portion of the hard mask 36 of the high pressure region 14, a portion of the base 20, and a portion of the insulating layer 32 on both sides of the base 22 to form a recess 40. Figure 7

[0059] Then, another patterned mask (not shown), such as a patterned photoresist, is formed covering the insulating layer 32 of the high pressure region 14 and the middle pressure region 16, and the patterned mask has an opening exposing the top surface of the hard mask 44 of the middle pressure region 16. An etching process is then performed using the patterned mask 46 as a mask to remove the hard mask 44 of the middle pressure region 16, a portion of the insulating layer 32, the liner layer 26, and even a portion of the base 22 to expose the surface of the base 22. Figure 8 ​​As shown, another oxide growth fabrication process such as a rapid thermal oxidation (RTO) fabrication process is first performed to form a gate dielectric layer 48 composed of silicon oxide on the base 22 of the middle voltage region 16, wherein the top surface of the gate dielectric layer 48 of the middle voltage region 16 is preferably trimmed to be flush with the top surface of the gate dielectric layer 42 of the high voltage region 14, and the thickness of the gate dielectric layer 42 of the high voltage region 14 is preferably greater than the thickness of the gate dielectric layer 48 of the middle voltage region 16. In the present embodiment, the thickness of the gate dielectric layer 42 of the high voltage region 14 can be more than twice, such as three times, four times or even five times the thickness of the gate dielectric layer 48 of the middle voltage region 16.

[0060] Next, the patterned mask 46 and the remaining hard mask 44 originally disposed in the high voltage region 14, the middle voltage region 16 and the low voltage region 18 are removed, and an etching fabrication process is then performed to completely remove the spacer layer 26 on top of the fin structure 24 of the low voltage region 14 and expose the top surface of the fin structure 24, and to remove portions of the insulating layer 32 in the high voltage region 14, the middle voltage region 16 and the low voltage region 18, so that the remaining top surface of the insulating layer 32 is slightly lower than the top surface of the base 20, 22 of the high voltage region 14 and the middle voltage region 16 and the fin structure 24 of the low voltage region 18 to form a shallow trench isolation (STI) 50. It is noted that at this stage, the top surface of the gate dielectric layer 42 of the high voltage region 14 is preferably trimmed to be flush with the top surface of the gate dielectric layer 48 of the middle voltage region 16 and the top surface of the fin structure 24 of the low voltage region 18.

[0061] As shown, another oxide growth fabrication process such as a rapid thermal oxidation (RTO) fabrication process is first performed to form a gate dielectric layer 48 composed of silicon oxide on the base 22 of the middle voltage region 16, wherein the top surface of the gate dielectric layer 48 of the middle voltage region 16 is preferably trimmed to be flush with the top surface of the gate dielectric layer 42 of the high voltage region 14, and the thickness of the gate dielectric layer 42 of the high voltage region 14 is preferably greater than the thickness of the gate dielectric layer 48 of the middle voltage region 16. In the present embodiment, the thickness of the gate dielectric layer 42 of the high voltage region 14 can be more than twice, such as three times, four times or even five times the thickness of the gate dielectric layer 48 of the middle voltage region 16. Figure 9As shown, a gate dielectric layer 52 composed of silicon oxide is then formed on the surfaces of the fin structures 24 in the low voltage region 18 by a one-oxidation process such as an in-situ steam generation (ISSG) process. Subsequently, gate structures 54, 56, 58 or dummy gates can be formed on the pedestals 20, 22 and the fin structures 24 in the high voltage region 14, the medium voltage region 16 and the low voltage region 18, respectively. In this embodiment, the gate structures 54, 56, 58 can be formed by a gate first process, a gate last process, a high-k first process or a high-k last process according to the process requirement. For example, in the high-k last process, a gate material layer 60 composed of polysilicon, a hard mask 62 composed of silicon nitride and a hard mask 64 composed of silicon oxide are sequentially formed on the gate dielectric layers 42, 48, 52 in the regions, and a patterned photoresist (not shown) is used as a mask to perform a pattern transfer process by a single etching or a step-by-step etching to remove part of the hard masks 62, 64, part of the gate material layer 60 and even part of the gate dielectric layer 48 in the medium voltage region 16. Then, the patterned photoresist is removed to form the gate structures 54, 56, 58 composed of the gate dielectric layers 42, 48, 52 and the patterned gate material layer 60 on the substrate 12 in the regions, respectively. Preferably, the patterned gate material layer 60 becomes the gate electrode 66 in the regions.

[0062] Subsequently, at least one spacer (not shown) is formed on the sidewalls of the gate structures 54, 56, 58. In this embodiment, the spacer can be a single spacer or a composite spacer, for example, can include a bias spacer (not shown) and a main spacer (not shown). Preferably, the bias spacer and the main spacer include different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbon nitride, but are not limited thereto.

[0063] Please continue to refer to Figure 10 , Figure 10 is an embodiment of the present application along Figure 1 The method for manufacturing semiconductor elements in the direction of the tangent AA' in the high voltage region 14, the tangent BB' in the medium voltage region 16 and the tangent DD' in the low voltage region 18 is shown in the schematic view. As shown, Figure 10As shown, a patterned mask (not shown) such as a patterned photoresist can be formed to cover the high-voltage region 14 and the medium-voltage region 16, and a dry etching and / or wet etching fabrication process can be performed to etch the substrate 12 along the spacers of the gate structures 58 of the low-voltage region 18 to form recesses (not shown) in the substrate 12 on both sides of the gate structures 58 of the low-voltage region 18. A selective epitaxial growth (SEG) fabrication process can then be performed to form epitaxial layers 68 in the recesses. It is noted that the epitaxial layers 68 are formed only on both sides of the gate structures 58 of the low-voltage region 18 in this embodiment, but the high-voltage region 14 and the medium-voltage region 16 are preferably free of any epitaxial layers. In addition, the hard mask 64 of the low-voltage region 18 can be partially removed during the formation of the recesses, so that the top surface of the hard mask 64 of the low-voltage region 18 is lower than the top surfaces of the hard masks 64 of the high-voltage region 14 and the medium-voltage region 16.

[0064] From the cross-sectional view of Figure 10 The epitaxial layers 68 of the low-voltage region 18 preferably have the same cross-sectional shape as the recesses, such as a circular arc, a hexagon (also known as sigma), or an octagon, but other cross-sectional shapes are also possible. In the preferred embodiment of the present application, the epitaxial layers 68 can have different materials depending on the type of metal-oxide-semiconductor (MOS) transistors. For example, if the metal-oxide-semiconductor transistor is a P-type transistor (PMOS), the epitaxial layers 68 can be selected to include silicon germanium (SiGe), silicon germanium boron (SiGeB), or silicon germanium tin (SiGeSn). In another embodiment of the present application, if the metal-oxide-semiconductor transistor is an N-type transistor (NMOS), the epitaxial layers 68 can be selected to include silicon carbide (SiC), silicon carbon phosphorus (SiCP), or silicon phosphorus (SiP). In addition, the selective epitaxial fabrication process can be performed in a single layer or multiple layers, and the hetero-atoms (such as germanium atoms or carbon atoms) can be gradually changed in the layers, but it is preferred that the surface of the epitaxial layers 68 is free of germanium atoms or has fewer germanium atoms to facilitate the formation of a metal silicide layer later.

[0065] Subsequently, a photolithography and etching fabrication process can be performed to remove part of the gate dielectric layer 48 of the medium-voltage region 16 to expose the top surfaces of the pedestals 22 on both sides of the gate structures 56, and one or more ion implantation fabrication processes can be performed to form source / drain regions 70 in the pedestals 20, 22 on both sides of the gate structures 54, 56 of the high-voltage region 14 and the medium-voltage region 16, and to form a doped region as an electrostatic discharge protection ring 72 in the pedestal 20 around the high-voltage transistor in the high-voltage region 14. The source / drain regions 70 and the electrostatic discharge protection ring 72 in the high-voltage region 14 preferably include different types of dopants, such as one including N-type dopants and the other including P-type dopants.

[0066] According to one embodiment of the present invention, the source / drain region 70 can be selectively formed in part or all of the epitaxial layer 68 in the low-voltage region 18. In one embodiment, the formation of the source / drain region 70 in the low-voltage region 18 can also be performed in-situ during a selective epitaxial growth process. For example, when the metal-oxide semiconductor is PMOS, a germanium silicide epitaxial layer, a germanium boron silicide epitaxial layer, or a germanium tin silicide epitaxial layer is formed, which may be accompanied by the implantation of P-type dopants; or when the metal-oxide semiconductor is NMOS, a carbon silicide epitaxial layer, a carbon phosphorus silicide epitaxial layer, or a phosphorus silicide epitaxial layer is formed, which may be accompanied by the implantation of N-type dopants. This eliminates the need for subsequent additional ion implantation steps to form the source / drain region 70 of the P-type / N-type transistor. Furthermore, in another embodiment, the dopants in the source / drain region 70 can also be formed in a gradient manner.

[0067] Then as Figure 11 As shown, a contact etch stop layer (CESL) (not shown) made of silicon nitride can be selectively formed on the substrate 12 to cover the gate structures 54, 56, and 58 of the high-voltage region 14, the medium-voltage region 16, and the low-voltage region 18. Then, an interlayer dielectric layer 74 is formed on the contact etch stop layer. Next, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 74 and part of the contact etch stop layer so that the upper surface of the hard mask 64 is flush with the upper surface of the interlayer dielectric layer 74.

[0068] Subsequently, a metal gate replacement fabrication process is performed to convert the gate structures 54, 56, and 58 of the high-voltage region 14, medium-voltage region 16, and low-voltage region 18 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 60 in the hard masks 62 and 64 and the gate structures 54, 56, and 58 to form a groove (not shown) in the interlayer dielectric layer 74. Then, a high dielectric constant dielectric layer 76 and a conductive layer including at least a work function metal layer 78 and a low impedance metal layer 80 are sequentially formed in the groove. A planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 76, the U-shaped work function metal layer 78 and the low impedance metal layer 80 flush with the surface of the interlayer dielectric layer 74. Preferably, the high dielectric constant dielectric layer 76, the work function metal layer 78 and the low impedance metal layer 80 are the gate electrode 66 of each transistor or each device.

[0069] In this embodiment, the high-k dielectric layer 76 comprises a dielectric material having a dielectric constant greater than 4, such as selected from the group consisting of hafnium oxide (Hf02), hafnium silicon oxide (HfSi04), hafnium silicon oxynitride (HfSiON), aluminum oxide (AI2O3), lanthanum oxide (La203), tantalum oxide (Ta205), yttrium oxide (Y203), zirconium oxide (Zr02), strontium titanate oxide (SrTi03), zirconium silicon oxide (ZrSi04), hafnium zirconium oxide (HfZr04), strontium bismuth tantalate (SrBi2Ta20g, SBT), lead zirconate titanate (PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x Ti03, BST), or combinations thereof.

[0070] The work function metal layer 78 is preferably used to adjust the work function of the metal gate to be suitable for either an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 78 can be selected from a metal material having a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminum (TiAl), zirconium aluminum (ZrAl), tungsten aluminum (WAl), tantalum aluminum (TaAl), hafnium aluminum (HfAl), or TiAlC (titanium aluminum carbide), but not limited thereto. If the transistor is a P-type transistor, the work function metal layer 78 can be selected from a metal material having a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but not limited thereto. Another barrier layer (not shown) can be included between the work function metal layer 78 and the low impedance metal layer 80, wherein the barrier layer can be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like. The low impedance metal layer 80 can be selected from a low resistance material such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. Since the conversion of the dummy gate to the metal gate according to the metal gate replacement process is well known to those skilled in the art, further description is not necessary. Then, a portion of the high dielectric constant dielectric layer 76, a portion of the work function metal layer 78, and a portion of the low impedance metal layer 80 are removed to form a recess (not shown), and then a hard mask 82 is filled in the recess and is planarized with the surface of the interlayer dielectric layer 74, wherein the hard mask 82 can be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

[0071] A pattern transfer process can then be performed, such as removing a portion of the interlayer dielectric layer 74 beside the gate structures 54, 56, 58 and a portion of the contact hole etch stop layer to form a plurality of contact holes (not shown) and expose the source / drain regions 70 using a patterned mask. Then, a desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like, and a low impedance metal layer selected from a low resistance material such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof, is filled in each of the contact holes. Then, a planarization process, such as chemical mechanical polishing, is performed to remove a portion of the metal material to form a contact plug 84 in each of the contact holes to electrically connect the source / drain regions 70, respectively. Thus, the fabrication of the semiconductor device according to the preferred embodiment of the present application is completed.

[0072] Please refer to Figure 1 and Figure 11 , Figure 1and Figure 11 A schematic diagram of the structure of a semiconductor device according to one embodiment of the present invention is also disclosed. For example... Figure 1 and Figure 11 As shown, the semiconductor device mainly includes a substrate 12 having a high-voltage region 14, a medium-voltage region 16, and a low-voltage region 18. A high-voltage element 114 is disposed in the high-voltage region 14, a medium-voltage element 116 is disposed in the medium-voltage region 16, and a low-voltage element 118 is disposed in the low-voltage region 18. An electrostatic discharge protection ring 72 surrounds the high-voltage element 114, and a shallow trench isolation 50 surrounds the high-voltage element 114, the medium-voltage element 116, and the low-voltage element 118. The high-voltage element 114 includes a base 20 disposed on the substrate 12, a gate dielectric layer 42 disposed on the base 20, a gate electrode 66 composed of a high dielectric constant dielectric layer 76, a work function metal layer 78, and a low impedance metal layer 80 disposed on the gate dielectric layer 42, and source / drain regions 70 disposed within the base 20 on both sides of the gate electrode 66.

[0073] The medium-voltage element 116 includes a base 22 disposed on a substrate 12, a gate dielectric layer 48 disposed on a base 20, a gate electrode 66 composed of a high dielectric constant dielectric layer 76, a work function metal layer 78, and a low impedance metal layer 80 disposed on the gate dielectric layer 48, and a source / drain region 70 disposed within the base 22 on both sides of the gate electrode 66. The low-voltage element 118 includes multiple fin structures 24 disposed on a substrate 12, a gate dielectric layer 52 disposed on the fin structures 24, a gate electrode 66 composed of a high dielectric constant dielectric layer 76, a work function metal layer 78, and a low impedance metal layer 80 disposed on the gate dielectric layer 52, and a source / drain region 70 disposed within the fin structures 24 or the substrate 12 on both sides of the gate electrode 66.

[0074] In detail, the top surface of the gate electrode 66 in the high voltage region 14 is preferably aligned with the top surface of the gate electrode 66 in the medium voltage region 16 and the low voltage region 18. The top surface of the gate dielectric layer 42 in the high voltage region 14 is preferably aligned with the top surface of the gate dielectric layer 48 in the medium voltage region 16 and the top surface of the fin structure 24 in the low voltage region 18. The top surface of the gate dielectric layer 52 in the low voltage region 18 may be slightly higher than the top surface of the gate dielectric layer 42 in the high voltage region 14 and the top surface of the gate dielectric layer 48 in the medium voltage region 16. The top surface of the source / drain region 70 in the high voltage region 14 is aligned with the top surface of the fin structure 24 in the low voltage region 18, and the top surface of the electrostatic discharge protection ring 72 is aligned with the top surface of the source / drain region 70.

[0075] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: a substrate comprising a high voltage region, a medium voltage region, and a low voltage region; forming a high voltage element in the high voltage region, the high voltage element comprising: a first pedestal disposed on the substrate; a first gate dielectric layer disposed on the first pedestal; and a first gate electrode disposed on the first gate dielectric layer; forming a low voltage element in the low voltage region, the low voltage element comprising: a fin structure disposed on the substrate; and a second gate electrode disposed on the fin structure, wherein a top surface of the first gate dielectric layer is flush with a top surface of the fin structure.

2. The method of claim 1, wherein a top surface of the first gate electrode is flush with a top surface of the second gate electrode.

3. The method of claim 1, further comprising: forming the first pedestal in the high voltage region, a second pedestal in the medium voltage region, and the fin structure in the low voltage region; forming an insulating layer around the first pedestal, the second pedestal, and the fin structure; removing a portion of the first pedestal; forming the first gate dielectric layer on the first pedestal; forming a second gate dielectric layer on the second pedestal; removing the insulating layer to form a shallow trench isolation; forming a third gate dielectric layer on the fin structure; forming the first gate electrode on the first gate dielectric layer, the second gate electrode on the third gate dielectric layer, and a third gate electrode on the second gate dielectric layer; forming a first source / drain region adjacent to the first gate electrode; and forming a second source / drain region adjacent to the second gate electrode.

4. The method of claim 3, wherein a top surface of the first gate dielectric layer is flush with a top surface of the second gate dielectric layer.

5. The method of claim 3, wherein a top surface of the first gate electrode is flush with a top surface of the third gate electrode.

6. The method of claim 3, wherein a top surface of the first source / drain region is flush with a top surface of the fin structure.

7. The method of claim 3, further comprising forming an electrostatic discharge protection ring around the high voltage element.

8. The method of claim 7, wherein a top surface of the electrostatic discharge protection ring is flush with a top surface of the first source / drain region.

9. A semiconductor element characterized by comprising: Comprising: a substrate comprising a high voltage region, a medium voltage region, and a low voltage region; a high voltage element disposed in the high voltage region, the high voltage element comprising: a first pedestal disposed on the substrate; a first gate dielectric layer disposed on the first pedestal; and a first gate electrode disposed on the first gate dielectric layer; a low voltage element disposed in the low voltage region, the low voltage element comprising: a fin structure disposed on the substrate; and a second gate electrode disposed on the fin structure, wherein a top surface of the first gate dielectric layer is flush with a top surface of the fin structure.

10. The semiconductor element of claim 9, wherein a top surface of the first gate electrode is flush with a top surface of the second gate electrode.

11. The semiconductor element of claim 9, wherein the high voltage element comprises a source / drain region adjacent to the first gate electrode, and a top surface of the source / drain region is flush with a top surface of the fin structure.

12. The semiconductor element of claim 11, further comprising a shallow trench isolation disposed between the first pedestal and the source / drain region.

13. The semiconductor device of claim 11, further comprising a static discharge protection ring formed around the high voltage device.

14. The semiconductor device of claim 13, wherein a top surface of the static discharge protection ring is flush with a top surface of the source / drain region.

15. The semiconductor device of claim 9, further comprising a medium voltage device disposed in the medium voltage region, the medium voltage device comprising: a second base disposed on the substrate; a second gate dielectric layer disposed on the second base; and a third gate electrode disposed on the second gate dielectric layer.

16. The semiconductor device of claim 15, wherein a top surface of the second gate dielectric layer is flush with a top surface of the first gate dielectric layer.

17. The semiconductor device of claim 15, wherein a top surface of the first gate electrode is flush with a top surface of the third gate electrode. ​ ​ ​

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