Voltage regulator circuit and reference voltage source

Abstract

This disclosure provides a voltage regulator circuit and a reference voltage source. The voltage regulator circuit includes a bandgap reference source sub-circuit, comprising a reference voltage terminal, a first voltage terminal, and an output voltage terminal. The bandgap reference source sub-circuit is configured to apply a reference voltage to the reference voltage terminal, apply a first voltage to the first voltage terminal, and apply an output voltage to the output voltage terminal. A voltage regulator sub-circuit, electrically connected to the first voltage terminal and the output voltage terminal, is configured to adjust the voltage of the output voltage terminal according to the voltage of the first voltage terminal. A feedback sub-circuit, electrically connected to the reference voltage terminal and the output voltage terminal, is configured to feed back the voltage of the output voltage terminal to the bandgap reference source sub-circuit based on the voltage of the reference voltage terminal. The voltage regulator circuit is configured to, upon detecting a change in the voltage of the reference voltage terminal, adjust the voltage of the output voltage terminal according to the voltage of the first voltage terminal through the voltage regulator sub-circuit to keep the voltage of the output voltage terminal constant.

Description

Technical Field

[0001] This disclosure relates to the field of reference voltage source technology, and more specifically, to a voltage regulator circuit and a reference voltage source. Background Technology

[0002] A bandgap reference (BGR) is a circuit that provides a reference voltage or current. A BGR utilizes the negative temperature characteristic (TTC) of the base-emitter voltage (VBE) of a bipolar transistor and the positive TTC of the base-emitter voltage (ΔVBE) of another bipolar transistor. Superimposing these two voltages in a certain proportion produces a reference voltage source independent of its temperature coefficient. A low-dropout (LDO) voltage regulator uses a negative feedback loop, consisting of an error amplifier (EA), a regulating transistor, and a feedback circuit, to clamp the output voltage to a stable level.

[0003] In related technologies, a combination of BGR and LDO circuits is typically used to generate a stable reference power supply. However, the combination of BGR and LDO circuits is not conducive to optimizing circuit area or reducing circuit power consumption. Summary of the Invention

[0004] This disclosure presents a voltage regulator circuit and a reference voltage source.

[0005] According to a first aspect of this disclosure, a voltage regulator circuit is proposed, comprising: a bandgap reference source sub-circuit, including a reference voltage terminal, a first voltage terminal, and an output voltage terminal; wherein the bandgap reference source sub-circuit is configured to apply a reference voltage to the reference voltage terminal, apply a first voltage to the first voltage terminal, and apply an output voltage to the output voltage terminal; a voltage regulator sub-circuit, electrically connected to the first voltage terminal and the output voltage terminal, configured to adjust the voltage of the output voltage terminal according to the voltage of the first voltage terminal; and a feedback sub-circuit, electrically connected to the reference voltage terminal and the output voltage terminal, configured to feed back the voltage of the output voltage terminal to the bandgap reference source sub-circuit based on the voltage of the reference voltage terminal; wherein the voltage regulator circuit is configured to, when a change in the voltage of the reference voltage terminal is detected, adjust the voltage of the output voltage terminal according to the voltage of the first voltage terminal through the voltage regulator sub-circuit to keep the voltage of the output voltage terminal constant.

[0006] For example, a bandgap reference source circuit includes: a first branch and a second branch; wherein, the first branch includes a first PMOS transistor and a first transistor; the second branch includes a second PMOS transistor, a second transistor, a first resistor, and a second resistor; the first branch and the second branch are configured to apply a reference voltage to a reference voltage terminal and apply an output voltage to an output voltage terminal; the gate of the first PMOS transistor is electrically connected to the drain of the first PMOS transistor, the drain is electrically connected to the collector of the first transistor, and the source is electrically connected to a first voltage terminal; the base of the first transistor is electrically connected to the reference voltage terminal; the source of the second PMOS transistor is electrically connected to the first voltage terminal, the gate is electrically connected to the gate of the first PMOS transistor, and the drain is electrically connected to the collector of the second transistor; the base of the second transistor is electrically connected to the base of the first transistor, and the emitter is electrically connected to one end of the first resistor; the other end of the first resistor is electrically connected to the emitter of the first transistor and one end of the second resistor; the other end of the second resistor is grounded.

[0007] For example, the bandgap reference source circuit further includes: a third branch, including a first NMOS transistor and a third PMOS transistor, configured to apply a first voltage to a first voltage terminal; wherein, the drain of the first NMOS transistor is electrically connected to the first voltage terminal, the gate is electrically connected to the drain of the second PMOS transistor, and the source is electrically connected to the source of the third PMOS transistor; the gate of the third PMOS transistor is electrically connected to one end of a second resistor, and the drain is grounded.

[0008] For example, the third branch also includes a first capacitor, one end of which is electrically connected to the drain of the first NMOS transistor and the other end of which is electrically connected to the gate of the first NMOS transistor, configured to perform signal compensation for the voltage regulator circuit.

[0009] For example, it also includes: a third resistor, one end of which is electrically connected to the power supply voltage VDD, and the other end of which is electrically connected to the drain of the first NMOS transistor and the first voltage terminal;

[0010] The third resistor and the third branch form an amplifier sub-circuit. The amplifier sub-circuit is configured to adjust the voltage of the first voltage terminal according to the voltage of the reference voltage terminal when the output load Rout of the output voltage changes.

[0011] For example, the voltage regulator circuit includes: a second NMOS transistor; wherein the drain of the second NMOS transistor is electrically connected to the power supply voltage VDD, the gate is electrically connected to the other end of the third resistor and the first voltage terminal, and the source is electrically connected to the output voltage terminal.

[0012] For example, the feedback sub-circuit includes a fourth resistor and a fifth resistor; wherein one end of the fourth resistor is electrically connected to the source of the second NMOS transistor, and the other end is electrically connected to the reference voltage terminal; one end of the fifth resistor is electrically connected to the reference voltage terminal, and the other end is grounded.

[0013] For example, it also includes a second capacitor, one end of which is electrically connected to the output voltage terminal and the other end is grounded, configured to filter the output signal at the output voltage terminal.

[0014] For example, both the voltage at the reference voltage terminal and the voltage at the output voltage terminal are voltages with zero temperature coefficient.

[0015] According to a second aspect of the present disclosure, a reference voltage source is provided, including: a voltage regulator circuit provided in the first aspect of the present disclosure, the voltage regulator circuit being configured to provide a reference voltage to the reference voltage source.

[0016] According to the technical solution of the disclosed embodiment, a voltage regulator circuit is provided. The bandgap reference source sub-circuit of this voltage regulator circuit includes a reference voltage terminal constituting negative feedback, a first voltage terminal, and an output voltage terminal. The voltage at the output voltage terminal is regulated and adjusted by the voltage regulator sub-circuit to keep the output voltage constant. This voltage regulator circuit avoids using a combination of BGR and LDO circuits to achieve a regulated voltage output, reducing the circuit area and lowering the power consumption. Attached Figure Description

[0017] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments in conjunction with the accompanying drawings. It should be noted that throughout the drawings, the same elements are indicated by the same or similar reference numerals. In the figures:

[0018] Figure 1 A schematic diagram of a voltage regulator circuit according to an embodiment of the present disclosure is shown;

[0019] Figure 2 A schematic diagram of a voltage regulator circuit according to another embodiment of the present disclosure is shown;

[0020] Figure 3 A schematic diagram of a voltage regulator circuit according to another embodiment of the present disclosure is shown; and

[0021] Figure 4 A schematic diagram of a reference voltage source according to an embodiment of the present disclosure is shown. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0023] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," "third," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0024] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" can refer to a direct connection between two components, or to a connection between two components via one or more other components, wherein the connection method is electrical connection or electrical coupling. Additionally, the two components can also be connected or coupled via wired or wireless means.

[0025] Both BGR and LDO are independent circuits. A traditional BGR circuit includes a bandgap core circuit, current mirror circuit, amplification clamping circuit, and startup circuit. An LDO circuit includes an error amplifier circuit, regulation transistor circuit, and output feedback circuit. Combining BGR and LDO circuits to achieve stable power output results in a complex, large-scale circuit that requires significant current and is difficult to integrate. Furthermore, in low-power applications, combining BGR and LDO circuits imposes significant limitations and fails to meet low-power requirements.

[0026] To address the technical problems associated with combining BGR and LDO circuits to achieve stable power output, this disclosure provides a voltage regulator circuit. The voltage regulator circuit's bandgap reference source sub-circuit, voltage regulator sub-circuit, and feedback sub-circuit form a negative feedback loop. The voltage regulator sub-circuit regulates the output voltage to maintain a constant output voltage. This voltage regulator circuit avoids the need for a combination of BGR and LDO circuits to achieve a regulated voltage output, reducing circuit area and power consumption.

[0027] This disclosure provides a voltage regulator circuit, including a bandgap reference source sub-circuit, comprising a reference voltage terminal, a first voltage terminal, and an output voltage terminal. The bandgap reference source sub-circuit is configured to apply a reference voltage to the reference voltage terminal, apply a first voltage to the first voltage terminal, and apply an output voltage to the output voltage terminal. A voltage regulator sub-circuit, electrically connected to the first voltage terminal and the output voltage terminal, is configured to adjust the voltage of the output voltage terminal according to the voltage of the first voltage terminal. A feedback sub-circuit, electrically connected to the reference voltage terminal and the output voltage terminal, is configured to feed back the voltage of the output voltage terminal to the bandgap reference source sub-circuit based on the voltage of the reference voltage terminal. The voltage regulator circuit is configured to, upon detecting a change in the voltage of the reference voltage terminal, adjust the voltage of the output voltage terminal according to the voltage of the first voltage terminal through the voltage regulator sub-circuit to keep the voltage of the output voltage terminal constant.

[0028] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0029] Figure 1 A schematic diagram of a voltage regulator circuit according to an embodiment of the present disclosure is shown.

[0030] like Figure 1 As shown, the voltage regulator circuit 100 includes a bandgap reference source sub-circuit 110, a voltage regulator sub-circuit 120, and a feedback sub-circuit 130.

[0031] The bandgap reference source circuit 110 includes a reference voltage terminal Nref, a first voltage terminal Ngate, and an output voltage terminal Nout. The bandgap reference source circuit 110 is configured to apply a reference voltage Vref to the reference voltage terminal Nref, apply a first voltage Vgate to the first voltage terminal Ngate, and apply an output voltage Vout to the output voltage terminal Nout.

[0032] A voltage regulator circuit 120 is electrically connected to a first voltage terminal Ngate and an output voltage terminal Nout. The voltage regulator circuit 120 is configured to adjust the voltage at the output voltage terminal Nout according to the voltage at the first voltage terminal Ngate.

[0033] Feedback sub-circuit 130 is electrically connected to the reference voltage terminal Nref and the output voltage terminal Nout, and is configured to feed back the voltage of the output voltage terminal Nout to the bandgap reference source sub-circuit 310 based on the voltage of the reference voltage terminal Nref.

[0034] In this embodiment of the disclosure, the voltage regulator circuit 100 is configured to, when a change in the voltage of the reference voltage terminal Nref is detected, adjust the voltage of the output voltage terminal Nout according to the voltage of the first voltage terminal Ngate through the voltage regulator sub-circuit, so that the voltage of the output voltage terminal Nout remains unchanged.

[0035] It can be understood that the reference voltage terminal Nref, the first voltage terminal Ngate, and the output voltage terminal Nout can be considered as the three nodes of the voltage regulator circuit 100. During circuit operation, due to the change in the output load Rout at the output voltage terminal Nout, the voltage of each of these three nodes may be different at different times.

[0036] For example, the bandgap reference source sub-circuit 110 is an integrated BGR circuit. The reference voltage Vref output by the bandgap reference source sub-circuit 110 is a temperature-independent voltage, i.e., a zero-temperature coefficient voltage.

[0037] For example, the base-emitter voltage of a transistor is a voltage with a negative temperature coefficient, and the thermoelectric potential V T The voltage has a positive temperature coefficient. Therefore, by adjusting the area ratio N and thermoelectric potential V of the transistors in the bandgap reference source circuit 110... T This ensures that the reference voltage Vref output by the bandgap reference source circuit 110 is independent of temperature.

[0038] For example, the bandgap reference source sub-circuit 110 outputs the reference voltage Vref to the reference voltage terminal Nref, and the voltage at the output voltage terminal Nout obtained through the voltage regulator sub-circuit 120 and the feedback sub-circuit 130 is also a voltage with zero temperature coefficient.

[0039] For example, when the output load Rout at the output voltage terminal Nout changes, the voltage at the output voltage terminal Nout also changes. This change in the output voltage terminal Nout causes a change in the voltage at the reference voltage terminal Nref, which is electrically connected to the feedback sub-circuit 130. This changes the current flowing through the bandgap reference source sub-circuit 110, resulting in a change in the input voltage of the voltage regulator sub-circuit 120. The voltage regulator sub-circuit 120 regulates the voltage at the output voltage terminal Nout according to the change in the input voltage, so that the voltage at the output voltage terminal Nout remains constant.

[0040] According to embodiments of this disclosure, the bandgap reference source sub-circuit BGR of the provided voltage regulator circuit has high integration. This bandgap reference source sub-circuit BGR achieves the function of combining BGR and LDO in related technologies to realize stable voltage output, reducing circuit area and power consumption. Furthermore, this voltage regulator circuit is suitable for low-power applications.

[0041] Figure 2A schematic diagram of a voltage regulator circuit according to another embodiment of the present disclosure is shown.

[0042] like Figure 2 As shown, the voltage regulator circuit 200 includes a bandgap reference source sub-circuit 210, a voltage regulator sub-circuit 220, and a feedback sub-circuit 230.

[0043] The bandgap reference source circuit 210 includes a reference voltage terminal Nref, a first voltage terminal Ngate, and an output voltage terminal Nout. The reference voltage terminal Nref is electrically connected to the feedback sub-circuit 230, and the reference voltage Vref represents the voltage at the reference voltage terminal Nref. The first voltage terminal Ngate is electrically connected to the voltage regulator sub-circuit 220, and the first voltage Vgate represents the voltage at the first voltage terminal Ngate. The output voltage terminal Nout is electrically connected to both the voltage regulator sub-circuit 220 and the feedback sub-circuit 330, and the output voltage Vout represents the voltage at the output voltage terminal Nout.

[0044] For example, the voltage regulator circuit 220 may include an NMOS transistor NM2.

[0045] For example, the gate of NMOS transistor NM2 is electrically connected to the first voltage terminal Ngate, the drain is electrically connected to the power supply voltage VDD, and the source is electrically connected to the output voltage terminal Nout. NMOS transistor NM2 is configured to adjust the voltage of the output voltage terminal Nout according to the voltage of the first voltage terminal Ngate.

[0046] For example, the feedback sub-circuit 230 may include resistors Rf1 and Rf2.

[0047] For example, one end of resistor Rf1 is electrically connected to the output voltage terminal Nout, and the other end is electrically connected to the reference voltage terminal Nref and one end of resistor Rf2. The other end of resistor Rf2 is grounded. Resistors Rf1 and Rf2 are configured to feed back the voltage of the output voltage terminal Nout to the bandgap reference source sub-circuit 210 based on the voltage of the reference voltage terminal Nref.

[0048] According to an embodiment of this disclosure, the voltage regulator circuit 200 further includes a resistor R3.

[0049] For example, one end of resistor R3 is electrically connected to the power supply voltage VDD, and the other end is electrically connected to the first voltage terminal Ngate. Resistor R3 is configured such that, when the output load Rout at the output voltage terminal Nout changes, the voltage at the first voltage terminal Ngate changes according to the current change of the bandgap reference source circuit 210, after voltage division through resistor R3.

[0050] According to an embodiment of this disclosure, the voltage regulator circuit 200 further includes a capacitor C2.

[0051] For example, one end of capacitor C2 is electrically connected to the output voltage terminal Nout, and the other end is grounded.

[0052] For example, capacitor C2 is a filter capacitor for the output voltage terminal Nout, configured to filter out glitches, noise and other impurities in the output signal of the output voltage terminal Nout.

[0053] like Figure 2 As shown, the reference voltage Vref generated by the bandgap reference source circuit 210 can be a voltage divider signal of the output voltage Vout. When the reference voltage Vref is applied to the reference voltage terminal Nref, the output voltage Vout at the output voltage terminal Nout can be expressed as:

[0054]

[0055] In equation (1), V ref This represents the reference voltage Vref at the reference voltage terminal Nref. R f1 and R f2 Let Rf1 and Rf2 represent the resistance values, respectively. In the example of equation (1), different zero-temperature coefficient output voltages Vout can be obtained by adjusting the reference voltage Vref.

[0056] According to embodiments of this disclosure, when the output load Rout at the output voltage terminal Nout changes, the output voltage terminal Nout will also change.

[0057] For example, when the output load Rout decreases, the output voltage Vout at the output voltage terminal Nout increases. At this time, the reference voltage Vref at the reference voltage terminal Nref of resistors Rf1 and Rf2 in the feedback sub-circuit 230 increases, causing the current in the two bandgap reference branches of the bandgap reference source sub-circuit 210 to increase. Because the bandgap reference source sub-circuit 210 increases the current through resistor R3, the first voltage Vgate at the first voltage terminal Ngate decreases (i.e., the gate voltage of NMOS transistor NM2 decreases). Due to the decrease in the first voltage Vgate, the output voltage Vout at the output voltage terminal Nout decreases. Therefore, by adjusting the voltage of NMOS transistor NM2, the output voltage Vout at the output voltage terminal Nout decreases, thereby keeping the output voltage Vout constant.

[0058] For example, when the output load Rout increases, the output voltage Vout at the output voltage terminal Nout decreases. At this time, the reference voltage Vref at the reference voltage terminal Nref of resistors Rf1 and Rf2 in the feedback sub-circuit 230 decreases, thereby reducing the current in the two bandgap reference branches of the bandgap reference source sub-circuit 210. Because the bandgap reference source sub-circuit 210 reduces the current through resistor R3, the first voltage Vgate at the first voltage terminal Ngate increases (i.e., the gate voltage of NMOS transistor NM2 increases). This increase in the first voltage Vgate causes the output voltage Vout at the output voltage terminal Nout to increase. Therefore, by adjusting the voltage of NMOS transistor NM2, the output voltage Vout at the output voltage terminal Nout increases, thereby keeping the output voltage Vout constant.

[0059] According to embodiments of this disclosure, a negative feedback loop is formed by a bandgap reference source sub-circuit, a voltage regulator sub-circuit, and a feedback sub-circuit. When a change in the voltage at the reference voltage terminal Nref is detected, the voltage regulator sub-circuit adjusts the voltage at the output voltage terminal Nout based on the voltage at the first voltage terminal Ngate, so that the voltage at the output voltage terminal Nout remains constant. This voltage regulator circuit has a simple structure, reduces the circuit area, and lowers the power consumption of the circuit.

[0060] Figure 3 A schematic diagram of a voltage regulator circuit according to another embodiment of the present disclosure is shown.

[0061] like Figure 3 As shown, the voltage regulator circuit 300 includes a bandgap reference source sub-circuit 310, a voltage regulator sub-circuit 320, and a feedback sub-circuit 330.

[0062] In this embodiment of the disclosure, the bandgap reference source circuit 310 includes a first branch, a second branch, and a third branch. The first and second branches are configured to apply a reference voltage Vref to a reference voltage terminal Nref and to apply an output voltage Vout to an output voltage terminal Nout. The third branch is configured to apply a first voltage Vgate to a first voltage terminal Ngate.

[0063] For example, the first branch includes a first PMOS transistor PM1 and a first transistor Q1. The second branch includes a second PMOS transistor PM2, a second transistor Q2, a first resistor R1, and a second resistor R2.

[0064] For example, the gate and drain of the first PMOS transistor PM1 are electrically connected, the drain is electrically connected to the collector of the first transistor Q1, and the source is electrically connected to the first voltage terminal Nout. The base of the first transistor Q1 is electrically connected to the reference voltage terminal Nref, and the emitter is electrically connected to one end of the second resistor R2.

[0065] For example, the source of the second PMOS transistor PM2 is electrically connected to the first voltage terminal Nout, its gate is electrically connected to the gate of the first PMOS transistor PM1, and its drain is electrically connected to the collector of the second transistor Q2. The base of the second transistor Q2 is electrically connected to the base of the first transistor Q1, and its emitter is electrically connected to one end of the first resistor R1. The other end of the first resistor R1 is electrically connected to the emitter of the first transistor Q1 and one end of the second resistor R2. The other end of the second resistor R2 is grounded.

[0066] It can be understood that the first branch and the second branch are the bandgap reference branches of the bandgap reference source circuit 310. The first branch and the second branch constitute a current mirror module, that is, the current change and voltage change of the first branch and the second branch can be the same.

[0067] For example, the third branch includes the first NMOS transistor NM1, the third PMOS transistor PM3, and the first capacitor C1.

[0068] For example, the drain of the first NMOS transistor NM1 is electrically connected to the first voltage terminal Ngate, the gate is electrically connected to the drain of the second PMOS transistor PM2, and the source is electrically connected to the source of the third PMOS transistor PM3. The gate of the third PMOS transistor PM3 is electrically connected to one end of the second resistor R2, and the drain is grounded.

[0069] For example, one end of the first capacitor C1 is electrically connected to the drain of the first NMOS transistor NM1, and the other end is electrically connected to the gate of the first NMOS transistor NM1. The first capacitor C1 is configured to perform signal compensation for the voltage regulator circuit.

[0070] In this embodiment of the disclosure, the voltage regulator circuit 300 further includes a third resistor R3. One end of the third resistor R3 is electrically connected to the power supply voltage VDD, and the other end is electrically connected to the drain of the first NMOS transistor NM1 and the first voltage terminal Ngate.

[0071] For example, the third resistor R3 and the third branch constitute an amplifier sub-circuit. The amplifier sub-circuit is configured to adjust the voltage of the first voltage terminal Ngate according to the voltage of the reference voltage terminal Nref when the output load Rout at the output voltage terminal Nout changes.

[0072] In this embodiment of the disclosure, the voltage regulator circuit 320 includes a second NMOS transistor NM2.

[0073] For example, the drain of the second NMOS transistor NM2 is electrically connected to the power supply voltage VDD, the gate is electrically connected to the other end of the third resistor R3 and the first voltage terminal Ngate, and the source is electrically connected to the output voltage terminal Nout. The voltage regulator circuit 320 is configured to adjust the voltage of the output voltage terminal Nout according to the voltage of the first voltage terminal Ngate.

[0074] In this embodiment of the disclosure, the feedback sub-circuit 330 includes a fourth resistor Rf1 and a fifth resistor Rf2. The feedback sub-circuit 330 is configured to feed back the voltage of the output voltage terminal Nout to the bandgap reference source sub-circuit 310 based on the voltage of the reference voltage terminal Nref.

[0075] For example, one end of the fourth resistor Rf1 is electrically connected to the source and output voltage terminal Nout of the second NMOS transistor NM2, and the other end is electrically connected to the reference voltage terminal Nref. One end of the fifth resistor Rf2 is electrically connected to the reference voltage terminal Nref, and the other end is grounded.

[0076] In this embodiment of the disclosure, the voltage regulator circuit 300 further includes a second capacitor C2.

[0077] For example, one end of the second capacitor C2 is electrically connected to the output voltage terminal Nout, and the other end is grounded. The second capacitor C2 is configured to filter the output signal at the output voltage terminal Nout.

[0078] like Figure 3 As shown, the first transistor Q1, the second transistor Q2, the first resistor R1, and the second resistor R2 of the bandgap reference source circuit 310 constitute the core structure of the bandgap reference. The base voltage of the first transistor Q1 and the base voltage of the second transistor Q2 are the reference voltage Vref. The reference voltage Vref can be expressed as:

[0079]

[0080] In equation (2), Vbe1 represents the base-emitter voltage of the first transistor Q1. Q2 This represents the current flowing through the second transistor Q2. V T V represents thermoelectric potential. T N is a constant. N represents the ratio of the area of ​​the first transistor Q1 to the area of ​​the second transistor Q2.

[0081] It's understandable, V T The voltages with positive temperature coefficients are the base-emitter voltage of the first transistor Q1 and the base-emitter voltage of the second transistor Q2, while the voltages with negative temperature coefficients are the base-emitter voltages. The parameters of other components are independent of temperature.

[0082] In the example of equation (2), by adjusting the first resistor R1, the second resistor R2, and the area ratio N, the reference voltage Vref can be obtained to be independent of temperature. Combining equations (1) and (2), the temperature-independent output voltage Vout can be obtained.

[0083] According to an embodiment of this disclosure, the voltage regulator circuit configuration 300 is configured to, when a change in the voltage of the reference voltage terminal Nref is detected, adjust the voltage of the output voltage terminal Nout according to the voltage of the first voltage terminal Ngate through the voltage regulator sub-circuit 320 so that the voltage of the output voltage terminal Nout remains unchanged.

[0084] For example, when the output load Rout at the output voltage terminal Vout changes, the voltage at the reference voltage terminal Nref also changes.

[0085] In this embodiment of the disclosure, the voltage regulation of the output voltage terminal Nout using the voltage regulator circuit 320 can be divided into two cases: the output load Rou decreases or the output load Rou increases.

[0086] For example, when the output load Rout decreases, the output voltage Vout at the output voltage terminal Nout increases. At this time, the reference voltage Vref at the reference voltage terminal Nref of the fourth resistor Rf1 and the fifth resistor Rf2 in the feedback sub-circuit 330 increases, thereby increasing the current in the two bandgap reference branches of the bandgap reference source sub-circuit 310.

[0087] Because the current increase rates of the first branch and the second branch of the bandgap reference source circuit 310 are different (e.g., the current rise rate of the first transistor Q1 in the first branch is greater than that of the second transistor Q2 in the second branch), based on the current mirror principle, the gate current of the first NMOS transistor NM1 increases, thus pulling up the gate voltage of the first NMOS transistor NM1 and increasing the current flowing through it. At this time, the voltage division of the third resistor R3 increases, causing the voltage at the first voltage terminal Ngate to decrease (i.e., the gate voltage of the second NMOS transistor NM2 decreases). Through the voltage adjustment of the second NMOS transistor NM2, the output voltage Vout at the output voltage terminal Nout is reduced, thereby keeping the output voltage Vout constant.

[0088] For example, when the output load Rout increases, the output voltage Vout at the output voltage terminal Nout decreases. At this time, the reference voltage Vref at the reference voltage terminal Nref of the fourth resistor Rf1 and the fifth resistor Rf2 in the feedback sub-circuit 330 decreases, thereby reducing the current in the two bandgap reference branches of the bandgap reference source sub-circuit 310.

[0089] Because the current reduction rates of the first branch and the second branch of the bandgap reference source circuit 310 are different—for example, the current reduction rate of the first transistor Q1 in the first branch is greater than that of the second transistor Q2 in the second branch—based on the current mirror principle, the gate current of the first NMOS transistor NM1 decreases, thus pulling down its gate voltage and reducing the current flowing through it. At this time, the voltage division of the third resistor R3 decreases, causing the voltage at the first voltage terminal Ngate to increase (i.e., the gate voltage of the second NMOS transistor NM2 to increase). By adjusting the voltage of NMOS transistor NM2, the output voltage Vout at the output voltage terminal Nout is increased, thereby maintaining the output voltage Vout constant.

[0090] It should be noted that the structures of the first and second branches are merely illustrative examples, and the current changes of the first transistor Q1 and the second transistor Q2 are also merely illustrative examples and do not constitute a limitation on the embodiments of this disclosure. In some other embodiments, the first and second branches can have other structures, such as one or more transistors in the first branch and one or more transistors in the second branch. Alternatively, the positions of the first and second branches can be interchanged, etc.

[0091] According to embodiments of this disclosure, the bandgap reference source sub-circuit, voltage regulator sub-circuit, and feedback sub-circuit of the voltage regulator circuit constitute a negative feedback loop. When the output load at the output voltage terminal of the voltage regulator circuit changes, the voltage change at the reference voltage terminal Nref of the feedback sub-circuit is fed back to the bandgap reference source sub-circuit. This causes the bandgap reference source sub-circuit to change the voltage at the first voltage terminal Ngate of the voltage regulator sub-circuit according to the voltage change at the reference voltage terminal Nref. This, in turn, regulates the voltage at the output voltage terminal Nout by adjusting the voltage at the first voltage terminal, thus keeping the voltage at the output voltage terminal Nout constant. This voltage regulator circuit has a simple structure, avoids the need for a combination of BGR and LDO circuits to achieve a regulated voltage source output, reduces circuit power consumption, and is beneficial for applications in low-power circuit scenarios.

[0092] Figure 4 A schematic diagram of a reference voltage source according to an embodiment of the present disclosure is shown.

[0093] like Figure 4 As shown, the reference voltage source 400 includes a voltage regulator circuit 410. The voltage regulator circuit 410 is configured to provide a reference voltage Vout to the reference voltage source.

[0094] For example, the reference voltage Vout is a stable zero temperature coefficient voltage.

[0095] For example, the voltage regulator circuit 410 can be as follows: Figure 1 , Figure 2 or Figure 3 The voltage regulator circuit structure shown is not described in detail here.

[0096] It should be noted that the technical solutions of the embodiments of this disclosure are shown by way of example only in the above description, and do not mean that the embodiments of this disclosure are limited to the above steps and structures. Where possible, the steps and structures can be adjusted and omitted as needed. Therefore, some steps and units are not essential elements for implementing the overall inventive concept of the embodiments of this disclosure.

[0097] The present disclosure has now been described in conjunction with preferred embodiments. It should be understood that those skilled in the art can make various other changes, substitutions, and additions without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of the embodiments of the present disclosure is not limited to the specific embodiments described above, but should be defined by the appended claims.

Claims

1. A voltage regulator circuit, comprising: A bandgap reference source circuit (310) includes a reference voltage terminal (Nref), a first voltage terminal (Ngate), and an output voltage terminal (Nout); wherein the bandgap reference source circuit is configured to apply a reference voltage (Vref) to the reference voltage terminal (Nref), apply a first voltage (Vgate) to the first voltage terminal (Ngate), and apply an output voltage (Vout) to the output voltage terminal (Nout); A voltage regulator circuit (320), electrically connected to the first voltage terminal (Ngate) and the output voltage terminal (Nout), is configured to adjust the voltage of the output voltage terminal (Nout) according to the voltage of the first voltage terminal (Ngate); and The feedback sub-circuit (330) is electrically connected to the reference voltage terminal (Nref) and the output voltage terminal (Nout), and is configured to feed back the voltage of the output voltage terminal (Nout) to the bandgap reference source sub-circuit (310) based on the voltage of the reference voltage terminal (Nref). The voltage regulator circuit is configured to, when a change in the voltage of the reference voltage terminal (Nref) is detected, adjust the voltage of the output voltage terminal (Nout) according to the voltage of the first voltage terminal (Ngate) through the voltage regulator sub-circuit (320) so that the voltage of the output voltage terminal (Nout) remains constant. The bandgap reference source sub-circuit (310) includes: A first branch and a second branch; wherein the first branch includes a first PMOS transistor (PM1) and a first transistor (Q1); the second branch includes a second PMOS transistor (PM2), a second transistor (Q2), a first resistor (R1), and a second resistor (R2); the first branch and the second branch are configured to apply the reference voltage (Vref) to the reference voltage terminal (Nref) and apply the output voltage (Vout) to the output voltage terminal (Nout); The gate of the first PMOS transistor (PM1) is electrically connected to the drain of the first PMOS transistor (PM1), the drain is electrically connected to the collector of the first transistor (Q1), and the source is electrically connected to the first voltage terminal (Nout). The base of the first transistor (Q1) is electrically connected to the reference voltage terminal (Nref); The source of the second PMOS transistor (PM2) is electrically connected to the first voltage terminal (Nout), the gate is electrically connected to the gate of the first PMOS transistor (PM1), and the drain is electrically connected to the collector of the second transistor (Q2). The base of the second transistor (Q2) is electrically connected to the base of the first transistor (Q1), and the emitter is electrically connected to one end of the first resistor (R1). The other end of the first resistor (R1) is electrically connected to the emitter of the first transistor (Q1) and one end of the second resistor (R2); The other end of the second resistor (R2) is grounded; The third branch includes a first NMOS transistor (NM1) and a third PMOS transistor (PM3), configured to apply a first voltage (Vgate) to the first voltage terminal (Ngate); wherein, The drain of the first NMOS transistor (NM1) is electrically connected to the first voltage terminal (Ngate), the gate is electrically connected to the drain of the second PMOS transistor (PM2), and the source is electrically connected to the source of the third PMOS transistor (PM3). The gate of the third PMOS transistor (PM3) is electrically connected to one end of the second resistor (R2), and the drain is grounded; The third resistor (R3) has one end electrically connected to the power supply voltage (VDD) and the other end electrically connected to the drain of the first NMOS transistor (NM1) and the first voltage terminal (Ngate). The third resistor (R3) and the third branch constitute an amplification sub-circuit. The amplification sub-circuit is configured to adjust the voltage of the first voltage terminal (Ngate) according to the voltage of the reference voltage terminal (Nref) when the output load (Rout) of the output voltage (Vout) changes.

2. The voltage regulator circuit according to claim 1, wherein, The third branch also includes: A first capacitor (C1) is configured to perform signal compensation for the voltage regulator circuit. One end of the first capacitor (C1) is electrically connected to the drain of the first NMOS transistor (NM1), and the other end is electrically connected to the gate of the first NMOS transistor (NM1).

3. The voltage regulator circuit according to claim 1, wherein, The voltage regulator sub-circuit (320) includes: a second NMOS transistor (NM2); wherein, The drain of the second NMOS transistor (NM2) is electrically connected to the power supply voltage (VDD), the gate is electrically connected to the other end of the third resistor (R3) and the first voltage terminal (Ngate), and the source is electrically connected to the output voltage terminal (Nout).

4. The voltage regulator circuit according to claim 3, wherein, The feedback sub-circuit (330) includes: a fourth resistor (Rf1) and a fifth resistor (Rf2); wherein, One end of the fourth resistor (Rf1) is electrically connected to the source of the second NMOS transistor (NM2), and the other end is electrically connected to the reference voltage terminal (Nref). One end of the fifth resistor (Rf2) is electrically connected to the reference voltage terminal (Nref), and the other end is grounded.

5. The voltage regulator circuit according to claim 1 further includes: The second capacitor (C2) has one end electrically connected to the output voltage terminal (Nout) and the other end grounded, and is configured to filter the output signal of the output voltage terminal (Nout).

6. The voltage regulator circuit according to claim 1, wherein, The voltage at the reference voltage terminal (Nref) and the voltage at the output voltage terminal (Nout) are both voltages with zero temperature coefficient.

7. A reference voltage source, comprising: The voltage regulator circuit according to any one of claims 1 to 6, wherein the voltage regulator circuit is configured to provide a reference voltage to the reference voltage source.

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