Heat dissipation mode determination method and device, storage medium and electronic equipment

Abstract

A heat dissipation mode determination method and device, a storage medium and an electronic device are disclosed. The method comprises: determining a heat risk level corresponding to each of a plurality of chips included in a circuit board; determining, based on the heat risk level corresponding to each of the plurality of chips, a first target simulation heat dissipation parameter corresponding to a heat dissipation boss arranged on at least part of the plurality of chips; simulating the plurality of chips based on the first target simulation heat dissipation parameter, with the circuit board as a simulation object, to obtain a first target simulation junction temperature corresponding to each of the plurality of chips; and determining a target heat dissipation mode of the circuit board based on the first target simulation junction temperature corresponding to each of the plurality of chips and a maximum junction temperature corresponding to each of the plurality of chips. The embodiments of the present disclosure can efficiently and reliably distinguish whether a heat dissipation boss needs to be arranged on different chips.

Description

Technical Field

[0001] This disclosure relates to chip technology, and in particular to a method, apparatus, storage medium, and electronic device for determining heat dissipation methods. Background Technology

[0002] Generally, a circuit board can include multiple chips. As chip power consumption increases, heat dissipation can be enhanced at a lower cost by adding heat dissipation bumps to the chips. However, since adding too many heat dissipation bumps will significantly increase production costs and complexity, it is necessary to distinguish whether heat dissipation bumps are necessary for different chips. Summary of the Invention

[0003] This disclosure is made to efficiently and reliably distinguish whether different chips need to have heat dissipation bumps. Embodiments of this disclosure provide a method, apparatus, storage medium, and electronic device for determining heat dissipation methods.

[0004] According to one aspect of the present disclosure, a method for determining a heat dissipation method is provided, including:

[0005] Determine the thermal risk level of each of the multiple chips included in the circuit board;

[0006] Based on the thermal risk level corresponding to each of the plurality of chips, the first target simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some of the plurality of chips are determined.

[0007] Using the circuit board as the simulation object, the plurality of chips are simulated based on the first target simulation heat dissipation parameters to obtain the first target simulation junction temperature of each of the plurality of chips.

[0008] Based on the first target simulated junction temperature corresponding to each of the plurality of chips, and the maximum junction temperature corresponding to each of the plurality of chips, the target heat dissipation method of the circuit board is determined.

[0009] According to another aspect of the present disclosure, a heat dissipation mode determination device is provided, comprising:

[0010] The first determining module is used to determine the thermal risk level of each of the multiple chips included in the circuit board;

[0011] The second determining module is used to determine, based on the thermal risk level of each of the plurality of chips determined by the first determining module, the first target simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some of the plurality of chips.

[0012] The simulation module is used to simulate the multiple chips based on the first target simulation heat dissipation parameters determined by the second determining module, using the circuit board as the simulation object, to obtain the first target simulation junction temperature corresponding to each of the multiple chips.

[0013] The third determining module is used to determine the target heat dissipation method of the circuit board based on the first target simulated junction temperature corresponding to each of the plurality of chips obtained by the simulation module, and the maximum junction temperature corresponding to each of the plurality of chips.

[0014] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program for performing the above-described heat dissipation method determination method.

[0015] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising:

[0016] processor;

[0017] Memory used to store the processor's executable instructions;

[0018] The processor is configured to read the executable instructions from the memory and execute the instructions to implement the above-described heat dissipation method determination method.

[0019] Based on the heat dissipation method, apparatus, storage medium, and electronic device provided in the above embodiments of this disclosure, the first target simulation heat dissipation parameters can be determined by referring to the thermal risk level of each of the multiple chips included in the circuit board. The first target simulation heat dissipation parameters are then used to simulate the multiple chips, thereby efficiently and reliably obtaining the first target simulation junction temperature of each of the multiple chips through simulation calculation. The first target simulation junction temperature can effectively reflect the working junction temperature of the chip under real working conditions. Combined with the maximum junction temperature of each of the multiple chips, the target heat dissipation method of the circuit board can be determined efficiently and reliably. The target heat dissipation method can be used to indicate whether it is necessary to set heat dissipation bumps for different chips. Thus, by adopting the embodiments of this disclosure, it is possible to efficiently and reliably distinguish whether it is necessary to set heat dissipation bumps for different chips.

[0020] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0022] Figure 1 This is a flowchart illustrating a method for determining a heat dissipation mode provided in an exemplary embodiment of this disclosure.

[0023] Figure 2 This is a flowchart illustrating a method for determining a heat dissipation mode provided in another exemplary embodiment of this disclosure.

[0024] Figure 3 This is a flowchart illustrating a method for determining a heat dissipation method provided in another exemplary embodiment of this disclosure.

[0025] Figure 4 This is a flowchart illustrating a method for determining a heat dissipation mode provided in yet another exemplary embodiment of this disclosure.

[0026] Figure 5 This is a flowchart illustrating a method for determining a heat dissipation mode provided in yet another exemplary embodiment of this disclosure.

[0027] Figure 6 This is a flowchart illustrating a method for determining a heat dissipation mode provided in yet another exemplary embodiment of this disclosure.

[0028] Figure 7 This is a flowchart illustrating a method for determining a heat dissipation mode provided in yet another exemplary embodiment of this disclosure.

[0029] Figure 8 This is a schematic diagram of the structure of a heat dissipation method determination device provided in an exemplary embodiment of the present disclosure.

[0030] Figure 9 This is a schematic diagram of the structure of a heat dissipation method determination device provided in another exemplary embodiment of this disclosure.

[0031] Figure 10 This is a schematic diagram of the structure of a heat dissipation method determination device provided in another exemplary embodiment of the present disclosure.

[0032] Figure 11 This is a schematic diagram of the structure of a heat dissipation method determination device provided in another exemplary embodiment of this disclosure.

[0033] Figure 12 This is a schematic diagram of the structure of a heat dissipation method determination device provided in another exemplary embodiment of this disclosure.

[0034] Figure 13 This is a schematic diagram of the structure of a heat dissipation method determination device provided in another exemplary embodiment of this disclosure.

[0035] Figure 14 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0036] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0037] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0038] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent specific technical meanings or necessary logical sequences.

[0039] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0040] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0041] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0042] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0043] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0044] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0045] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0046] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0047] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0048] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are performed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0049] Application Overview

[0050] A circuit board may include multiple chips; for example, a circuit board in a vehicle's domain controller may include multiple artificial intelligence (AI) chips.

[0051] As chip power consumption increases, heat dissipation can be enhanced at a lower cost by adding heat dissipation bumps to the chip, which can quickly transfer heat to air coolers or liquid coolers. However, adding too many heat dissipation bumps significantly increases production costs and complexity; therefore, it is necessary to distinguish whether heat dissipation bumps are necessary for different chips. How to efficiently and reliably distinguish whether heat dissipation bumps are necessary for different chips is a problem that urgently needs to be solved by those skilled in the art.

[0052] Exemplary Overview

[0053] In the embodiments of this disclosure, computer simulation technology (CST) can be used to efficiently and reliably distinguish whether different chips need to be provided with heat dissipation bumps.

[0054] Understandably, computer simulation technology is a comprehensive technology that utilizes the achievements of computer science and technology to build a model of the system being simulated and to conduct dynamic experiments on the model under certain experimental conditions. It has advantages such as high efficiency, safety, and less constraint from environmental conditions, and has become an important tool for analyzing, designing, operating, evaluating, and training systems (especially complex systems).

[0055] Optionally, computer simulation technology may include computational fluid dynamics (CFD) simulation technology.

[0056] Understandably, CFD simulation technology is equivalent to conducting experiments "virtually" on a computer. It uses numerical solutions to solve the differential equations used to control fluid flow, and obtains the discrete distribution of the fluid flow field in a continuous region, thereby approximately simulating the actual fluid flow.

[0057] Exemplary methods

[0058] Figure 1 This is a flowchart illustrating a method for determining a heat dissipation mode provided in an exemplary embodiment of this disclosure. Figure 1 The method shown may include steps 110, 120, 130 and 140, which are described below.

[0059] Step 110: Determine the thermal risk level of each of the multiple chips included in the circuit board.

[0060] Optionally, the circuit board can be located in the vehicle's domain controller, or in other electronic systems within the vehicle besides the domain controller. Of course, the circuit board can also be located in other electronic devices outside the vehicle.

[0061] Optionally, the circuit board may include: a substrate and a plurality of chips disposed on the substrate; wherein, the substrate may be a printed circuit board (PCB); the plurality of chips may refer to all the chips disposed on the substrate, or to a portion of the chips disposed on the substrate.

[0062] It should be noted that the thermal risk level of a chip can refer to the risk level of the chip overheating. The higher the thermal risk level, the more likely the chip is to overheat, and the lower the thermal risk level, the less likely the chip is to overheat.

[0063] Optionally, the thermal risk levels can be divided into n+1 levels in order of increasing level: Level 0, Level 1, Level 2, ..., Level n-1, Level n.

[0064] Step 120: Based on the thermal risk level of each of the multiple chips, determine the first target simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some of the multiple chips.

[0065] In step 120, by referring to the thermal risk level of each chip, several chips that need to be verified for the rationality of setting up heat dissipation protrusions can be determined from the multiple chips (for ease of description, the set of these chips will be referred to as the first chip group to be verified). Based on the determination results, heat dissipation characteristic values ​​are determined for each of the multiple chips to obtain the first target simulation heat dissipation parameters composed of the heat dissipation characteristic values ​​of each of the multiple chips.

[0066] Optionally, for each of the multiple chips, if the chip is located in the first chip group to be verified, the first preset feature value used to characterize the setting of heat dissipation protrusions can be determined as the heat dissipation feature value corresponding to the chip; if the chip is not located in the first chip group to be verified, the second preset feature value used to characterize the absence of heat dissipation protrusions can be determined as the heat dissipation feature value corresponding to the chip.

[0067] Optionally, the first preset feature value can be 1 and the second preset feature value can be 0; or, the first preset feature value can be YES and the second preset feature value can be NO.

[0068] Step 130: Using the circuit board as the simulation object, simulate multiple chips based on the first target simulation heat dissipation parameters to obtain the first target simulation junction temperature of each chip.

[0069] In step 130, the circuit board drawings, dimensions, materials, and other information, as well as the first target simulation heat dissipation parameters, can be provided to the computer simulation software. Based on this, the computer simulation software can build a model of the circuit board, simulate the working conditions of each chip in the first chipset to be verified having heat dissipation protrusions, and conduct dynamic experiments on the circuit board model to obtain the first target simulation junction temperature of each chip through simulation calculation.

[0070] It is understandable that junction temperature usually refers to the highest temperature of a semiconductor chip in an electronic device. It is typically higher than the case temperature and the device surface temperature, and can be used to measure the chip's heat dissipation capacity from the semiconductor wafer to the case.

[0071] Step 140: Based on the first target simulated junction temperature of each of the multiple chips and the maximum junction temperature of each of the multiple chips, determine the target heat dissipation method of the circuit board.

[0072] Optionally, the maximum junction temperature corresponding to the chip can refer to the maximum junction temperature that the chip can withstand, which is pre-designed for the chip; the maximum junction temperatures corresponding to different chips can be the same or different.

[0073] In step 140, by combining the first target simulated junction temperature of each chip and the maximum junction temperature of each chip, it is possible to evaluate which chips among the chips need to have heat dissipation bumps and which chips do not need to have heat dissipation bumps, thereby obtaining the target heat dissipation method including the evaluation results.

[0074] Based on the heat dissipation method determination method provided in the above embodiments of this disclosure, the first target simulation heat dissipation parameters can be determined by referring to the thermal risk level of each of the multiple chips included in the circuit board. The first target simulation heat dissipation parameters are then used to simulate the multiple chips, thereby efficiently and reliably obtaining the first target simulation junction temperature of each of the multiple chips through simulation calculation. The first target simulation junction temperature can effectively reflect the working junction temperature of the chip under real working conditions. Combined with the maximum junction temperature of each of the multiple chips, the target heat dissipation method of the circuit board can be determined efficiently and reliably. The target heat dissipation method can be used to indicate whether it is necessary to set heat dissipation bumps for different chips. Thus, by adopting the embodiments of this disclosure, it is possible to efficiently and reliably distinguish whether it is necessary to set heat dissipation bumps for different chips.

[0075] exist Figure 1 Based on the illustrated embodiments, as Figure 2 As shown, step 120 includes steps 1201, 1203, 1205, 1207, 1209 and 1211.

[0076] Step 1201: Determine the first set of chips among multiple chips whose corresponding thermal risk level is the first preset thermal risk level.

[0077] Optionally, the first preset thermal risk level can be the highest thermal risk level. Taking the case where the thermal risk levels are divided into n+1 levels in order of increasing level as an example, the first preset thermal risk level can be Level n.

[0078] Step 1203: Determine the first reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some chips in the first set.

[0079] In step 1203, several chips that need to be verified for the rationality of setting heat dissipation protrusions can be determined from the first set (for ease of description, the set of these chips will be referred to as the second chip group to be verified). Based on the determination results, heat dissipation characteristic values ​​are determined for multiple chips respectively (the specific determination method can refer to the method of determining heat dissipation characteristic values ​​for chips in order to obtain the first target simulation heat dissipation parameters mentioned above). Thus, the first reference simulation heat dissipation parameters can be obtained.

[0080] Step 1205: Using the circuit board as the simulation object, simulate multiple chips based on the first reference simulation heat dissipation parameters to obtain the first reference simulation junction temperature corresponding to each of the multiple chips.

[0081] It should be noted that the specific implementation of step 1205 can be referred to the description of step 130, and will not be repeated here.

[0082] Step 1207: Based on the first reference simulation junction temperature corresponding to each of the multiple chips and the maximum junction temperature corresponding to each of the multiple chips, determine the second set of chips among the multiple chips whose corresponding thermal risk level is between the first preset thermal risk level and the second preset thermal risk level, and which meet the preset over-temperature conditions. The level of the second preset thermal risk level is lower than that of the first preset thermal risk level, and there is a preset number of thermal risk levels between them.

[0083] Optionally, the preset quantity can be 0, 1, 2, or other quantities. That is, the second preset thermal risk level can be a thermal risk level that is one, two, three, or more levels lower than the first preset thermal risk level. For ease of understanding, the embodiments of this disclosure are all illustrated with the case where the preset quantity is 0 and the second preset thermal risk level is a thermal risk level that is one level lower than the first preset thermal risk level. That is, the second preset thermal risk level can be Level n-1.

[0084] In step 1207, from multiple chips, each chip whose corresponding thermal risk level is between the first preset thermal risk level and the second preset thermal risk level (including both the first preset thermal risk level and the second preset thermal risk level themselves) can be determined. For each determined chip, the difference between the chip's maximum junction temperature and the first reference simulation junction temperature can be used to determine whether the chip meets the preset over-temperature condition.

[0085] Assume the first reference simulation result for the chip is represented by T1, and the maximum junction temperature for the chip is represented by T. max The difference between the maximum junction temperature of the chip and the first reference simulated junction temperature can be represented by T. max Characterized by -T1, or using (T max -T1) / T maxCharacterization can be performed. Optionally, it can be done in T. max - If T1 is greater than the preset difference, the chip is determined to meet the preset over-temperature condition; or, it can be determined that (T) max -T1) / T max If the temperature exceeds the first preset ratio, the chip is determined to meet the preset over-temperature condition. The methods for determining whether a chip meets the preset over-temperature condition described below are the same as those in this section and will not be repeated hereafter.

[0086] The set of chips whose corresponding thermal risk levels are between the first preset thermal risk level and the second preset thermal risk level, and which meet the preset over-temperature conditions, can be used as the second set.

[0087] Step 1209: Determine the second reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of each chip in the second set.

[0088] It should be noted that the specific implementation of step 1209 can be referred to the description of step 1203, and will not be repeated here.

[0089] Step 1211: Determine the first target simulation heat dissipation parameters based on the second preset thermal risk level and the second reference simulation heat dissipation parameters.

[0090] In one specific embodiment, step 1211 includes:

[0091] In response to the second preset thermal risk level being the lowest thermal risk level, the second reference simulation heat dissipation parameters are determined as the first target simulation heat dissipation parameters;

[0092] In response to the second preset thermal risk level not being the lowest thermal risk level, using the circuit board as the simulation object, multiple chips are simulated based on the second reference simulation heat dissipation parameters to obtain the second reference simulation junction temperature corresponding to each chip. Based on the second reference simulation junction temperature and the maximum junction temperature corresponding to each chip, a third set of chips is determined, whose corresponding thermal risk level is between the first and third preset thermal risk levels and meets the preset over-temperature conditions. The third preset thermal risk level is lower than the second preset thermal risk level and is separated from the second preset thermal risk level by a preset number of thermal risk levels. The third reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of each chip in the third set are determined. Based on the third preset thermal risk level and the third reference simulation heat dissipation parameters, the first target simulation heat dissipation parameters are determined.

[0093] It should be noted that the method for determining the first target simulation heat dissipation parameters based on the third preset thermal risk level and the third reference simulation heat dissipation parameters can be the same as the method for determining the first target simulation heat dissipation parameters based on the second preset thermal risk level and the second reference simulation heat dissipation parameters. It is only necessary to regard the third preset thermal risk level as a new second preset thermal risk level and the third reference simulation heat dissipation parameters as a new second reference simulation heat dissipation parameters.

[0094] In a specific example, the thermal risk levels can be divided into three levels, from lowest to highest: Level 0, Level 1, and Level 2. Multiple chips can be represented as 30 chips, numbered I1, I2, I3, ..., I... 30 Among them, I1 to I 10 Corresponding to Level 2, I 11 to I 22 Corresponding to Level 1, I 23 to I 30 Corresponding to Level 0.

[0095] Assuming the first preset thermal risk level is Level 2, then the first set may include I1 to I 10 Assuming the first reference simulation thermal parameters correspond to the case where all chips in the first set have heat dissipation bumps, the circuit board can be used as the simulation object. Based on the first reference simulation thermal parameters, a first simulation is performed on 30 chips to obtain the first reference simulation junction temperature for each of the 30 chips. Based on the first reference simulation junction temperatures of each of the 30 chips, and the maximum junction temperatures of each of the 30 chips, temperatures can be ranged from I1 to I... 22 Chips that meet the preset over-temperature conditions are selected to form a second set. Assume the second set includes I1 to I5 and I... 18 to I 22 The second reference simulation thermal parameters correspond to I1 to I5 and I... 18 to I 22 Each of these 10 chips has a heat dissipation protrusion.

[0096] Assuming the second preset thermal risk level is Level 1 and the third preset thermal risk level is Level 0, it's clear that the second preset thermal risk level is not the lowest level. Therefore, the circuit board can be used as the simulation object. Based on the second reference simulation thermal parameters, a second simulation can be performed on the 30 chips to obtain the second reference simulation junction temperature for each of the 30 chips. Combined with the maximum junction temperature for each of the 30 chips, the temperature can be calculated from I1 to I... 30 From the individual chips, those that meet the preset over-temperature conditions are selected to form a third set. Assume the third set includes I1 to I5, I... 18to I 20 and I 23 to I 28 Then we can determine I1 to I5, I 18 to I 20 and I 23 to I 28 Each heat dissipation protrusion has its own third reference simulation heat dissipation parameters. Since the third preset thermal risk level is already the lowest level, the third reference simulation heat dissipation parameters can be directly set as the first target simulation heat dissipation parameters.

[0097] It should be noted that, assuming that Level 0, which is the third preset thermal risk level, is not the lowest thermal risk level, for example, there is a Level 0′ which is one level lower than Level 0, the circuit board can be used as the simulation object. Based on the third reference simulation heat dissipation parameters, the multiple chips included in the circuit board can be simulated to obtain the reference simulation junction temperature of each chip. Then, combined with the maximum junction temperature of each chip, the chips that meet the preset over-temperature conditions can be selected from the chips whose corresponding thermal risk levels are between Level 2 and Level 0′ to form another set. The subsequent processing is similar to that after the third set is determined above, and will not be repeated here.

[0098] As can be seen, by referring to whether the second preset thermal risk level is the lowest thermal risk level, one can choose to directly determine the second reference simulation heat dissipation parameter as the first target simulation heat dissipation parameter, or, based on the data obtained from simulating multiple chips based on the second reference simulation heat dissipation parameter, include the chips with overheating among the lower-level chips in the category of chips for which the rationality of setting heat dissipation protrusions needs to be verified, and perform simulation again, and determine the appropriate first target simulation heat dissipation parameter by referring to the data obtained from the second simulation. This helps to ensure the rationality and reliability of the finally determined first target simulation heat dissipation parameter.

[0099] It should be noted that the specific implementation of step 1211 is not limited to this. For example, if the second preset thermal risk level is the lowest thermal risk level, the second reference simulation heat dissipation parameter may not be directly determined as the first target simulation heat dissipation parameter. Instead, the second reference simulation heat dissipation parameter may be presented to the user, who may manually correct the second reference simulation heat dissipation parameter and use the correction result of the second reference simulation heat dissipation parameter as the first target simulation heat dissipation parameter.

[0100] In addition, after obtaining the second reference simulation heat dissipation parameters by executing step 1209, the second reference simulation heat dissipation parameters can be directly determined as the first target simulation heat dissipation parameters, without having to determine the first target simulation heat dissipation parameters based on whether the second preset thermal risk level is the lowest level of thermal risk.

[0101] In the embodiments of this disclosure, starting with the chip with the highest corresponding thermal risk level, the rationality of setting heat dissipation protrusions on the chip is verified through simulation. Then, chips with relatively lower corresponding thermal risk levels can be gradually included in the scope of chips whose rationality of setting heat dissipation protrusions needs to be verified, and simulation is performed again until the first target simulated heat dissipation parameters are obtained. In this way, the rationality and reliability of the finally determined first target simulated heat dissipation parameters can be guaranteed through multiple simulations, and the efficiency of determining the first target simulated heat dissipation parameters can be guaranteed by using thermal risk levels.

[0102] In one optional example, step 1203 includes:

[0103] The fourth reference simulation thermal parameters are determined so that none of the chips in the multiple chips have heat dissipation protrusions;

[0104] Using the circuit board as the simulation object, multiple chips are simulated based on the fourth reference simulation heat dissipation parameters to obtain the third reference simulation junction temperature of each chip.

[0105] Based on the third reference simulation junction temperature corresponding to each of the multiple chips, and the maximum junction temperature corresponding to each of the multiple chips, the chips in the first set that meet the preset over-temperature conditions are determined.

[0106] The chips in the first set that meet the preset over-temperature conditions are respectively set with the first reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions.

[0107] In the embodiments of this disclosure, the heat dissipation characteristic values ​​corresponding to each of the multiple chips can be set to a second preset characteristic value to obtain a fourth reference simulation heat dissipation parameter. The fourth reference simulation heat dissipation parameter corresponds to the case where none of the chips have heat dissipation bumps. Next, the circuit board drawings, dimensions, materials, and other information, as well as the fourth reference simulation heat dissipation parameter, can be provided to computer simulation software. The computer simulation software can then build a model of the circuit board, simulate the working condition where none of the chips have heat dissipation bumps, and conduct dynamic experiments on the circuit board model to obtain the third reference simulation junction temperature corresponding to each of the multiple chips through simulation calculations. For each chip in the first set, the difference between the maximum junction temperature corresponding to the reference chip and the third reference simulation junction temperature can determine whether the chip meets the preset over-temperature condition. This allows us to identify each chip in the first set that meets the preset over-temperature condition, and thus obtain the first reference simulation heat dissipation parameter. Here, the first reference simulation heat dissipation parameter corresponds to the case where only the chips in the first set that meet the preset over-temperature condition have heat dissipation bumps. Chips that are prone to over-temperature phenomena are the chips that truly need to have heat dissipation bumps. Therefore, the first reference simulation heat dissipation parameter is highly targeted, which helps to ensure the rationality and reliability of the subsequently determined first target simulation heat dissipation parameter.

[0108] Of course, the specific implementation of step 1205 is not limited to this. For example, the first reference simulation heat dissipation parameters can directly correspond to the case where all chips in the first set are provided with heat dissipation protrusions.

[0109] exist Figure 1 Based on the illustrated embodiments, as Figure 3 As shown, step 140 includes steps 1401, 1403, 1405, 1407, and 1409.

[0110] Step 1401: Based on the first target simulated junction temperature corresponding to each of the multiple chips and the maximum junction temperature corresponding to each of the multiple chips, determine the fourth set of chips that meet the preset over-temperature conditions among the multiple chips.

[0111] In step 1401, for each of the multiple chips, the difference between the chip's maximum junction temperature and the first target simulated junction temperature can be used to determine whether the chip meets the preset over-temperature condition. The set of chips that meet the preset over-temperature condition can be used as the fourth set.

[0112] Step 1403: Determine the second target simulation heat dissipation parameters corresponding to the heat dissipation protrusions of each chip in the fourth set.

[0113] It should be noted that the specific implementation of step 1403 can be referred to the description of step 1203, and will not be repeated here.

[0114] Step 1405: Using the circuit board as the simulation object, simulate multiple chips based on the second target simulation heat dissipation parameters to obtain the second target simulation junction temperature of each chip.

[0115] It should be noted that the specific implementation of step 1405 can be referred to the description of step 130, and will not be repeated here.

[0116] Step 1407: For each of the multiple chips, determine the first temperature difference between the maximum junction temperature of that chip and the second target simulated junction temperature.

[0117] In step 1407, for each of the multiple chips, the difference between the maximum junction temperature corresponding to the chip and the second target simulated junction temperature can be calculated to obtain the first temperature difference corresponding to the chip.

[0118] Step 1409: Based on the first temperature difference corresponding to each of the multiple chips and the fourth set, determine the target heat dissipation method of the circuit board.

[0119] Optionally, the target heat dissipation method determined in step 1409 can be used to indicate that each chip in the fourth set needs to be equipped with a heat dissipation bump. For each chip in the fourth set, the material and size of the heat dissipation bump can be determined by referring to the first temperature difference corresponding to the chip. For example, the larger the first temperature difference corresponding to the chip, the better the thermal conductivity of the heat dissipation bump can be. In addition, if a thermal interface material is provided between the chip and the heat dissipation bump, the thermal interface material can also be selected according to the first temperature difference corresponding to the chip. That is, the target heat dissipation method can not only indicate which chips need to be equipped with heat dissipation bumps, but also indicate the material and size of the heat dissipation bumps, as well as the selection of a thermal interface material.

[0120] In the embodiments of this disclosure, by combining the first target simulated junction temperature and the maximum junction temperature of each of the multiple chips, a fourth set of chips that meet the preset over-temperature conditions can be efficiently and reliably determined. For the fourth set, second target simulated heat dissipation parameters can be determined, and the second target simulated junction temperature of each of the multiple chips can be obtained through simulation. By combining the maximum junction temperature of each of the multiple chips, the first temperature difference of each of the multiple chips can be obtained. The first temperature difference of each of the multiple chips and the fourth set can be used together to determine the target heat dissipation method. In this way, the determined target heat dissipation method can not only be used to indicate whether different chips need to be equipped with heat dissipation bumps, but also to indicate what material and size the heat dissipation bumps should be made of, and what thermal interface should be selected. This can provide an effective reference for the design of chips, circuit boards, and even the entire domain controller.

[0121] exist Figure 1 Based on the illustrated embodiments, as Figure 4 As shown, step 110 includes steps 1101, 1103 and 1105.

[0122] Step 1101: Determine the theoretical junction temperature of each of the multiple chips included in the circuit board.

[0123] Optionally, the theoretical junction temperature of the chip can refer to the junction temperature obtained through theoretical calculation for the chip.

[0124] In one specific embodiment, step 1101 includes:

[0125] Determine the cooling method of the circuit board, calculate the safety factor for the chip junction temperature, and the third temperature difference between the circuit board and the ambient temperature;

[0126] Determine the temperature of the cooling medium corresponding to the cooling method;

[0127] Determine the sum of the cooling medium temperature and the third temperature difference;

[0128] For each of the multiple chips, calculate the product of the chip junction temperature calculation safety factor, the chip's heat generation power, and the chip's junction thermal resistance. Based on the sum of the product, the cooling medium temperature, and the sum of the values, determine the theoretical junction temperature corresponding to the chip.

[0129] Optionally, the cooling method of the circuit board can be manually set, including but not limited to air cooling and liquid cooling; the safety factor for calculating the chip junction temperature can be a safety factor estimated based on experience; the ambient temperature can be manually set, and the third temperature difference between the circuit board and the ambient temperature can be a temperature difference that is manually set or estimated based on experience; the temperature of the cooling medium corresponding to the cooling method can be manually set, and the temperature of the cooling medium corresponding to the air cooling method can refer to the ambient temperature, while the temperature of the cooling medium corresponding to the liquid cooling method can refer to the inlet temperature of the coolant.

[0130] Alternatively, the theoretical junction temperature of the chip can be calculated using the following formula:

[0131] T pcb =T α +△T pcb

[0132] T j '=k×P×R jb +T α +T pcb

[0133] Among them, T α Indicates the temperature of the cooling medium, ΔT pcb Indicates the third temperature difference, T pcb T represents the sum of the cooling medium temperature and the third temperature difference. j ' represents the theoretical junction temperature of the chip, k represents the safety factor for calculating the chip junction temperature, P represents the heat dissipation power of the chip, and R jb This indicates the thermal resistance of the chip's bonding plate.

[0134] It's understandable that the chip's junction thermal resistance can refer to the thermal resistance between the chip's heat source junction and the PCB. It should be noted that R... jb There are two cases. In one case, R jb It can refer to the chip's own thermal resistance on the board; in another case, R... jb This could refer to the junction thermal resistance of the chip estimated empirically.

[0135] In this implementation, the theoretical junction temperature of the chip is determined efficiently and reliably by using simple calculation logic such as addition and multiplication operations, based on the cooling medium temperature corresponding to the cooling method of the reference circuit board, the chip junction temperature calculation safety factor, and the third temperature difference between the circuit board and the ambient temperature.

[0136] Of course, the specific implementation of step 1101 is not limited to this; for example, in obtaining T in the above formula... j After that, T can be manually adjusted. j Make corrections and put T j The correction result of ' is used as the theoretical junction temperature corresponding to the chip.

[0137] Step 1103: Determine the maximum junction temperature for each of the multiple chips.

[0138] Optionally, the maximum junction temperature of each of the multiple chips can be preset.

[0139] Step 1105: Based on the theoretical junction temperature and the maximum junction temperature of each chip, determine the thermal risk level of each chip.

[0140] In one specific embodiment, step 1105 includes:

[0141] For each of the multiple chips, determine the second temperature difference between the maximum junction temperature and the theoretical junction temperature for that chip;

[0142] For each of the multiple chips, determine the temperature range to which the second temperature difference belongs, where different temperature ranges correspond to different thermal risk levels;

[0143] Based on the temperature range to which each of the multiple second temperature differences corresponds to multiple chips, the thermal risk level of each of the multiple chips is determined.

[0144] It should be noted that multiple temperature ranges can be preset, and a correspondence between these temperature ranges and their corresponding thermal risk levels can be established. Optionally, there can be a one-to-one correspondence between the temperature ranges and the thermal risk levels.

[0145] For each of the multiple chips, the difference between the chip's maximum junction temperature and the theoretical junction temperature can be used to obtain the chip's second temperature difference. The chip's second temperature difference can be considered as the chip's junction temperature design margin, and the thermal risk level corresponding to the temperature difference range to which the chip's second temperature difference belongs can be used as the chip's thermal risk level.

[0146] In a specific example, the correspondence between multiple temperature ranges and their corresponding thermal risk levels can be found in Table 1 below. Based on the information recorded in Table 1, the thermal risk level of each of the multiple chips can be determined.

[0147]

[0148] Table 1

[0149] According to Table 1, (﹣∞,N1]、(N1,N2]、(N2,N3]、……、(N n-1 N n ]、(N n +∞) can each represent a temperature range. Additionally, ΔT j This can represent the second temperature difference corresponding to the chip. Thus, the chip's design margin can be expressed as ΔT. j Or T max —T j '.

[0150] Assuming the second error corresponding to the chip falls within the temperature difference range of (N2, N3), then according to the information recorded in Table 1, the thermal risk level corresponding to the chip can be Level 2.

[0151] In this implementation, by pre-setting the correspondence between multiple temperature difference ranges and corresponding thermal risk levels, the thermal risk level of the chip can be determined efficiently and reliably by simply calculating the difference between the maximum junction temperature and the theoretical junction temperature of the chip and based on the distribution of the obtained second temperature difference relative to multiple temperature difference ranges.

[0152] Of course, the specific implementation of step 1105 is not limited to this. For example, multiple proportional ranges and corresponding thermal risk levels can be pre-defined. After the difference between the maximum junction temperature and the theoretical junction temperature of the chip is calculated to obtain the second temperature difference, the obtained second temperature difference can be divided by the theoretical junction temperature of the chip, and the thermal risk level corresponding to the proportional range to which the division result belongs can be used as the thermal risk level of the chip.

[0153] In the embodiments of this disclosure, for each of the multiple chips, the design margin of the chip can be effectively assessed by referring to the difference between the theoretical junction temperature and the maximum junction temperature of the chip. Specifically, the greater the difference between the theoretical junction temperature and the maximum junction temperature, the greater the design margin of the chip can be considered, and the smaller the difference between the theoretical junction temperature and the maximum junction temperature of the chip, the smaller the design margin of the chip can be considered. Based on the design margin, a reasonable thermal risk level can be determined for the chip. For example, the greater the design margin of the chip, the higher the thermal risk level of the chip can be.

[0154] exist Figure 4 Based on the illustrated embodiments, as Figure 5 As shown, the method provided in the embodiments of this disclosure may further include steps 150, 160 and 170.

[0155] Step 150: After simulating multiple chips, determine the simulation temperature of the area on the circuit board corresponding to each of the multiple chips.

[0156] Optionally, for each of the multiple chips, the simulated temperature of the area on the circuit board corresponding to the chip can refer to the temperature of the area on the circuit board where the chip is located, calculated by computer simulation software.

[0157] Step 160: For each of the multiple chips, determine the fourth temperature difference between the simulated temperature of the corresponding region and the ambient temperature.

[0158] In step 160, for each of the multiple chips, the difference between the simulated temperature of the corresponding area of ​​the chip and the ambient temperature can be calculated to obtain the fourth temperature difference corresponding to the chip.

[0159] Step 170: Based on the multiple fourth temperature differences corresponding to multiple chips, update the theoretical junction temperature corresponding to each of the multiple chips, and then execute step 1105 again.

[0160] In step 170, for each of the multiple chips, the third temperature difference corresponding to the chip can be updated to the fourth temperature difference corresponding to the chip. Then, the updated third temperature difference is substituted into the relevant calculation formula of the theoretical junction temperature mentioned above to calculate the new theoretical junction temperature corresponding to the chip.

[0161] In the embodiments of this disclosure, a fourth temperature difference can be determined by using computer simulation technology, and the theoretical junction temperature of the chip obtained by pure theoretical calculation can be updated accordingly. Subsequently, multiple chips can be reclassified based on the updated theoretical junction temperature to obtain the corresponding thermal risk level. This helps to ensure the rationality and reliability of the thermal risk level of each of the multiple chips that are finally determined.

[0162] exist Figure 1 Based on the illustrated embodiments, as Figure 6 As shown, step 110 includes steps 1107, 1109 and 1111.

[0163] Step 1107: Determine the junction-case thermal resistance of each chip included in the circuit board.

[0164] It is understandable that the junction-to-case thermal resistance of a chip can refer to the thermal resistance between the chip's heat source junction and its outer casing. Optionally, the junction-to-case thermal resistance of a chip can be expressed as R. jc .

[0165] Step 1109: Select multiple chips from all the chips included in the circuit board whose junction thermal resistance is less than the preset thermal resistance.

[0166] In step 1109, the junction thermal resistance of each chip in the circuit board can be compared with a preset thermal resistance to select multiple chips whose junction thermal resistance is less than the preset thermal resistance.

[0167] Step 1111: Determine the thermal risk level of each of the multiple chips whose junction-to-shell thermal resistance is less than the preset thermal resistance.

[0168] Generally, if the junction thermal resistance of a chip is too high, the heat generated during actual operation will not be excessive, the chip will not heat up significantly, and it will not have a major impact on the normal operation of the circuit board or even the domain controller. Therefore, in the embodiments of this disclosure, only a few chips with junction thermal resistance less than a preset thermal resistance can be selected from all the chips included in the circuit board. The corresponding thermal risk level is determined only for these selected chips to further determine whether a heat dissipation bump is needed. This eliminates the need to verify the need for heat dissipation bumps on all chips included in the circuit board, thus improving verification efficiency.

[0169] In an optional example, such as Figure 7 As shown, to differentiate whether different chips require heat dissipation bumps, the cooling method can be determined for the circuit board, and relevant parameters can be estimated. These parameters include, but are not limited to, the safety factor k for calculating the chip junction temperature and the third temperature difference ΔT between the circuit board and the ambient temperature. pcb Based on this, the chip junction temperature can be theoretically calculated to obtain the theoretical junction temperature of each of the multiple chips included in the circuit board. According to the theoretical junction temperatures of each chip, and combined with their respective maximum junction temperatures, the junction temperature design margin for each chip can be calculated by subtraction. Based on the obtained junction temperature design margin, the chips can be classified to obtain their respective thermal risk levels. For example, the chips can be divided into Level 0, Level 1, Level 2, ..., Level n-1, Level n.

[0170] Next, we can determine the first version of the heat dissipation structure where no heat dissipation bumps are set on all levels of chips, and perform simulation calculations to obtain the junction temperature of chips at different levels, and mark the chips that exceed the temperature (equivalent to determining the fourth reference simulation heat dissipation parameter corresponding to the determination of all chips in multiple chips without heat dissipation bumps in the above text; using the circuit board as the simulation object, we simulate multiple chips based on the fourth reference simulation heat dissipation parameter to obtain the third reference simulation junction temperature corresponding to each of the multiple chips; based on the third reference simulation junction temperature corresponding to each of the multiple chips, and the maximum junction temperature corresponding to each of the multiple chips, we determine the chips in the first set that meet the preset over-temperature conditions).

[0171] Afterwards, the design verification of all Level n chips can be performed. For Level n chips that exceed the temperature limit, heat dissipation bumps and thermal interface materials can be designed. Based on this, the second version of the heat dissipation structure (corresponding to the first reference simulation heat dissipation parameters mentioned above) can be determined, and simulation calculations can be performed to obtain the junction temperature of all chips.

[0172] Next, for Level n-1 and Level n chips, and for the chips identified as overheating in the previous simulation, heat dissipation bumps and thermal interface materials can be designed. Based on this, the third version of the heat dissipation structure (corresponding to the second reference simulation heat dissipation parameters mentioned above) can be determined, and simulation calculations can be performed to obtain the junction temperature of all chips. This process is repeated until the (n+1)th version of the heat dissipation structure is determined, thereby identifying which chips require heat dissipation bumps and which do not.

[0173] Optionally, after each simulation, the theoretical junction temperature can be updated based on the simulated regional temperature obtained from the simulation, so as to redetermine the thermal risk level of each of the multiple chips.

[0174] In summary, by using the embodiments of this disclosure, it is possible to efficiently and reliably distinguish whether different chips need to be provided with heat dissipation protrusions.

[0175] Any of the heat dissipation method determination methods provided in this disclosure can be executed by any suitable device with data processing capabilities, including but not limited to: terminal devices and servers. Alternatively, any of the heat dissipation method determination methods provided in this disclosure can be executed by a processor, such as by a processor executing any of the heat dissipation method determination methods mentioned in this disclosure by calling corresponding instructions stored in memory. Further details will not be elaborated below.

[0176] Exemplary device

[0177] Figure 8 This is a schematic diagram of the structure of a heat dissipation method determination device provided in an exemplary embodiment of the present disclosure. Figure 8 The device shown includes a first determining module 810, a second determining module 820, a simulation module 830, and a third determining module 840.

[0178] The first determining module 810 is used to determine the thermal risk level of each of the multiple chips included in the circuit board.

[0179] The second determining module 820 is used to determine the first target simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some of the chips based on the heat risk levels of the multiple chips determined by the first determining module 810.

[0180] The simulation module 830 is used to simulate multiple chips based on the first target simulation heat dissipation parameters determined by the second determination module 820, using the circuit board as the simulation object, to obtain the first target simulation junction temperature of each chip.

[0181] The third determining module 840 is used to determine the target heat dissipation method of the circuit board based on the first target simulation junction temperature of each of the multiple chips obtained by the simulation module 830, and the maximum junction temperature of each of the multiple chips.

[0182] In an optional example, such as Figure 9 As shown, the second determining module 820 includes:

[0183] The first determining submodule 8201 is used to determine a first set of chips among multiple chips whose corresponding thermal risk level is a first preset thermal risk level;

[0184] The second determining submodule 8203 is used to determine the first reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some chips in the first set determined by the first determining submodule 8201.

[0185] The first simulation submodule 8205 is used to simulate multiple chips based on the first reference simulation heat dissipation parameters determined by the second determination submodule 8203, using the circuit board as the simulation object, to obtain the first reference simulation junction temperature of each chip.

[0186] The third determining submodule 8207 is used to determine, based on the first reference simulation junction temperature of each of the multiple chips obtained by the first simulation submodule 8205, and the maximum junction temperature of each of the multiple chips, a second set of chips whose corresponding thermal risk level is between the first preset thermal risk level and the second preset thermal risk level, and which meet the preset over-temperature condition. The level of the second preset thermal risk level is lower than that of the first preset thermal risk level, and there is a preset number of thermal risk levels between them.

[0187] The fourth determining submodule 8209 is used to determine the second reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of each chip in the second set determined by the third determining submodule 8207.

[0188] The fifth determining submodule 8211 is used to determine the first target simulation heat dissipation parameters based on the second preset thermal risk level and the second reference simulation heat dissipation parameters determined by the fourth determining submodule 8209.

[0189] In one optional example, the fifth determining submodule 8211 includes:

[0190] The first determining unit is used to determine the second reference simulation heat dissipation parameter determined by the fourth determining submodule 8209 as the first target simulation heat dissipation parameter in response to the second preset thermal risk level being the lowest thermal risk level.

[0191] The second determining unit is used to respond to the second preset thermal risk level not being the lowest thermal risk level, using the circuit board as the simulation object, and to simulate multiple chips based on the second reference simulation heat dissipation parameters determined by the fourth determining submodule 8209, to obtain the second reference simulation junction temperature corresponding to each of the multiple chips; based on the second reference simulation junction temperature and the maximum junction temperature corresponding to each of the multiple chips, to determine a third set of chips whose corresponding thermal risk level is between the first and third preset thermal risk levels and meets the preset over-temperature conditions, wherein the third preset thermal risk level is lower than the second preset thermal risk level and is separated from the second preset thermal risk level by a preset number of thermal risk levels; to determine the third reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of each chip in the third set; and to determine the first target simulation heat dissipation parameters based on the third preset thermal risk level and the third reference simulation heat dissipation parameters.

[0192] In one optional example, the second determining submodule 8203 includes:

[0193] The third determining unit is used to determine the fourth reference simulation heat dissipation parameters corresponding to the fact that none of the chips in the multiple chips have heat dissipation protrusions.

[0194] The simulation unit is used to simulate multiple chips based on the fourth reference simulation heat dissipation parameters determined by the third determination unit, using the circuit board as the simulation object, to obtain the third reference simulation junction temperature of each chip.

[0195] The fourth determining unit is used to determine the chips that meet the preset over-temperature conditions in the first set determined by the first determining submodule 8201 based on the third reference simulation junction temperature of each of the multiple chips obtained by the simulation unit and the maximum junction temperature of each of the multiple chips.

[0196] The fifth determining unit is used to determine the first reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of the chips in the first set determined by the first determining submodule 8201 that meet the preset over-temperature conditions.

[0197] In an optional example, such as Figure 10 As shown, the third determining module 840 includes:

[0198] The sixth determining submodule 8401 is used to determine the fourth set of chips that meet the preset over-temperature conditions among the multiple chips based on the first target simulation junction temperature of each of the multiple chips obtained by the simulation module 830 and the maximum junction temperature of each of the multiple chips.

[0199] The seventh determining submodule 8403 is used to determine the second target simulation heat dissipation parameters corresponding to the heat dissipation protrusions set for each chip in the fourth set determined by the sixth determining submodule 8401.

[0200] The second simulation submodule 8405 is used to simulate multiple chips based on the second target simulation heat dissipation parameters determined by the seventh determination submodule 8403, using the circuit board as the simulation object, to obtain the second target simulation junction temperature of each chip.

[0201] The eighth determination submodule 8407 is used to determine, for each of the multiple chips, the first temperature difference between the maximum junction temperature corresponding to the chip and the second target simulation junction temperature corresponding to the chip determined by the second simulation submodule 8405.

[0202] The ninth determining submodule 8409 is used to determine the target heat dissipation method of the circuit board based on the first temperature difference corresponding to each of the multiple chips determined by the eighth determining submodule 8407 and the fourth set determined by the sixth determining submodule 8401.

[0203] In an optional example, such as Figure 11 As shown, the first determining module 810 includes:

[0204] The tenth determining submodule 8101 is used to determine the theoretical junction temperature of each of the multiple chips included in the circuit board;

[0205] The eleventh determination submodule 8103 is used to determine the maximum junction temperature of each of the multiple chips;

[0206] The twelfth determination submodule 8105 is used to determine the thermal risk level of each of the multiple chips based on the theoretical junction temperature of each of the multiple chips determined by the tenth determination submodule 8101 and the maximum junction temperature of each of the multiple chips determined by the eleventh determination submodule 8103.

[0207] In one optional example, the twelfth determined submodule 8105 includes:

[0208] The sixth determining unit is used to determine, for each of the multiple chips, the second temperature difference between the maximum junction temperature corresponding to the chip determined by the tenth determining submodule 8101 and the theoretical junction temperature corresponding to the chip determined by the eleventh determining submodule 8103.

[0209] The seventh determining unit is used to determine, for each of the multiple chips, the temperature difference range to which the second temperature difference corresponding to the chip determined by the sixth determining unit belongs, wherein different temperature difference ranges correspond to different thermal risk levels;

[0210] The eighth determining unit is used to determine the thermal risk level of each of the multiple chips based on the temperature difference range to which each of the multiple second temperature differences corresponding to the multiple chips determined by the seventh determining unit belongs.

[0211] In one optional example, the tenth determining submodule 8101 includes:

[0212] The ninth determining unit is used to determine the cooling method of the circuit board, the safety factor for calculating the chip junction temperature, and the third temperature difference between the circuit board and the ambient temperature.

[0213] The tenth determining unit is used to determine the temperature of the cooling medium corresponding to the cooling method determined by the ninth determining unit;

[0214] The eleventh determining unit is used to determine the sum of the cooling medium temperature determined by the tenth determining unit and the third temperature difference;

[0215] The twelfth determining unit is used to calculate, for each of the multiple chips, the product of the chip junction temperature calculation safety factor determined by the ninth determining unit, the heat generation power of the chip, and the junction thermal resistance of the chip, and to determine the theoretical junction temperature of the chip based on the sum of the product, the cooling medium temperature determined by the ninth determining unit, and the sum of the values.

[0216] In an optional example, such as Figure 12 As shown, the apparatus provided in the embodiments of this disclosure further includes:

[0217] The fourth determination module 850 is used to determine the simulation temperature of the area on the circuit board corresponding to each of the multiple chips after simulating multiple chips.

[0218] The fifth determining module 860 is used to determine, for each of the multiple chips, the fourth temperature difference between the simulated temperature of the region corresponding to the chip and the ambient temperature, as determined by the fourth determining module 850.

[0219] The update module 870 is used to update the theoretical junction temperature of each chip based on the multiple fourth temperature differences corresponding to the multiple chips determined by the fifth determination module 860, and to trigger the twelfth determination submodule 8105.

[0220] In an optional example, such as Figure 13 As shown, the first determining module 810 includes:

[0221] The thirteenth determination submodule 8107 is used to determine the junction-case thermal resistance of each chip included in the circuit board;

[0222] The screening submodule 8109 is used to screen from all the chips included in the circuit board multiple chips that the junction-case thermal resistance determined by the thirteenth determination submodule 8107 is less than the preset thermal resistance.

[0223] The fourteenth determination submodule 8111 is used to determine the thermal risk level of each of the multiple chips whose junction-shell thermal resistance is less than the preset thermal resistance, as selected by the screening submodule 8109.

[0224] In the apparatus disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed above can be flexibly selected and combined as needed to achieve the corresponding functions and effects, and this disclosure does not list them all.

[0225] Exemplary electronic devices

[0226] Below, for reference Figure 14 This describes an electronic device according to embodiments of the present disclosure. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0227] Figure 14 A block diagram of an electronic device 1400 according to an embodiment of the present disclosure is shown.

[0228] like Figure 14 As shown, the electronic device 1400 includes one or more processors 1410 and memory 1420.

[0229] The processor 1410 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.

[0230] The memory 1420 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1410 may execute the program instructions to implement the heat dissipation method determination method of the various embodiments of this disclosure described above and / or other desired functions. Various contents such as input signals, signal components, and noise components may also be stored in the computer-readable storage medium.

[0231] In one example, the electronic device 1400 may also include an input device 1430 and an output device 1440, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0232] For example, when electronic device 1400 is a first device or a second device, the input device 1430 may be a microphone or a microphone array. When electronic device 1400 is a standalone device, the input device 1430 may be a communication network connector for receiving acquired input signals from the first device and the second device.

[0233] In addition, the input device 1430 may also include, for example, a keyboard, a mouse, etc.

[0234] The output device 1440 can output various information to the outside. The output device 1440 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0235] Of course, for the sake of simplicity, Figure 14 Only some of the components of the electronic device 1400 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1400 may include any other suitable components depending on the specific application.

[0236] Exemplary computer program products and computer-readable storage media

[0237] In addition to the methods and devices described above, embodiments of this disclosure may also be computer program products, including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the heat dissipation method determination method according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0238] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0239] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the heat dissipation method determination method according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0240] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0241] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. The specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the specific details described above.

[0242] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0243] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0244] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0245] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0246] The above description of the disclosed aspects is provided to enable those skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. This disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0247] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for determining a heat dissipation method, comprising: Determine the thermal risk level of each of the multiple chips included in the circuit board; Based on the thermal risk level corresponding to each of the plurality of chips, the first target simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some of the plurality of chips are determined. Using the circuit board as the simulation object, the plurality of chips are simulated based on the first target simulation heat dissipation parameters to obtain the first target simulation junction temperature of each of the plurality of chips. Based on the first target simulated junction temperature corresponding to each of the plurality of chips, and the maximum junction temperature corresponding to each of the plurality of chips, the target heat dissipation method of the circuit board is determined.

2. The method according to claim 1, wherein, The step of determining the first target simulated heat dissipation parameters corresponding to the heat dissipation protrusions of at least a portion of the chips based on the respective thermal risk levels of the chips includes: A first set of chips is determined among the plurality of chips that correspond to a first preset thermal risk level; Determine the first reference simulation heat dissipation parameters corresponding to at least a portion of the chips in the first set having heat dissipation protrusions; Using the circuit board as a simulation object, the plurality of chips are simulated based on the first reference simulation heat dissipation parameters to obtain the first reference simulation junction temperature of each of the plurality of chips. Based on the first reference simulation junction temperature corresponding to each of the plurality of chips, and the maximum junction temperature corresponding to each of the plurality of chips, a second set of chips is determined among the plurality of chips whose corresponding thermal risk level is between the first preset thermal risk level and the second preset thermal risk level, and which meet the preset over-temperature condition. The level of the second preset thermal risk level is lower than the first preset thermal risk level, and there is a preset number of thermal risk levels between them. Determine the second reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of each chip in the second set; Based on the second preset thermal risk level and the second reference simulation heat dissipation parameters, the first target simulation heat dissipation parameters are determined.

3. The method according to claim 2, wherein, The step of determining the first target simulation heat dissipation parameters based on the second preset thermal risk level and the second reference simulation heat dissipation parameters includes: In response to the second preset thermal risk level being the lowest thermal risk level, the second reference simulation heat dissipation parameter is determined as the first target simulation heat dissipation parameter; In response to the second preset thermal risk level not being the lowest thermal risk level, using the circuit board as the simulation object, the plurality of chips are simulated based on the second reference simulation heat dissipation parameters to obtain the second reference simulation junction temperature corresponding to each of the plurality of chips; based on the second reference simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips, a third set of chips is determined among the plurality of chips whose corresponding thermal risk level is between the first preset thermal risk level and the third preset thermal risk level, and which meet the preset over-temperature condition, wherein the third preset thermal risk level is lower than the second preset thermal risk level and is separated from the second preset thermal risk level by a preset number of thermal risk levels; the third reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of each chip in the third set are determined; based on the third preset thermal risk level and the third reference simulation heat dissipation parameters, the first target simulation heat dissipation parameters are determined.

4. The method according to claim 2, wherein, Determining the first reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least a portion of the chips in the first set includes: The fourth reference simulation heat dissipation parameters are determined to be the parameters corresponding to the fact that none of the chips in the plurality of chips have heat dissipation protrusions. Using the circuit board as the simulation object, the plurality of chips are simulated based on the fourth reference simulation heat dissipation parameters to obtain the third reference simulation junction temperature of each of the plurality of chips. Based on the third reference simulation junction temperature corresponding to each of the multiple chips, and the maximum junction temperature corresponding to each of the multiple chips, determine the chips in the first set that meet the preset over-temperature conditions; The chips in the first set that meet the preset over-temperature conditions are respectively equipped with the first reference simulation heat dissipation parameters corresponding to the heat dissipation protrusions.

5. The method according to claim 1, wherein, The step of determining the target heat dissipation method for the circuit board based on the first target simulated junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips includes: Based on the first target simulated junction temperature corresponding to each of the plurality of chips, and the maximum junction temperature corresponding to each of the plurality of chips, a fourth set of chips that meet the preset over-temperature conditions is determined among the plurality of chips. Determine the second target simulation heat dissipation parameters corresponding to the heat dissipation protrusions set for each chip in the fourth set; Using the circuit board as the simulation object, the plurality of chips are simulated based on the second target simulation heat dissipation parameters to obtain the second target simulation junction temperature of each of the plurality of chips. For each of the plurality of chips, determine a first temperature difference between the maximum junction temperature corresponding to that chip and the second target simulated junction temperature; Based on the first temperature difference corresponding to each of the multiple chips, and the fourth set, the target heat dissipation method of the circuit board is determined.

6. The method according to claim 1, wherein, The determination of the thermal risk level of each of the multiple chips included in the circuit board includes: Determine the theoretical junction temperature of each of the multiple chips included in the circuit board; Determine the maximum junction temperature corresponding to each of the plurality of chips; Based on the theoretical junction temperature and the maximum junction temperature of each of the multiple chips, the thermal risk level of each of the multiple chips is determined.

7. The method according to claim 6, wherein, The determination of the thermal risk level of each of the multiple chips based on their respective theoretical junction temperatures and their respective maximum junction temperatures includes: For each of the plurality of chips, a second temperature difference between the maximum junction temperature and the theoretical junction temperature corresponding to that chip is determined; For each of the plurality of chips, the temperature difference range to which the second temperature difference belongs is determined, wherein different temperature difference ranges correspond to different thermal risk levels; Based on the temperature difference range to which each of the multiple second temperature differences corresponding to the multiple chips belongs, the thermal risk level corresponding to each of the multiple chips is determined.

8. The method according to claim 6, wherein, Determining the theoretical junction temperature of each of the multiple chips included in the circuit board includes: Determine the cooling method of the circuit board, calculate the safety factor for the chip junction temperature, and determine the third temperature difference between the circuit board and the ambient temperature; Determine the temperature of the cooling medium corresponding to the cooling method; Determine the sum of the temperature of the cooling medium and the third temperature difference; For each of the plurality of chips, the product of the chip junction temperature calculation safety factor, the chip's heat generation power, and the chip's junction thermal resistance is calculated, and the theoretical junction temperature corresponding to the chip is determined based on the sum of the product, the cooling medium temperature, and the sum of the values.

9. The method according to claim 6, further comprising: After simulating the plurality of chips, the simulation temperature of the area on the circuit board corresponding to each of the plurality of chips is determined; For each of the plurality of chips, a fourth temperature difference between the simulated temperature of the region corresponding to that chip and the ambient temperature is determined; Based on the multiple fourth temperature differences corresponding to the multiple chips, update the theoretical junction temperature corresponding to each of the multiple chips, and then perform the step of determining the thermal risk level corresponding to each of the multiple chips based on the theoretical junction temperature and the maximum junction temperature corresponding to each of the multiple chips again.

10. The method according to any one of claims 1-9, wherein determining the thermal risk level corresponding to each of the plurality of chips included in the circuit board includes; Determine the junction-case thermal resistance of each chip included in the circuit board; From all the chips included in the circuit board, select a number of chips whose junction thermal resistance is less than a preset thermal resistance; Determine the thermal risk level of each of the plurality of chips whose junction thermal resistance is less than the preset thermal resistance.

11. A heat dissipation method determination device, comprising: The first determining module is used to determine the thermal risk level of each of the multiple chips included in the circuit board; The second determining module is used to determine, based on the thermal risk level of each of the plurality of chips determined by the first determining module, the first target simulation heat dissipation parameters corresponding to the heat dissipation protrusions of at least some of the plurality of chips. The simulation module is used to simulate the multiple chips based on the first target simulation heat dissipation parameters determined by the second determining module, using the circuit board as the simulation object, to obtain the first target simulation junction temperature corresponding to each of the multiple chips. The third determining module is used to determine the target heat dissipation method of the circuit board based on the first target simulated junction temperature corresponding to each of the plurality of chips obtained by the simulation module, and the maximum junction temperature corresponding to each of the plurality of chips.

12. A computer-readable storage medium storing a computer program for performing the heat dissipation method determination method according to any one of claims 1-10.

13. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the heat dissipation method determination method according to any one of claims 1-10.

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