A Compilation Optimization Method and System Based on High-Order Cryptographic Operators for Heterogeneous Platforms

Abstract

The present invention discloses a compilation optimization method and system for high-order cryptographic operators on heterogeneous platforms. The method includes: Step 1: According to the domain-specific language, through the analysis of encryption and decryption algorithms, design and implement a domain-specific language for describing tensor operations, and perform the extraction and analysis of operators; Step 2: Through the tensorization and parallelization of data, reorganize the calculations to efficiently utilize the memory hierarchy and parallel execution hardware; Step 3: Implement high-order operators through an end-to-end compilation framework and map the high-order operators to heterogeneous hardware; Step 4: Compile and optimize the high-order operators mapped to the hardware to obtain the compiled and optimized high-order operators; Step 5: Compile the hardware-executable code according to the compiled and optimized high-order operators. The present invention solves the domain-specific language abstraction, memory optimization, compilation mapping of complex operators, and efficiently constructs high-performance algorithms and hardware deployments in the field of encryption and decryption.

Description

Technical Field

[0001] The present invention relates to the technical field of compilation optimization, and in particular to a compilation optimization method and system for high-order cryptographic operators on heterogeneous platforms. Background Art

[0002] With the rapid development of cryptographic algorithms, early-designed cryptographic algorithms such as MD4, MD5, and SHA-1 can no longer meet the security requirements. On this basis, SHA-2 and SHA-3 series algorithms have been developed. While improving the security of the algorithms, the algorithm structures have become more and more complex, resulting in an increasing calculation time of cryptographic algorithms. The performance of existing cryptographic algorithms can no longer meet the requirements. As the computing power requirements of cryptographic algorithms for chips are getting higher and higher, conveniently and efficiently using these computing resources has gradually become a key issue affecting chip applications. This not only requires the design of the chip, but also requires the compilation technology to keep up. It requires both software and hardware to be well done to fully utilize the performance of many-core processors. Deploying upper-layer applications to hardware must be solved through software toolchains. For example, Corelet in the United States, PyNN used in the middle, and Tianjic toolchain of Tsinghua University have all played a great role, and the computing performance has been improved through the software-hardware cooperation method. To achieve hardware diversity and effectively map the calculation to the hardware to obtain higher performance, programmers must be familiar with the characteristics of the target hardware architecture, and then rewrite the program code in a domain-specific language or add guiding statements to the code. Because the optimized code is related to the target hardware architecture, it will make the source program difficult to maintain and transplant, reduce the usability of the compilation system, and greatly increase the time cost of software development.

[0003] Traditional CPUs or GPUs are difficult to efficiently process cryptographic algorithms. Using the programmability of FPGAs for cryptographic algorithm development can combine flexibility and efficiency. However, FPGA programming is complex and lacks a fast and efficient design and deployment method. For this reason, the present invention proposes a method for abstracting, compiling and optimizing, and mapping different granularity operators to solve the problem of fast and efficient deployment of high-order cryptographic operators on FPGAs. By abstracting hot operators from cryptographic algorithms, using a multi-level compilation optimization framework to add domain-specific intermediate representation dialects, an operator library is constructed. And through tensorization and register optimization, the mapping of high-order cryptographic operators on a specific hardware architecture is improved. Summary of the Invention

[0004] Aiming at the problem of lacking fast and efficient deployment on heterogeneous platforms in operator abstraction, compilation optimization, and mapping in the field of password cracking, the present invention proposes a compilation optimization method and system for high-order cryptographic operators on heterogeneous platforms.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] On the one hand, the present invention proposes a compilation optimization method for high-order cryptographic operators on heterogeneous platforms, including:

[0007] Step 1: According to the domain-specific language, through the analysis of encryption and decryption algorithms, design and implement a domain-specific language for describing tensor operations, and perform the extraction and analysis of operators;

[0008] Step 2: Through the tensorization and parallelization of data, reorganize the calculations to efficiently utilize the memory hierarchy and parallel execution hardware;

[0009] Step 3: Implement high-order operators through an end-to-end compilation framework and map the high-order operators to heterogeneous hardware;

[0010] Step 4: Compile and optimize the high-order operators mapped to the hardware to obtain the compiled and optimized high-order operators;

[0011] Step 5: Compile the hardware-executable code according to the compiled and optimized high-order operators.

[0012] Further, the step 1 includes:

[0013] First, perform "atomic-level" operator abstraction, extract the "atomic-level" operators through function-level operation rules to construct application-level high-order operators, that is, coarse-grained operators.

[0014] Further, the step 3 includes:

[0015] Step 3.1: Through the analysis of hash-based cryptographic algorithms, inject the "atomic-level" operators to be mapped into the arithmetic logic unit (ALU) microcode operations through "optimization passes", and add the corresponding encoding information to the environment variables to prepare for generating high-order operators;

[0016] Step 3.2: According to the mapped "atomic-level" operators, register the function-level operator expressions and the built-in function expressions of the corresponding operator names in the compilation framework; when there is no corresponding built-in function for the operator, the compiler translates the function-level operator into a combination of operations of "atomic-level" operators according to the registered built-in function expressions; map all the abstracted "atomic-level" operators to the built-in functions with the same name in the compilation backend;

[0017] Step 3.3: Add a Python call interface for function-level operators. This interface registers the call name, data type, and operator operation parameters on the Python side of the high-order operator as call nodes in the compilation framework. The call nodes use the language interaction FFI interface in the compilation framework to associate the functions defined in C++ in the compilation framework with Python in the form of Python PackedFunc objects, thus realizing cross-language calls;

[0018] Step 3.4: Add the operation codes of the high-order operators in the hardware environment respectively so that the hardware can recognize them;

[0019] Step 3.5: Add the conversion rules of the high-order operators in the "optimization pass" of the built-in operator injection compilation in the hardware architecture. According to this rule, the compiler maps the operator name to the corresponding operation code and generates the ALU instructions of the hardware architecture containing the operation code.

[0020] Further, the said Step 4 includes:

[0021] Place all the computations and storages in the algorithm-level operators into the VTA for execution;

[0022] Add new compilation rules in the "optimization pass" to automate the data backup process.

[0023] On the other hand, the present invention proposes a compilation optimization system for heterogeneous platforms based on high-order cryptographic operators, including:

[0024] An operator extraction module, which is used to design and implement a domain-specific language for describing tensor operations through the analysis of encryption and decryption algorithms according to the domain-specific language, and perform operator extraction and analysis;

[0025] A tensorization module, which is used to reorganize the computations to efficiently utilize the memory hierarchy and parallel execution hardware through the tensorization and parallelization of data;

[0026] A mapping module, which is used to implement high-order operators through an end-to-end compilation framework and map the high-order operators to heterogeneous hardware;

[0027] A compilation optimization module, which is used to compile and optimize the high-order operators mapped to the hardware to obtain the compiled and optimized high-order operators;

[0028] A compilation module, which is used to compile and obtain the hardware-executable code according to the compiled and optimized high-order operators.

[0029] Further, the said operator extraction module is specifically used for:

[0030] First, perform "atomic-level" operator abstraction, extract the "atomic-level" operators through function-level operation rules to construct application-level high-order operators, that is, coarse-grained operators.

[0031] Further, the said mapping module is specifically used for:

[0032] Through the analysis of hash-based cryptographic algorithms, inject the "atomic-level" operators to be mapped into the arithmetic logic unit (ALU) microcode operations through the "optimization pass", and add the corresponding encoding information in the environment variables to prepare for the generation of high-order operators;

[0033] Register function-level operator expressions and built-in function expressions corresponding to the operator names in the compilation framework according to the mapped "atomic-level" operators; when there is no corresponding built-in function for the operator, the compiler translates the function-level operator into a combination of operations of "atomic-level" operators according to the registered built-in function expressions; map all the abstracted "atomic-level" operators to the built-in functions with the same name in the compilation backend;

[0034] Add a Python call interface for function-level operators. This interface registers the call name, data type, and operator operation parameters on the Python side of the high-order operator as call nodes in the compilation framework. The call nodes use the language interaction FFI interface in the compilation framework to associate the functions defined in C++ in the compilation framework with Python in the form of Python PackedFunc objects, thus realizing cross-language calls;

[0035] Add the operation codes of high-order operators in the hardware environment respectively so that the hardware can recognize them;

[0036] Add conversion rules for high-order operators in the compilation "pass" of injecting built-in operators in the ALU of the hardware architecture. According to this rule, the compiler maps the operator name to the corresponding operation code and generates the ALU instructions of the hardware architecture containing the operation code.

[0037] Furthermore, the compilation optimization module is specifically used for:

[0038] Place all the computations and storages in the algorithm-level operators into the VTA for execution;

[0039] Add new compilation rules in the "pass" to automate the data backup process.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] According to the domain-specific language, by analyzing the algorithms in the encryption and decryption fields, extract and analyze the core computational operators; through this compilation framework, realize the transformation from "atomic-level" operators to "function-level" operators and then to "high-order operators", map the high-order operators to different hardware through compilation, and perform compilation optimization on the operators mapped to the hardware; according to the optimized high-order operators after compilation, convert them into machine language that can be recognized by the underlying hardware. The present invention solves the problems of domain-specific language abstraction, memory optimization, compilation mapping of complex operators, and efficiently constructs high-performance algorithms and hardware deployments in the encryption and decryption fields.

[0042] Compared with the existing operator compilation abstractions, the present invention solves the problems of higher-order operator abstraction and higher-order operator mapping. Compared with traditional compilation optimization methods, the present invention uses a tensorization method to improve computational efficiency and reduce hardware execution time, which can increase the computational efficiency by 32 times on the basis of the original computational efficiency. Through the register optimization method, the problem of memory data being overwritten is solved, and the automated memory data processing reduces the workload of programmers and makes compilation more automated. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 FIG. is a schematic flowchart of a method for compiling and optimizing a high-order cryptographic operator on a heterogeneous platform according to an embodiment of the present invention;

[0044] Figure 2 PRINCIPLES OF OPERATOR EXTRACTION ACCORDING TO AN EMBODIMENT OF THE PRESENT INVENTION;

[0045] Figure 3 IMPLEMENTATION METHOD OF HIGH-ORDER OPERATOR MAPPING ACCORDING TO AN EMBODIMENT OF THE PRESENT INVENTION;

[0046] Figure 4 EXAMPLE OF REPETITIVE USE OF TENSORIZED DATA ACCORDING TO AN EMBODIMENT OF THE PRESENT INVENTION;

[0047] Figure 5 EXAMPLE OF SINGLE-INSTRUCTION MULTIPLE-DATA IMPLEMENTATION WITH TENSORIZATION OF 16 ACCORDING TO AN EMBODIMENT OF THE PRESENT INVENTION;

[0048] Figure 6 EXAMPLE OF SINGLE-INSTRUCTION MULTIPLE-THREAD IMPLEMENTATION WITH TENSORIZATION OF 2 * 16 * 16 ACCORDING TO AN EMBODIMENT OF THE PRESENT INVENTION;

[0049] Figure 7 SCHEMATIC DIAGRAM OF MEMORY OPTIMIZATION EFFECT ACCORDING TO AN EMBODIMENT OF THE PRESENT INVENTION;

[0050] Figure 8 ARCHITECTURE DIAGRAM OF A SYSTEM FOR COMPILING AND OPTIMIZING A HIGH-ORDER CRYPTOGRAPHIC OPERATOR ON A HETEROGENEOUS PLATFORM ACCORDING TO AN EMBODIMENT OF THE PRESENT INVENTION. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] The following further explains the present invention with reference to the accompanying drawings and specific embodiments:

[0052] As Figure 1 shown, a method for compiling and optimizing a high-order cryptographic operator on a heterogeneous platform includes:

[0053] Step S101: According to the domain-specific language, through the analysis of encryption and decryption algorithms, design and implement a domain-specific language for describing tensor operations, and perform operator extraction and analysis;

[0054] Step S102: Through data tensorization and parallelization, reorganize the calculations to efficiently utilize the memory hierarchy and parallel execution hardware;

[0055] Step S103: Implement high-order operators through an end-to-end compilation framework and map the high-order operators to heterogeneous hardware;

[0056] Step S104: Compile and optimize the high-order operators mapped to the hardware to obtain the compiled and optimized high-order operators;

[0057] Step S105: Compile the hardware executable code according to the compiled and optimized high-order operators.

[0058] The present invention is directed to an optimization method for high-order cryptographic operators on a heterogeneous platform, thereby improving the computing speed and resource occupancy rate of high-order cryptographic operators on the heterogeneous platform. This method solves the domain-specific language abstraction, memory optimization, compilation mapping of complex operators, and efficiently constructs high-performance programs.

[0059] The specific introduction is as follows:

[0060] 1. Operator extraction principle

[0061] In order to effectively map the computation to various different hardware, the operators need to be adapted to different hardware. Therefore, it is necessary to implement the operators and solve the operator adaptation problem through compilation optimization and mapping. First, perform "atomic-level" operator abstraction, and extract "function-level" operators from the "atomic-level" operators through "function-level" operation rules to construct application-level "high-order operators" - "algorithm-level" operators, that is, coarse-grained operators. Operators that implement multi-instruction operation functions.

[0062] As Figure 2 shown, the present invention provides an operator abstraction principle. First, perform "atomic-level" operator abstraction. The "atomic-level" operator is the smallest operation unit of the program and cannot be further subdivided during the compilation abstraction process. Basic operation units, such as: logical operations (AND, OR, NOT, XOR), arithmetic operations (multiplication, addition, assignment), shift operations, substitution operations (S-box), permutation operations. "Function-level" operators are combinations of atomic-level operators and are presented in polynomial form. Function-level operators provide operator combination templates for typical algorithms to adapt to customized algorithms. "Algorithm-level" operators are an independent set of algorithms, such as MD5, SHA1, etc. By using these operators, the application requirements or development requirements of users can be directly met.

[0063] Through the analysis of hash-based cryptographic algorithms, different levels of operator abstraction are performed, providing support for the construction of high-order operators.

[0064] In the present invention, taking MD5 as an example: perform operator extraction at different granularities. The "atomic-level" operators in the MD5 algorithm include: logical AND &, logical OR |, logical NOT ~, logical XOR ^, logical circular left shift <<, addition operation.

[0065] (1) "Function-level" operator extraction:

[0066] All the arithmetic operations used in MD5 are shown in the following table:

[0067] Operation Explanation & Logical AND | Logical OR ^ Logical XOR ～ Logical NOT << The left shift operation, such as "x << n", means that x is shifted left by n bits, and the vacant positions generated by the left shift are filled with 0 >> The right shift operation, such as "x << n", means that x is shifted left by n bits, and the empty positions generated by the left shift are filled with 0 <![CDATA[ROTL n (x)]]> The circular left shift operation is equivalent to "(x << n) | (x >> L - n)", where L is the number of bits of x

[0068] (1) The operator extraction principle of the four "function-level" kernel functions in MD5, where the input b = 0Xefcdab89, c = 0X98badcfe, d = 0X10325476:

[0069] F(b, c, d) = (b & c) | (~b & d)

[0070] G(b, c, d) = (b & d) | (c & ~d))

[0071] H(b, c, d) = (b ^ c ^ d)

[0072] I(b, c, d) = (c ^ (b | ~d))

[0073] (2) The 64-round calculation of MD5 is completed through the calculations of the following four functions FF, GG, HH, and II. Each function loops 16 times, and the result output by each round of calculation is used as the input for the next round of calculation. a = 0X657452301e, W i represents the input 512-bit message, T i represents the bit random number generated by the sine function, and n represents the number of bits of cyclic left shift. Among them, the value range of i is (0 - 63).

[0074] FF(a, b, c, d, n, i) = b + ROTL n (a + F(b, c, d) + W i + T i )

[0075] GG(a, b, c, d, n, i) = b + ROTL n (a + G(b, c, d) + W i + T i )

[0076] HH(a, b, c, d, n, i) = b + ROTL n (a + H(b, c, d) + W i + T i )

[0077] II(a, b, c, d, n, i) = b + ROTL n (a + I(b, c, d) + W i + T i )

[0078] At the development end, it is encapsulated into four kernel functions using Python. Users only need to call the following five interfaces to implement MD5 encryption. The parameters that users need to input are a, b, c, d, message, and n:

[0079]

[0080]

[0081] (2) "Algorithm-level" operator extraction:

[0082] For the MD5 input, a = 0X657452301e, b = 0Xefcdab89, c = 0X98badcfe, d = 0X10325476. The 64 rounds of MD5 calculation are completed through the calculation of the following KK function. The result output in each round is used as the input for the next round of calculation. W i represents the input 512-bit message, and T i represents the bit random number generated by the sine function, and n represents the number of bits of circular left shift. Among them, the value range of i is (0 - 63), and the value range of k is (0 - 3).

[0083] M(b, c, d)0 = (b & c) | (~b & d)

[0084] M(b, c, d)1 = (b & d) | (c & ~d))

[0085] M(b, c, d)2 = (b ^ c ^ d)

[0086] M(b, c, d)3 = (c ^ (b | ~d))

[0087] KK(a, b, c, d, n, k, i) = b + ROTL n (a + M k (b, c, d) + W i + T i )

[0088] At the development end, it is encapsulated into a kernel function using Python. Users only need to call the following one interface to implement MD5 encryption. The parameters that users need to input are a, b, c, d, w, t, and n. Users can directly call the following function, which greatly facilitates the developers on the user side:

[0089] md5(a, b, c, d, w, t, n)

[0090] 2. High-order operator mapping method for applications

[0091] According to the analysis of operators with different granularities in hash-based cryptographic algorithms, through the compilation mapping of multi-level intermediate representation (IR), operators with different granularities at each stage are mapped to the corresponding hardware. Modularize the logical operations that require a large number of repeated calculations and map each module into the implementation of the hardware circuit to solve the operator adaptation problem and the problems of domain application performance and flexibility.

[0092] Use TE (tensor expression) to generate calculation rules, and perform operator-level optimization given scheduling rules (including how to execute calculations specifically, how to load and store data, and what means to use for loop tiling, loop unrolling, and multi-threading). Schedule the operator to run on the VTA device, and the specific operation execution method needs to be specified. The complete process of an operator includes the load, compute, and store processes. In the load stage, the input message is copied to the corresponding buffer through DMA (Direct Memory Access), in the compute stage, calculations are performed on the ALU, and in the store stage, the final calculation result is copied from the output buffer to the DRAM through DMA. The scheduling process specifies the computing unit for data execution, the method of data copying, and the destination buffer.

[0093] After operator-level optimization, a low-level intermediate representation, namely TIR, is generated. This TIR is hardware-related, and the API provided by the VTA hardware is embedded in it. The compilation does not directly generate VTA instructions, but controls the VTA runtime system through the VTA API, that is, JIT (Just In Time) compilation. The compiled file is uploaded to the FPGA device through PRC (Remote Procedure Call). At this time, the VTA microkernel is generated, the VTA instructions are expanded, and the entire heterogeneous system is driven to execute the computing task. After the VTA instructions are generated, a running signal is written to the PL (Programmable Logic) of the FPGA device, and the HLS accelerator part of the VTA (PL of the FPGA) starts to execute the computing task in a task-level parallel execution manner, and finally the entire algorithm is deployed on the hardware.

[0094] As Figure 3 shown, the specific mapping implementation method of high-order operators:

[0095] Step S201: Through the analysis of hash-based cryptographic algorithms, the "atomic-level" operators to be mapped are injected into the arithmetic logic unit (ALU) microcode operations through "optimization passes" (through different optimization methods such as unroll, inline, dead code elimination, etc., and through multiple iterations of optimization to improve the code execution efficiency), and the corresponding encoding information is added to the environment variables to prepare for generating high-order operators.

[0096] Step S202: According to the mapped "atomic-level" operators, register the "function-level operator" expressions and the built-in function expressions of the corresponding operator names in the compilation framework. When registering the operator, set the operator attribute to "FLegalize" to indicate to the compiler that this operator is a "function-level operator". When there is no corresponding built-in function for this operator, the compiler can translate the "function-level operator" into a combination of operations of "atomic-level" operators according to the registered built-in function expressions. Built-in functions are implemented by the compiler using dedicated hardware instructions based on different hardware platforms and have high performance. Map all the abstracted "atomic-level" operators to the built-in functions of the same name in the compilation backend.

[0097] Step S203: Add the Python call interface for "function-level operators" to facilitate the call when constructing application-level operators. This interface registers the call name, data type, and operator operation parameters on the Python side of the high-order operator as call nodes in the compilation framework. The call nodes use the language interaction FFI interface (Foreign Function Interface, FFI) in the compilation framework to associate the functions defined in C++ in the compilation framework with Python in the form of Python PackedFunc objects, thus realizing cross-language calls.

[0098] Step S204: Add the operation codes of high-order operators to the hardware environment respectively so that the hardware can recognize them.

[0099] Step S205: Add the conversion rules of high-order operators in the compilation "optimization pass" of the ALU built-in operators in the hardware architecture. According to this rule, the compiler maps the operator name to the corresponding operation code and generates the ALU instructions of the hardware architecture containing the operation code.

[0100] 3. Tensorization for hash-based cryptographic algorithms

[0101] The tensorization of data is the process of converting or mapping low-dimensional data into high-dimensional data. The result obtained through tensorization can be a two-dimensional matrix, a three-dimensional tensor, or a higher-dimensional tensor. The program is decomposed and matched to the underlying hardware tensor calculation unit through an optimizer. Tensorization is more challenging than vectorization. Tensorization involves multi-dimensional data, variable input data lengths, and layouts. Since the input tensor instructions sometimes reuse the same input multiple times, it reduces the required register file bandwidth, improves the computing efficiency, and reduces the hardware execution time. Through tensorization methods, for example, the single-instruction multiple-data (SIMD) implementation with tensorization in one dimension to 16 can improve the computing efficiency by 16 times on the original basis, and the single-instruction multiple-thread (SIMT) implementation with tensorization in two dimensions to 2x16 can improve the computing efficiency by 32 times on the original basis. This patent applies to the extended implementation of such methods.

[0102] To implement the cryptographic algorithm to encrypt multiple messages simultaneously, nx16 messages are input into the initialization input data at the same time.

[0103] Figure 4 Show the situation of tensorized data reuse:

[0104] Figure 4 In it, data0 - data15 represent the input 512-bit messages, which are divided into 16 groups of 32-bit data and stored in memory in row storage mode. The variable i represents the address index, and the range of i is [1, 64]. In step1, when i < 16, the 512-bit messages are accessed in sequential access mode for data access; in step2, when i < 32, the 512-bit messages are accessed in the (5*i + 1) % 16 mode for data access; in step3, when i < 48, the 512-bit messages are accessed in the (3*i + 5) % 16 mode for data access; in step4, when i < 64, the 512-bit messages are accessed in the (7*i) % 16 mode for data access; the input tensor instructions are reused 4 times, reducing the required register file bandwidth, improving the computing efficiency, and reducing the hardware execution time.

[0105] Figure 5Show the single-instruction multiple-data (SIMD) implementation with tensor quantization to 16: The input data is 16 * 16. The rows represent 32-bit * 16 data, and the columns represent 16 input packets. It is a row-addressing mode. For example, the addressing process in step1 is: the first column of the first row, the second column of the first row, that is, the row remains unchanged and the column moves. After the 16th column of the first row is addressed, then the nth column of the second row, and so on... until the two-dimensional matrix data of 16 * 16 is accessed. The single-instruction multiple-data SIMD implementation with tensor quantization to 16 in one dimension improves the computing efficiency by 16 times on the basis of the original computing efficiency.

[0106] Figure 6 Show the single-instruction multiple-thread (SIMT) implementation with tensor quantization to 2 * 16 * 16: The tensor quantization to 2 * 16 in two dimensions with single-instruction multiple-thread improves the efficiency by 32 times on the basis of the original computing efficiency. The memory access method of the calculation is the same as Figure 5 that way. Just one more dimension.

[0107] 4. Register optimization under the VTA architecture

[0108] 1. Take the MD5 algorithm as an example: Reconstruct the MD5 algorithm into a domain-specific language supported by the compilation framework. Before memory optimization, the result of each round of calculation of the MD5 algorithm has to be placed on the CPU. When the next round of operation is to be performed, the calculation result is reloaded to the device for the next round of operation. The MD5 algorithm has 64 rounds of reuse of intermediate results. The calculation result of each round requires interaction between the host side and the device side, which will greatly reduce the computing efficiency, and even the calculation time can be ignored. All the time is basically used for data exchange.

[0109] 2. In order to improve the efficiency of memory access, store the calculations in the "algorithm-level" operators in VTA, which can greatly improve the computing efficiency. For the "algorithm-level" operators in the field of encryption and decryption, the data exchange in each round of loop calculation is placed on VTA. There will be a situation where the same intermediate result needs to be used multiple times. Due to the limitations of the VTA architecture, when the same memory data is used multiple times, it will be found that the memory data will be tampered with, resulting in an incorrect final operation result.

[0110] 3. To solve the problem of memory data being tampered with, each intermediate data needs to be backed up multiple times. The problem of memory data being tampered with can be solved by applying for and backing up the memory buffer, but this manual compilation optimization method will greatly increase the workload of programmers and the cost of later maintenance.

[0111] 4. To solve the problems brought by manual optimization compilation, new compilation optimization rules are added in the "optimization pass" to automate the data backup process, which not only reduces the workload and energy of programmers but also makes the compilation more automated.

[0112] The schematic diagram of the memory optimization effect is as Figure 7 shown.

[0113] As Figure 8 shown, based on the above embodiments, the present invention also proposes a heterogeneous platform compilation optimization system based on high-order cryptographic operators, including:

[0114] An operator extraction module, which is used to design and implement a domain-specific language for describing tensor operations according to the domain-specific language, and perform operator extraction and analysis by analyzing the encryption and decryption algorithms;

[0115] A tensorization module, which is used to reorganize the calculation to efficiently utilize the memory hierarchy and parallel execution hardware through the tensorization and parallelization of data;

[0116] A mapping module, which is used to implement high-order operators through an end-to-end compilation framework and map the high-order operators to heterogeneous hardware;

[0117] A compilation optimization module, which is used to compile and optimize the high-order operators mapped to the hardware to obtain the compiled and optimized high-order operators;

[0118] A compilation module, which is used to compile the hardware executable code according to the compiled and optimized high-order operators.

[0119] Furthermore, the operator extraction module is specifically used for:

[0120] First, perform "atomic-level" operator abstraction, extract function-level operators from "atomic-level" operators through function-level operation rules, and construct application-level high-order operators, that is, coarse-grained operators.

[0121] Furthermore, the mapping module is specifically used for:

[0122] Through the analysis of hash-based cryptographic algorithms, inject the "atomic-level" operators to be mapped into the arithmetic logic unit (ALU) microcode operations through the "optimization pass", and add the corresponding encoding information to the environment variables to prepare for generating high-order operators;

[0123] According to the mapped "atomic-level" operators, register the function-level operator expressions and the built-in function expressions of the corresponding operator names in the compilation framework; when there is no corresponding built-in function for the operator, the compiler translates the function-level operator into an operation combination of "atomic-level" operators according to the registered built-in function expressions; map all the abstracted "atomic-level" operators to the built-in functions with the same name in the compilation backend.

[0124] Add a Python call interface for function-level operators. This interface registers the call name, data type, and operator operation parameters on the Python side of the high-order operator as call nodes in the compilation framework. The call nodes use the language interaction FFI interface in the compilation framework to associate the functions defined in C++ in the compilation framework with Python in the form of Python PackedFunc objects, thus realizing cross-language calls;

[0125] Add the operation codes of high-order operators in the hardware environment respectively so that the hardware can recognize them;

[0126] In the compilation "optimization pass" of injecting built-in operators in the ALU of the hardware architecture, add the conversion rules of high-order operators. According to these rules, the compiler maps the operator names to the corresponding operation codes and generates the ALU instructions of the hardware architecture containing the operation codes.

[0127] Furthermore, the compilation optimization module is specifically used for:

[0128] Place all the storage of calculations in the algorithm-level operators into the VTA for execution;

[0129] Add new compilation rules in the "optimization pass" to automate the data backup process.

[0130] In summary, according to the domain-specific language, the present invention analyzes the algorithms in the encryption and decryption field, extracts and analyzes the core calculation operators; through this compilation framework, it realizes from "atomic-level" operators to "function-level" operators and then to "high-order operators", maps the high-order operators to different hardware through compilation, and performs compilation optimization on the operators mapped to the hardware; according to the optimized high-order operators after compilation, it is converted into machine language that can be recognized by the underlying hardware. The present invention solves the domain-specific language abstraction, memory optimization, compilation mapping of complex operators, and efficiently constructs high-performance algorithms and hardware deployments in the encryption and decryption field.

[0131] Compared with the existing operator compilation abstractions, the present invention solves the problems of higher-order operator abstraction and high-order operator mapping. Compared with traditional compilation optimization methods, the present invention improves the calculation efficiency and reduces the hardware execution time by 32 times on the basis of the original calculation efficiency through the tensorization method. Through the register optimization method, it solves the problem of memory data being overwritten, automates the memory data processing, reduces the workload of programmers, and makes the compilation more automated.

[0132] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A compilation optimization method based on high-order cryptographic operators for heterogeneous platforms, characterized in that, including: Step 1: According to the domain-specific language, through the analysis of encryption and decryption algorithms, design and implement a domain-specific language for describing tensor operations, and perform the extraction and analysis of operators; Step 2: Through the tensorization and parallelization of data, reorganize the calculations to efficiently utilize the memory hierarchy and parallel execution hardware; Step 3: Implement high-order operators through an end-to-end compilation framework and map the high-order operators to heterogeneous hardware; Step 4: Compile and optimize the high-order operators mapped to the hardware to obtain the compiled and optimized high-order operators; Step 5: Compile the hardware-executable code according to the compiled and optimized high-order operators; The said Step 3 includes: Step 3.1: Through the analysis of hash-based cryptographic algorithms, inject the atomic-level operators to be mapped into the arithmetic logic unit (ALU) microcode operations through the "optimization pass", and add the corresponding encoding information to the environment variables to prepare for generating high-order operators; Step 3.2: According to the mapped atomic-level operators, register the function-level operator expressions and the built-in function expressions of the corresponding operator names in the compilation framework; when there is no corresponding built-in function for the operator, the compiler translates the function-level operator into an operation combination of atomic-level operators according to the registered built-in function expressions; map all the abstracted atomic-level operators to the built-in functions with the same name in the compilation backend; Step 3.3: Add a Python call interface for the function-level operators. This interface registers the call name, data type, and operator operation parameters on the Python side of the high-order operators as call nodes in the compilation framework. The call nodes use the language interaction FFI interface in the compilation framework to associate the functions defined in C++ in the compilation framework to Python in the form of Python PackedFunc objects, thus realizing cross-language calls; Step 3.4: Add the operation codes of the high-order operators in the hardware environment respectively so that the hardware can recognize them; Step 3.5: In the compilation "optimization pass" of injecting built-in operators in the ALU of the hardware architecture, add the conversion rules of the high-order operators. According to this rule, the compiler maps the operator names to the corresponding operation codes and generates the ALU instructions of the hardware architecture containing the operation codes.

2. The heterogeneous platform compilation optimization method based on a high-order cryptographic operator according to claim 1, wherein The said Step 1 includes: First, perform the abstraction of atomic-level operators, extract the function-level operators from the atomic-level operators through the function-level operation rules, and construct the application-level high-order operators, that is, the algorithm-level operators.

3. The heterogeneous platform compilation optimization method based on a high-order cryptographic operator according to claim 2, wherein The said Step 4 includes: Place all the calculations and storages in the algorithm-level operators into the VTA for processing; Add new compilation rules in the "optimization pass" to automate the data backup process.

4. A heterogeneous platform compilation optimization system based on high-order cryptographic operators, characterized in that, including: An operator extraction module, which is used to design and implement a domain-specific language for describing tensor operations according to the domain-specific language, through the analysis of encryption and decryption algorithms, and perform the extraction and analysis of operators; A tensorization module, which is used to reorganize the calculations to efficiently utilize the memory hierarchy and parallel execution hardware through the tensorization and parallelization of data; A mapping module, which is used to implement high-order operators through an end-to-end compilation framework and map the high-order operators to heterogeneous hardware; A compilation optimization module, which is used to compile and optimize the high-order operators mapped to the hardware to obtain the compiled and optimized high-order operators; A compilation module, which is used to compile hardware-executable code according to the high-order operators after compilation optimization; The mapping module is specifically used for: By analyzing the hash-based cryptographic algorithm, injecting the atomic-level operators to be mapped into the arithmetic logic unit (ALU) microcode operations through an "optimization pass", and adding corresponding encoding information to the environment variables to prepare for generating high-order operators; According to the mapped atomic-level operators, registering the function-level operator expressions and the built-in function expressions of the corresponding operator names in the compilation framework; when there is no corresponding built-in function for the operator, the compiler translates the function-level operator into an operation combination of atomic-level operators according to the registered built-in function expressions; mapping all the abstracted atomic-level operators to the built-in functions with the same name in the compilation backend; Adding a Python call interface for the function-level operator, and registering the call name, data type, and operator operation parameters on the Python side of the high-order operator as call nodes in the compilation framework. The call nodes use the language interaction Foreign Function Interface (FFI) in the compilation framework to associate the functions defined in C++ in the compilation framework with Python in the form of Python PackedFunc objects, so as to achieve cross-language calls; Adding the operation codes of the high-order operators in the hardware environment respectively, so that the hardware can recognize them; Adding the conversion rules of the high-order operators in the compilation "optimization pass" for injecting the built-in operators of the ALU in the hardware architecture. According to this rule, the compiler maps the operator names to the corresponding operation codes and generates the ALU instructions of the hardware architecture containing the operation codes.

5. The heterogeneous platform compilation optimization system based on a high-order cryptographic operator according to claim 4, characterized in that, The operator extraction module is specifically used for: Firstly, performing atomic-level operator abstraction, extracting the atomic-level operators into function-level operators through function-level operation rules, and constructing application-level high-order operators, that is, algorithm-level operators.

6. The heterogeneous platform compilation optimization system based on a high-order cryptographic operator according to claim 4, wherein, The compilation optimization module is specifically used for: Putting all the computations and storages in the algorithm-level operators into the VTA for processing; Adding new compilation rules in the "optimization pass" to automate the data backup process.

Images