Error correction code standardized verification component and verification method thereof

Abstract

The application discloses an error correction code standardization verification component and a verification method thereof, wherein the error correction code standardization verification component comprises a test object, an error injection module and a result expectation module; the error injection module monitors the behavior of the test object, and when it is monitored that the test object is performing a write operation of RAM, injects an error correction code error into the RAM; the result expectation module, when it is monitored that the test object is performing a read RAM operation, judges whether the read RAM operation request will occur an error correction code error and specific error information according to the error injection information received from the error injection module, obtains an expected value, and when the test object reports error information, compares the reported error information with the expected value to judge the correctness of the error information reporting behavior of the test object; wherein the error injection module and the result expectation module are both designed by using a parameterized class, and are packaged with the test object into an independent error correction code standardization verification component. The error correction code standardization verification component has high reusability and efficient error detection.

Description

Technical Field

[0001] This invention relates to error correcting code (ECC) verification technology, and in particular to a standardized ECC verification component and its verification method. Background Technology

[0002] Error correction coding is a technology that enables "error checking and correction." It is commonly used on servers to improve the stability and reliability of computer operation.

[0003] Currently, there are two major challenges in verifying error-correcting codes (ECC):

[0004] First, RAM (Random Access Memory) comes in various sizes. RAM is internal memory that directly exchanges data with the CPU; it's also called main memory. RAM can be read and written at any time, and its read / write speed is very fast. It is typically used as a temporary data storage medium for the operating system or other running programs. For example... Figure 1 As shown, a CPU typically contains multiple modules: the Instruction Fetch Unit (IFU), the Load and Store Unit (LSU), the Memory Management Unit (MMU), and the L2 cache. The IFU contains the instruction cache (icache), the LSU contains the data cache (dcache), the MMU contains the translation lookaside buffer (tlb), and the L2 cache contains the Level 2 cache. These modules usually utilize RAM, and the size of the RAM varies depending on the hardware configuration. When the CPU executes an instruction, the data flow is as follows: access the IFU's instruction cache -> access the MMU's tlb -> access the LSU's dcache -> access the L2 cache. The instruction cache, dcache, and tlb are all used for caching information and are all composed of RAM. The IFU (Instruction Fetch Unit), LSU (Load and Store Unit), and MMU (Memory Management Unit) are memory management units. Therefore, error correction code (ECC) verification technology needs to be adapted to different sizes of RAM, resulting in poor reusability.

[0005] Secondly, ECC verification involves encoding the data written to RAM by the processor and decoding it when reading data from RAM to check for consistency. Inconsistencies indicate an error in RAM, requiring the specific error information to be reported: which RAM block and its exact location (index, way) where the error occurred. Verifying the correctness of the ECC code necessitates knowing precisely when and where the error occurred in the corresponding RAM. This allows the processor to detect potential errors each time it accesses RAM and ensure the accuracy of reported error messages. However, current technology lacks effective detection methods to verify the correctness of reported error messages.

[0006] In view of the above, it is necessary to propose a standardized verification component and method for error correction codes (ECC) to solve the technical problems of poor reusability and lack of effective detection methods. Summary of the Invention

[0007] The purpose of this invention is to provide a standardized verification component and method for error correction codes, which solves the technical problems of poor reusability and lack of effective detection methods in the prior art.

[0008] To achieve the above objectives, the present invention provides an error-correcting code standardization verification component, comprising:

[0009] Test object;

[0010] The error injection module is used to monitor the behavior of the test object and inject error correction codes into RAM when it detects that the test object is performing a write operation to RAM.

[0011] The result prediction module is communicatively connected to the error injection module. When the result prediction module detects that the test object has performed a RAM read operation, it determines whether the RAM read operation request will result in an error correction code error and the specific error information based on the error injection information received from the error injection module, obtains the expected value, and compares the reported error information with the expected value when the test object reports error information to determine the correctness of the test object's error reporting behavior.

[0012] The error injection module and the result expectation module both adopt parameterized class design and are encapsulated with the test object into an independent error correction code standardized verification component.

[0013] In some embodiments of the present invention, the error correction code standardization verification component includes an error injection module and a result expectation module that both monitor the behavior of the test object through a virtual interface.

[0014] In some embodiments of the present invention, the error correction code standardization verification component includes an error injection module that performs error correction code error injection at the verification granularity and controls the injection probability of 1-bit and 2-bit errors.

[0015] In some embodiments of the present invention, the error correction code standardization verification component supports parameters including: RAM data bit width, RAM index bit width, RAM verification granularity, and RAM path count.

[0016] In some embodiments of the present invention, the error correction code standardization verification component is wherein the independent error correction code standardization verification component adapts to different sizes of RAM by adjusting the parameters.

[0017] On the other hand, the present invention also provides a verification method for a standardized verification component of an error correction code, comprising:

[0018] The error injection step involves the error injection module monitoring the behavior of the test object and injecting error correction codes into the RAM when it detects that the test object is performing a write operation to RAM.

[0019] The expected result steps are as follows: When the expected result module detects that the test object has performed a RAM read operation, it determines whether the RAM read operation request will result in an error correction code error and the specific error information based on the error injection information received from the error injection module, obtains the expected value, and compares the reported error information with the expected value when the test object reports error information to determine the correctness of the test object's error reporting behavior.

[0020] The error injection module and the result expectation module both adopt parameterized class design and are encapsulated with the test object into an independent error correction code standardized verification component.

[0021] In some embodiments of the present invention, the verification method of the error correction code standardization verification component includes an error injection module and a result expectation module that both monitor the behavior of the test object through a virtual interface.

[0022] In some embodiments of the present invention, the verification method of the error correction code standardization verification component further includes, in the error injection step:

[0023] The error injection module injects error correction codes at the verification granularity and controls the injection probability of 1-bit and 2-bit errors.

[0024] In some embodiments of the present invention, the verification method of the error correction code standardization verification component includes the following parameters supported by the independent error correction code standardization verification component: RAM data bit width, RAM index bit width, RAM verification granularity, and RAM path count.

[0025] In some embodiments of the present invention, the verification method of the error correction code standardization verification component is wherein the independent error correction code standardization verification component adapts to different sizes of RAM by adjusting the parameters.

[0026] Furthermore, to achieve the above objectives, the present invention also provides a computer device, comprising:

[0027] At least one processor; and

[0028] A memory for storing computer instructions that can run on the processor, which, when executed by the processor, implement the verification method of the error-correcting code standardization verification component as described above.

[0029] In addition, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed, implements the verification method of the error correction code standardization verification component as described above.

[0030] This invention addresses the verification of error-correcting codes (ECC) by proposing a standardized ECC verification component and method based on UVM (Universal Verification Methodology) and employing parameterized classes. Compared to existing technologies, it offers the following technical advantages:

[0031] 1. Effectively check error reporting status

[0032] In order to obtain the error reporting situation, the present invention determines whether there is an injection error and obtains the expected value each time the RAM memory is accessed. When the DUT reports error information, the reported error information is compared with the expected value to obtain the accurate error reporting situation.

[0033] 2. Good reusability

[0034] This invention employs a parameterized class design, which allows for easy adjustment of parameters to adapt to RAM memories of different sizes. At the same time, the error correction code (ECC) standardization verification component is encapsulated into an independent verification component, which can be instantiated and used in different verification environments, thus exhibiting good reusability. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of an existing CPU internal cache module.

[0036] Figure 2 This is a structural framework diagram of the error correction code standardization verification component of the present invention.

[0037] Figure 3 This is a flowchart of the verification method for the error correction code standardization verification component of the present invention.

[0038] In the attached figures, the following labels are used:

[0039] 200… Error Correction Code ECC Standardized Verification Component

[0040] 201…test object

[0041] 202… Error Injection Module

[0042] 203…Expected Results Module

[0043] S301-S305…Steps Detailed Implementation

[0044] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0045] First, in order to better understand the present invention, the following explanations are provided for some terms or nouns that appear in the description of the embodiments of this application:

[0046] UVM is a verification platform development framework based on the SystemVerilog class library. Verification engineers can leverage its reusable components to build functional verification environments with standardized hierarchical structures and interfaces. This invention, based on UVM, employs a parameterized class design, adaptable to RAM memories of different sizes, thus improving reusability. One RAM instance instantiates one ECC verification component, requiring RAM configuration information to be passed during instantiation. A Vif interface is used to connect the RAM memory and the standardized ECC verification component.

[0047] RAM, or storage device in a computer system, can also be called main memory or RAM. In this invention, it is the subject of a test.

[0048] like Figure 2 The above is a structural framework diagram of the error correction code standardization verification component of the present invention. The error correction code standardization verification component 200 adopts the UVM framework structure, specifically including a test object 201, an error injection module 202, and a result expectation module 203.

[0049] exist Figure 2 In this context, DUT (Device Under Testing) refers to the test object 201. Specifically, in this invention, DUT 201 is RAM.

[0050] Error injection module 202 communicates with DUT 201 via Vif and is used to inject error correction code (ECC) errors into DUT 201.

[0051] Specifically, the error injection module 202 monitors the behavior of the DUT 201 via Vif, and when it detects that the DUT 201 is performing a write operation to RAM, it injects an error correction code (ECC) into RAM and passes the error injection information to the result expectation module 203. The result expectation module 203 receives the error injection information and records it.

[0052] In some embodiments of the present invention, the error injection module 202 performs ECC error injection at the verification granularity and can control the injection probability of 1-bit and 2-bit errors.

[0053] The result prediction module 203 communicates with the DUT 201 via Vif and is used to predict the ECC verification result.

[0054] Specifically, the result prediction module 203 monitors the behavior of the DUT 201 via Vif. When a RAM read operation is detected by the DUT 201, it determines whether the RAM read operation request will result in an ECC error and the specific error information based on the error injection information received and recorded from the error injection module 202. It then obtains the expected value and compares the reported error information with the expected value when the DUT 201 reports error information. This checks the correctness of the DUT 201's error reporting behavior, thereby identifying errors in error reporting and omissions. In some embodiments, when the reported error information matches the expected value, the result prediction module 203 determines that the DUT 201's error reporting behavior is correct; when the reported error information does not match the expected value, the result prediction module 203 determines that the DUT 201's error reporting behavior is incorrect.

[0055] In some embodiments of the present invention, the error injection module 202 and the result expectation module 203 adopt a parameterized class design. Specifically, the parameters supported by the error injection module 202 and the result expectation module 203 may include: the data bit width of RAM, the index bit width of RAM, the verification granularity of RAM, and the number of paths of RAM.

[0056] Furthermore, this invention encapsulates the error injection module 202, the result prediction module 203, and the DUT 201, which employ parameterized class design, to obtain an independent error-correcting code standardization verification component. Therefore, the parameters supported by this independent error-correcting code standardization verification component include: RAM data bit width, RAM index bit width, RAM check granularity, and RAM path count. This independent error-correcting code standardization verification component adapts to RAMs of different sizes by adjusting these parameters.

[0057] Therefore, in conjunction with the above, compared with the prior art, when applying this independent error correction code standardization verification component for verification, the present invention can conveniently integrate the independent error correction code standardization verification component into different verification environments, and only requires configuring the relevant RAM parameters to complete the control of the independent error correction code standardization verification component, realize the injection and checking of error correction code ECC errors, and greatly reduce the verification workload.

[0058] In one embodiment of the present invention, the technical solution can be implemented in different languages, such as OVM, C++, Verilog, etc.

[0059] like Figure 3 The above is a flowchart of the verification method for the error-correcting code standardization verification component of the present invention. Combined with... Figure 2 The specific steps of this verification method include:

[0060] S301, Error injection module 202 monitors the behavior of DUT 201;

[0061] S302, when the error injection module 202 detects that the DUT 201 is performing a write operation in RAM, it injects the error correction code ECC error into RAM and transmits the error injection information to the result expectation module 203 for recording.

[0062] S303, Result Expectation Module 203 monitors the behavior of DUT 201;

[0063] S304, When the result expectation module 203 detects that the DUT 201 has a RAM read operation, it determines whether the RAM read operation request will cause an error correction code (ECC) error and the specific error information based on the error injection information received and recorded from the error injection module 202, and obtains the expected value.

[0064] S305, When the DUT 201 reports an error message, the result expectation module 203 compares the reported error message with the expected value to determine the correctness of the DUT 201's error message reporting behavior;

[0065] In step S305, when the reported error information is consistent with the expected value, the result expectation module 203 determines that the behavior of the DUT 201 in reporting the error information is correct and proceeds to the next step; when the reported error information is inconsistent with the expected value, the result expectation module 203 determines that the behavior of the DUT 201 in reporting the error information is incorrect and returns to step S301.

[0066] S306, End.

[0067] In step S301 above, the error injection module 202 monitors the behavior of the DUT 201 through Vif.

[0068] In step S301 above, preferably, the error injection module 202 performs ECC error injection at the verification granularity and can control the injection probability of 1-bit and 2-bit errors.

[0069] In step S303 above, the result expectation module 203 monitors the behavior of DUT 201 through Vif.

[0070] In the above method flow, preferably, the error injection module 202 and the result expectation module 203 adopt a parameterized class design. Specifically, the parameters supported by the error injection module 202 and the result expectation module 203 may include: the data bit width of RAM, the index bit width of RAM, the verification granularity of RAM, and the number of RAM paths.

[0071] In the above method flow, preferably, the present invention further encapsulates the error injection module 202, the result expectation module 203, and the DUT 201, which employ parameterized class design, to obtain an independent error correction code standardization verification component. The parameters supported by this independent error correction code standardization verification component also include: RAM data bit width, RAM index bit width, RAM verification granularity, and RAM path count. This independent error correction code standardization verification component adapts to RAMs of different sizes by adjusting these parameters.

[0072] In view of the above objectives, another aspect of the present invention provides a computer device comprising: at least one processor; and a memory storing computer instructions executable by the processor to implement the method steps described above.

[0073] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the methods described above.

[0074] It should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The verification method program for the error correction code standardization verification component can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. The storage medium for the program can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0075] The above-described computer program embodiments can achieve the same or similar effects as any of the corresponding aforementioned method embodiments.

[0076] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0077] Furthermore, the above-described method steps and components can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or components.

[0078] Those skilled in the art will also understand that the various exemplary modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0079] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the spirit and essence of this invention.

[0080] The technical solution described in this embodiment proposes a standardized verification component based on UVM and employing parameterized classes for ECC verification. This invention offers at least the following two technical advantages for ECC verification:

[0081] 1. Effectively check error reporting status

[0082] In order to obtain the error reporting status, this invention determines whether there is an injection error and obtains the expected value each time the RAM memory is accessed. When the DUT reports error information, the reported error information is compared with the expected value to obtain the error reporting status.

[0083] 2. Good reusability

[0084] When the size of the RAM memory, the granularity of the verification, or the number of paths changes, the code needs to be manually adjusted for adaptation. Furthermore, because the ECC verification code is not encapsulated as an independent component, it also requires manual modification for adaptation when porting between different verification environments.

[0085] The error correction code standard verification component of this invention adopts a parameterized class design. With simple parameter adjustments, it can adapt to RAM memory of different sizes and provides a comprehensive checking mechanism. Furthermore, it is encapsulated as an independent verification component, making integration very simple and convenient for application in different levels of verification environments, such as module-level, subsystem-level, and system-level, greatly improving the efficiency and quality of error correction code ECC verification.

[0086] Of course, those skilled in the art should understand that the descriptions of any of the above embodiments are merely exemplary and are not intended to imply that the scope of the embodiments of the present invention (including the claims) is limited to these examples. Within the framework of the embodiments of the present invention, technical features of the above embodiments or different embodiments can also be combined, and many other variations of different aspects of the embodiments of the present invention exist, which are not detailed in this invention due to space limitations. Therefore, any omissions, modifications, equivalent substitutions, improvements, and other corresponding changes and modifications made without departing from the spirit and essence of the present invention, that is, within the spirit and principles of the embodiments of the present invention, should be included within the protection scope of the appended claims.

Claims

1. A standardized verification component for error-correcting codes, characterized in that, include: Test object; The error injection module is used to monitor the behavior of the test object and inject error correction code into the RAM when the test object is detected to be performing a write operation in RAM. One error correction code standardization verification component is instantiated for each RAM, and the RAM configuration information is passed in during instantiation. The result prediction module is communicatively connected to the error injection module. When the result prediction module detects that the test object has performed a RAM read operation, it determines whether the RAM read operation request will result in an error correction code error and the specific error information based on the error injection information received from the error injection module, obtains the expected value, and compares the reported error information with the expected value when the test object reports error information to determine the correctness of the test object's error reporting behavior and to identify any errors in the reporting or omission of error information. The error injection module and the result expectation module both adopt parameterized class design and are encapsulated with the test object into an independent error correction code standardized verification component. The parameters supported by the independent error correction code standardized verification component include: RAM data bit width, RAM index bit width, RAM verification granularity, and RAM path count. These parameters are used to adapt to the corresponding RAM.

2. The error correction code standardization verification component according to claim 1, characterized in that, Both the error injection module and the result expectation module monitor the behavior of the test object through a virtual interface.

3. The error-correcting code standardization verification component according to claim 1, characterized in that, The error injection module performs error injection of error correction code at the verification granularity and controls the injection probability of 1-bit and 2-bit errors.

4. The error-correcting code standardization verification component according to claim 1, characterized in that, The independent error-correcting code standardization verification component adapts to different RAM sizes by adjusting the parameters.

5. A verification method for a standardized error-correcting code verification component, characterized in that, include: The error injection step involves the error injection module monitoring the behavior of the test object and injecting error correction codes into the RAM when the test object is detected to be performing a write operation in RAM. One error correction code standardization verification component is instantiated for each RAM, and the RAM configuration information is passed in during instantiation. The expected result steps are as follows: When the expected result module detects that the test object has performed a RAM read operation, it determines whether the RAM read operation request will result in an error correction code error and the specific error information based on the error injection information received from the error injection module, obtains the expected value, and compares the reported error information with the expected value when the test object reports the error information to determine the correctness of the test object's error reporting behavior and to identify any errors in the reporting or omission of the error information. The error injection module and the result expectation module both adopt parameterized class design and are encapsulated with the test object into an independent error correction code standardized verification component. The parameters supported by the independent error correction code standardized verification component include: RAM data bit width, RAM index bit width, RAM verification granularity, and RAM path count. These parameters are used to adapt to the corresponding RAM.

6. The verification method for the error correction code standardization verification component according to claim 5, characterized in that, Both the error injection module and the result expectation module monitor the behavior of the test object through a virtual interface.

7. The verification method for the error correction code standardization verification component according to claim 6, characterized in that, The error injection step also includes: The error injection module performs error injection of error correction code at the verification granularity and controls the injection probability of 1-bit and 2-bit errors.

8. The verification method for the error correction code standardization verification component according to claim 5, characterized in that, The independent error-correcting code standardization verification component adapts to different RAM sizes by adjusting the parameters.

9. A computer device, characterized in that, include: At least one processor; as well as A memory for storing computer instructions that can run on the processor, which, when executed by the processor, implement the verification method of the error-correcting code standardization verification component as described in any one of claims 5-8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed, it implements the verification method of the error correction code standardization verification component as described in any one of claims 5-8.

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