A bus transmission method, apparatus, device and storage medium

Abstract

The application relates to the communication technical field and discloses a bus transmission method, a bus transmission device, a bus transmission equipment and a storage medium, which are applied to a bus matrix based on an advanced extensible interface protocol and include the following steps: receiving read address signals sent by a master device and storing the read address signals in corresponding read address storage spaces; the read address storage spaces are arranged in the bus matrix and have a corresponding relationship with slave devices; sending the read address signals stored in the read address storage spaces to corresponding slave devices; receiving read data returned by the slave devices and storing the read data in corresponding read data storage spaces; the read address storage spaces are arranged in the bus matrix and have a corresponding relationship with the slave devices; and sending the read data stored in the read data storage spaces to the master device. The application can improve the transmission efficiency of data transmission between a single master device and multiple slave devices based on the advanced extensible interface protocol and avoid the occurrence of a device communication deadlock.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a bus transmission method, apparatus, device, and storage medium. Background Technology

[0002] The Advanced eXtensible Interface (AXI) is a point-to-point master-slave interface protocol. When multiple peripherals need to exchange data, a bus matrix (AXI interconnect matrix) is required to provide a switching mechanism connecting master devices to slave devices. Currently, a single bus matrix IP core can support a maximum of 16 master devices and 16 slave devices. If more interfaces are needed, more IP cores can be added. However, in AXI transmission, deadlock often occurs between master and slave devices, leading to communication failures and low data transmission efficiency.

[0003] Therefore, the aforementioned technical problems urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a bus transmission method, apparatus, device, and storage medium that can improve the transmission efficiency of data transmission between a single master device and multiple slave devices based on an advanced extensible interface protocol, and avoid device communication deadlock. The specific solution is as follows:

[0005] The first aspect of this application provides a bus transmission method applied to a bus matrix based on an advanced extensible interface protocol, comprising:

[0006] The system receives each read address signal sent by the master device and stores each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device;

[0007] Each read address signal stored in each read address storage space is sent to the corresponding slave device;

[0008] The system receives each read data returned by the slave device and stores each read data into a corresponding read data storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device.

[0009] Each of the read data stored in the read data storage space is sent to the master device.

[0010] Optionally, sending each of the read address signals stored in each of the read address storage spaces to the corresponding slave device includes:

[0011] According to the first-in-first-out (FIFO) rule, each read address signal stored in the read address storage space is sent to the corresponding slave device; the read address storage space is a first-in-first-out (FIFO) memory.

[0012] Optionally, receiving the read data returned by the slave device includes:

[0013] Determine the transaction number of the read address signal corresponding to the read data;

[0014] Determine whether the master device has sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data;

[0015] If so, determine whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device; if so, determine to receive the read data.

[0016] Optionally, determining whether a read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device includes:

[0017] Determine whether the flag bit corresponding to the read address signal with the same transaction number sent to other slave devices is an invalid flag bit. If it is, determine that a response has been received from the corresponding slave device.

[0018] Optionally, after determining that the read data has been received, the method further includes:

[0019] Modify the flag bit corresponding to the received read data to the invalid flag bit.

[0020] Optionally, sending the read data stored in each of the read data storage spaces to the master device includes:

[0021] The read data storage space is polled and arbitrated.

[0022] If the read data storage space currently being polled and arbitrated is not empty, then each piece of read data stored in the read data storage space is sent to the master device according to the first-in-first-out rule; the read data storage space is a first-in-first-out memory;

[0023] If the read data storage space currently being polled for arbitration is empty, then continue polling for arbitration of the next read data storage space.

[0024] Optionally, after receiving each read address signal sent by the master device, the method further includes:

[0025] If there is no read address storage space corresponding to the read address signal in the bus matrix, the read address signal is stored in the fault-tolerant space, and the master device is responded to according to the preset rules.

[0026] A second aspect of this application provides a bus transmission device applied to a bus matrix based on an advanced extensible interface protocol, comprising:

[0027] The first receiving and storage module is used to receive each read address signal sent by the master device and store each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device;

[0028] The first transmitting module is used to transmit each of the read address signals stored in each of the read address storage spaces to the corresponding slave device;

[0029] The second receiving and storage module is used to receive each read data returned by the slave device and store each read data into a corresponding read data storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device;

[0030] The second sending module is used to send the read data stored in each of the read data storage spaces to the main device.

[0031] A third aspect of this application provides an electronic device including a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the aforementioned bus transmission method.

[0032] A fourth aspect of this application provides a computer-readable storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the aforementioned bus transmission method.

[0033] In this application, a bus matrix based on the Advanced Extensible Interface Protocol (AEP) first receives read address signals sent by the master device and stores each read address signal in a corresponding read address storage space. The read address storage spaces are configured within the bus matrix and correspond to the slave devices. Then, the read address signals stored in each read address storage space are sent to the corresponding slave device. Next, read data returned by the slave device is received, and each read data is stored in a corresponding read data storage space. The read address storage spaces are configured within the bus matrix and correspond to the slave devices. Finally, the read data stored in each read data storage space is sent to the master device. Therefore, this application improves the transmission efficiency of data transfer between the master and slave devices based on the AEP by setting read address storage spaces and read data storage spaces in the bus matrix, utilizing these two storage spaces for data flow between a single master device and multiple slave devices, thus avoiding device communication deadlock. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 A flowchart of a bus transmission method provided in an embodiment of this application;

[0036] Figure 2 A specific bus transmission architecture example diagram is provided for embodiments of this application;

[0037] Figure 3 A flowchart illustrating a specific bus transmission method provided in this application embodiment;

[0038] Figure 4 A flowchart illustrating a specific bus transmission method provided in this application embodiment;

[0039] Figure 5 This is a schematic diagram of a bus transmission device structure provided in an embodiment of this application;

[0040] Figure 6 This is a structural diagram of a bus transmission electronic device provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0042] Currently, deadlocks often occur between master and slave devices in AXI transmission, leading to communication failures and low data transmission efficiency. To address these technical shortcomings, this paper proposes a bus transmission scheme. By setting up read address storage space and read data storage space in the bus matrix, data flow is performed between a single master device and multiple slave devices via the bus, improving the transmission efficiency of data transmission between master and slave devices based on the Advanced Extensible Interface Protocol (AAPI) and avoiding device communication deadlocks.

[0043] Figure 1 A flowchart illustrating a bus transmission method provided in an embodiment of this application. See also... Figure 1 As shown, this bus transmission method is applied to a bus matrix based on an advanced extensible interface protocol, including:

[0044] S11: Receive each read address signal sent by the master device and store each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device.

[0045] In this embodiment, the bus matrix is ​​actually an AXI bus interconnect module, similar to the switching matrix in a switch. A System-on-a-Chip (SoC) contains processors (sometimes more than one), memory, and numerous various devices. To enable them to operate at high speed and efficiency, a high-performance on-chip bus is required. A high-performance on-chip bus allows the SoC to have a smaller area, lower power consumption, and higher performance. However, the on-chip bus of an SoC is still under development and is not as mature as a microcomputer bus. Currently, there is no unified standard. AMBA (Advanced Microcontroller Bus Architecture) is a commonly used SoC bus standard. The purpose of the AMBA protocol is to introduce the specification of the on-chip bus. AMBA 3.0 introduced the AXI bus, a high-performance, high-bandwidth, low-latency on-chip bus. Its address / control and data phases are separated, supporting unaligned data transmission. In burst transmissions, only the starting address is needed. Simultaneously, the separate read / write data channels and the support for significant and out-of-order access make AXI a new high-performance protocol within AMBA. AXI technology enriches the existing AMBA standard, meeting the needs of ultra-high performance and complex SOC designs. The AXI bus adopts a read-write separation and address / control / data separation transmission mechanism. By defining five independent transmission channels—Read Address Channel (AR), Read Data Channel (R), Write Address Channel (AW), Write Data Channel (W), and Write Response Channel (B)—it significantly improves transmission efficiency. In SOCs based on the AXI bus protocol, the master and slave devices often exchange data through the bus matrix. This bus matrix is ​​compatible with the Outstanding Transfer Access and Out-of-Order (OoO) access mechanisms supported by the AXI protocol. While this improves transmission throughput, it also increases the risk of bus deadlock.

[0046] Based on this, this embodiment sets up a read address storage space in the bus matrix. The read address storage space corresponds to a slave device; that is, one slave device corresponds to one read address storage space. Each slave device corresponds to a set of storage spaces, namely a read address storage space and a read data storage space. The transmission architecture is as follows: Figure 2As shown. The AXI protocol provides a single interface definition to describe interfaces: between a master device and a bus matrix, between a slave device and a bus matrix, and between a master device and a slave device. This interface definition facilitates the expression of various interconnections. Interconnections between devices, like other devices with symmetrical master and slave ports, can connect true master and slave devices. Most systems employ one of three interconnection methods: shared address and data buses, shared address bus and multiple data buses, or multi-layer interconnection with multiple address and data buses.

[0047] In this embodiment, the bus matrix receives read address signals sent by the master device and stores each read address signal in the corresponding read address storage space. The read address signal is a read request sent by the master device through the PCIe interface. The slave device uses the AXI standard bus interface, which can be a VGA interface, H2B interface, or MCTP interface, etc. When receiving a read address signal, the bus matrix sends it to the read address storage space corresponding to the slave device. PCIe can send read address signals continuously. It should be noted that this embodiment only applies to AXI read operations. Because the AXI4 protocol has removed WID, write operations can only be executed sequentially and no longer support out-of-order execution, thus eliminating the deadlock problem.

[0048] Furthermore, if the bus matrix does not contain a read address storage space corresponding to the read address signal, the read address signal is stored in the fault tolerance space, and the master device is responded to according to preset rules. That is, in addition to the read address storage space and the read data storage space, the bus matrix also includes a fault tolerance space. This fault tolerance space is used to handle read operation errors, i.e., if each slave device does not match the read request sent by the master device's PCIe interface, the signal will be sent to the fault tolerance space. The fault tolerance space can be a first-in-first-out (FIFO) memory with a depth of 8 and a width equal to the signal bit width of each data channel. The fault tolerance space stores the id, user, etc., of the read address signal that cannot match the slave device, with last set to 1, resp set to 2'b11 (the response to be returned in error cases), and data set to all 1s. This is the process of responding to the master device according to preset rules.

[0049] S12: Send each of the read address signals stored in the read address storage space to the corresponding slave device.

[0050] In this embodiment, each read address signal stored in each read address storage space is sent to the corresponding slave device. The read address storage space is a first-in-first-out (FIFO) memory, denoted as Addr FIFO. After the read address signal is written into Addr FIFO, it can be sent to the corresponding slave device as long as Addr FIFO is not empty. Specifically, the read address signals stored in each read address storage space are sent to the corresponding slave device according to the FIFO rule. The depth of Addr FIFO is 8, and its width is the sum of the bit widths of all signals in the address channel.

[0051] S13: Receive each read data returned by the slave device and store each read data into the corresponding read data storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device.

[0052] In this embodiment, while sending the Addr FIFO to the slave device, the bus matrix can receive returned read data at any time. That is, it receives each read data returned by the slave device and stores each read data into a corresponding read data storage space. As mentioned above, the bus matrix is ​​equipped with such a read data storage space, which is also a first-in-first-out (FIFO) memory, represented as a Data FIFO. The process of receiving read data from the slave device specifically includes (e.g.) Figure 3 As shown):

[0053] S131: Determine the transaction number of the read address signal corresponding to the read data.

[0054] In this embodiment, when receiving read data from the slave device, the bus matrix first determines the transaction number of the read address signal corresponding to the read data. In AXI transmission, the master device uses an ID number to mark each transmission (i.e., each transaction). This ID number is the transaction number. The same master device sends different transmissions to different slave devices using the same ID number. Different transmissions must be performed in sequence, but the slave device can return transmissions with different ID numbers in an out-of-order manner. This process can lead to deadlock. For a multi-master to multi-slave transmission architecture, this can be avoided by using a mechanism where only a single slave device or the same ID can only be used by a single slave device. That is, a master device cannot send the same ID to different slave devices unless the previous ID has already been processed. However, this is not suitable for a transmission architecture with a single master device and multiple slave devices. For example, if the master device sends the same ID to two slave devices in the order of slave device 1 first and then slave device 2, even if slave device 2 processes it faster, it cannot return because it needs to return according to the master device's sending order. If slave device 1 does not return, it will greatly affect the communication with slave device 2. Therefore, the above processing method is only suitable for multiple master devices to multiple slave devices. If a master device is connected to multiple slave devices, using this method will reduce efficiency.

[0055] S132: Determine whether the master device has sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data.

[0056] S133: If yes, determine whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device; if yes, determine that the read data is received.

[0057] In this embodiment, after determining the transaction number of the read address signal corresponding to the read data, it is first determined whether the master device has sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data. If so, it is further determined whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device. If so, it is determined to receive the read data.

[0058] In this embodiment, the flag bit of the signal can be used to determine whether the master device has sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data. Specifically, it is determined whether the flag bit corresponding to the read address signal with the same transaction number sent to other slave devices is an invalid flag bit. If so, it is determined that a response has been received from the corresponding slave device. The flag bit of the read address signal is custom-added and can be modified according to actual conditions. When the bus matrix receives the read address signal, this flag bit is set to a valid flag bit, and it can be modified to an invalid flag bit after transmission is completed, that is, the flag bit corresponding to the received read data is modified to an invalid flag bit.

[0059] Therefore, the above process mainly achieves sequential execution of the same ID by controlling the return data from the slave devices. Each signal sent by PCIe needs to be stored with a flag bit added. This flag bit indicates that the transmission is valid, and it is invalidated after the transmission is completed. In this embodiment, if the master device has not sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data, then it determines to receive the read data. If the read address signal with the same transaction number sent to other slave devices has not yet received a response from the corresponding slave device, then the reception of the read data is paused. Before each data return from the slave device to the Data FIFO, it is compared whether the ID of the data has been sent before, whether it is valid, and whether it is to a different slave device. If so, it means that the master device has not yet finished processing this ID to a different slave device. Because data needs to be returned sequentially, the transmission of this ID will be paused first, but it will not hinder PCIe from sending transactions for other IDs. This processing method does not hinder transactions for other IDs and does not cause blocking, thus greatly improving transmission efficiency. Of course, if the comparison does not meet the requirements, the data of this ID will continue to be transmitted without affecting any transmission. When a transmission ends, the flag bit and the data at the location of that transmission will be cleared.

[0060] S14: Send the read data stored in each of the read data storage spaces to the master device.

[0061] In this embodiment, the read data stored in each of the read data storage spaces is sent to the master device, that is, the read data in the Data FIFO is sent to the PCIe, specifically including the following steps (e.g. Figure 4 As shown):

[0062] S141: Perform polling arbitration on each of the read data storage spaces.

[0063] S142: If the read data storage space of the current polling arbitration is not empty, then each read data stored in the read data storage space is sent to the master device according to the first-in-first-out rule; the read data storage space is a first-in-first-out memory.

[0064] S143: If the read data storage space currently being polled and arbitrated is empty, then continue polling and arbitrating the next read data storage space.

[0065] In this embodiment, when returning read data to the master device, the process primarily involves polling and arbitrating each read data storage space. If the currently polled read data storage space is not empty, the read data stored in that space is sent to the master device according to a first-in-first-out (FIFO) rule. The read data storage space is a FIFO memory. If the currently polled read data storage space is empty, the process continues polling and arbitrating the next read data storage space. In other words, this embodiment, used for PCIe read operations, arbitrates the data read into the Data FIFO, reading data from each Data FIFO and sending it to the PCIe. The arbitration method used here is polling and arbitrating: first, the Data FIFOs are checked sequentially; as long as one is not empty, data in that Data FIFO is sent until it is empty, then the next Data FIFO is checked, and so on, polling sequentially.

[0066] It should be noted that the Data FIFO used here to store information about the data channels read from the device has a maximum of 256 per burst, and the current depth is 256. If necessary, the parameters will be changed later. The depth of the Addr FIFO mentioned earlier is also temporary, and the parameters can be changed later.

[0067] As can be seen, in this embodiment of the application, during bus transmission, the bus matrix based on the Advanced Extensible Interface Protocol (AEP) first receives each read address signal sent by the master device and stores each read address signal in a corresponding read address storage space. The read address storage space is located in the bus matrix and corresponds to a slave device. Then, the read address signals stored in each read address storage space are sent to the corresponding slave device. Next, the read data returned by the slave device is received, and each read data is stored in a corresponding read data storage space. The read address storage space is located in the bus matrix and corresponds to a slave device. Finally, the read data stored in each read data storage space is sent to the master device. This embodiment of the application, by setting read address storage space and read data storage space in the bus matrix, utilizes these two storage spaces to perform data flow in bus transmission between a single master device and multiple slave devices, improving the transmission efficiency of data transmission between the master device and slave devices based on the AEP and avoiding device communication deadlock.

[0068] See Figure 5 As shown in the figure, this application also discloses a bus transmission device applied to a bus matrix based on an advanced extensible interface protocol, including:

[0069] The first receiving and storage module 11 is used to receive each read address signal sent by the master device and store each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device;

[0070] The first transmitting module 12 is used to transmit each of the read address signals stored in each of the read address storage spaces to the corresponding slave device;

[0071] The second receiving and storage module 13 is used to receive each read data returned by the slave device and store each read data into a corresponding read data storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device;

[0072] The second sending module 14 is used to send the read data stored in each of the read data storage spaces to the main device.

[0073] As can be seen, in this embodiment of the application, during bus transmission, the bus matrix based on the Advanced Extensible Interface Protocol (AEP) first receives each read address signal sent by the master device and stores each read address signal in a corresponding read address storage space. The read address storage space is located in the bus matrix and corresponds to a slave device. Then, the read address signals stored in each read address storage space are sent to the corresponding slave device. Next, the read data returned by the slave device is received, and each read data is stored in a corresponding read data storage space. The read address storage space is located in the bus matrix and corresponds to a slave device. Finally, the read data stored in each read data storage space is sent to the master device. This embodiment of the application, by setting read address storage space and read data storage space in the bus matrix, utilizes these two storage spaces to perform data flow in bus transmission between a single master device and multiple slave devices, improving the transmission efficiency of data transmission between the master device and slave devices based on the AEP and avoiding device communication deadlock.

[0074] In some specific embodiments, the first sending module 12 is specifically used to send each of the read address signals stored in each of the read address storage spaces to the corresponding slave devices according to the first-in-first-out rule; the read address storage space is a first-in-first-out memory.

[0075] In some specific embodiments, the second receiving and storage module 13 specifically includes:

[0076] The numbering determination unit is used to determine the transaction number of the read address signal corresponding to the read data;

[0077] The first judgment unit is used to determine whether the master device has sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data;

[0078] The second determination unit is used to determine, if yes, whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device; if yes, it determines that the read data is received.

[0079] In some specific embodiments, the second determining unit is specifically used to determine whether the flag bit corresponding to the read address signal with the same transaction number sent to other slave devices is an invalid flag bit; if so, it is determined that a response has been obtained from the corresponding slave device.

[0080] In some specific embodiments, the bus transmission device further includes:

[0081] The modification module is used to modify the flag bit corresponding to the received read data to an invalid flag bit;

[0082] The fault-tolerant module is used to store the read address signal in the fault-tolerant space if there is no read address storage space corresponding to the read address signal in the bus matrix, and respond to the master device according to the preset rules.

[0083] In some specific embodiments, the second sending module 14 specifically includes:

[0084] The polling unit is used to poll and arbitrate each of the read data storage spaces.

[0085] The sending unit is configured to send each piece of read data stored in the read data storage space to the master device according to the first-in-first-out rule if the read data storage space currently being polled and arbitrated is not empty; the read data storage space is a first-in-first-out memory.

[0086] The continued polling unit is used to continue polling the next read data storage space if the currently polled arbitration space is empty.

[0087] Furthermore, embodiments of this application also provide an electronic device. Figure 6 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0088] Figure 6 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21, and at least performs the following steps:

[0089] The system receives each read address signal sent by the master device and stores each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device;

[0090] Each read address signal stored in each read address storage space is sent to the corresponding slave device;

[0091] The system receives each read data returned by the slave device and stores each read data into a corresponding read data storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device.

[0092] Each of the read data stored in the read data storage space is sent to the master device.

[0093] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0094] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222 and data 223, etc., and the storage method can be temporary storage or permanent storage.

[0095] The operating system 221 manages and controls the various hardware devices on the electronic device 20 and the computer program 222 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows Server, Netware, Unix, Linux, etc. In addition to including computer programs capable of performing the bus transmission method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks. The data 223 may include signal data collected by the electronic device 20.

[0096] Furthermore, embodiments of this application also disclose a storage medium storing a computer program, which, when loaded and executed by a processor, performs at least the following steps:

[0097] The system receives each read address signal sent by the master device and stores each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device;

[0098] Each read address signal stored in each read address storage space is sent to the corresponding slave device;

[0099] The system receives each read data returned by the slave device and stores each read data into a corresponding read data storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device.

[0100] Each of the read data stored in the read data storage space is sent to the master device.

[0101] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0102] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0103] The bus transmission method, apparatus, device, and storage medium provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A bus transmission method, characterized in that, Applications to bus matrices based on advanced extensible interface protocols include: The system receives each read address signal sent by the master device and stores each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device; Each read address signal stored in each read address storage space is sent to the corresponding slave device; The system receives each read data returned by the slave device and stores each read data into a corresponding read data storage space; the read data storage space is set in the bus matrix and has a corresponding relationship with the slave device. Send the read data stored in each of the read data storage spaces to the main device; The step of receiving each read data returned by the slave device includes: determining the transaction number of the read address signal corresponding to the read data; determining whether the master device has sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data; if so, determining whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device; if so, determining to receive the read data. The step of determining whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device includes: determining whether the flag bit corresponding to the read address signal with the same transaction number sent to other slave devices is an invalid flag bit; if so, it is determined that a response from the corresponding slave device has been received.

2. The bus transmission method according to claim 1, characterized in that, The step of sending each of the read address signals stored in each of the read address storage spaces to the corresponding slave device includes: According to the first-in-first-out (FIFO) rule, each read address signal stored in the read address storage space is sent to the corresponding slave device; the read address storage space is a first-in-first-out (FIFO) memory.

3. The bus transmission method according to claim 1, characterized in that, After determining that the read data has been received, the process further includes: Modify the flag bit corresponding to the received read data to the invalid flag bit.

4. The bus transmission method according to claim 1, characterized in that, The step of sending the read data stored in each of the read data storage spaces to the main device includes: The read data storage space is polled and arbitrated. If the read data storage space currently being polled and arbitrated is not empty, then each piece of read data stored in the read data storage space is sent to the master device according to the first-in-first-out rule; the read data storage space is a first-in-first-out memory; If the read data storage space currently being polled for arbitration is empty, then continue polling for arbitration of the next read data storage space.

5. The bus transmission method according to any one of claims 1 to 4, characterized in that, After receiving each read address signal sent by the master device, the method further includes: If there is no read address storage space corresponding to the read address signal in the bus matrix, the read address signal is stored in the fault-tolerant space, and the master device is responded to according to the preset rules.

6. A bus transmission device, characterized in that, Applications to bus matrices based on advanced extensible interface protocols include: The first receiving and storage module is used to receive each read address signal sent by the master device and store each read address signal into the corresponding read address storage space; the read address storage space is set in the bus matrix and has a corresponding relationship with the slave device; The first transmitting module is used to transmit each of the read address signals stored in each of the read address storage spaces to the corresponding slave device; The second receiving and storage module is used to receive each read data returned by the slave device and store each read data into a corresponding read data storage space; the read data storage space is set in the bus matrix and has a corresponding relationship with the slave device; The second sending module is used to send the read data stored in each of the read data storage spaces to the main device; The step of receiving each read data returned by the slave device includes: determining the transaction number of the read address signal corresponding to the read data; determining whether the master device has sent a read address signal with the same transaction number to other slave devices before sending the read address signal corresponding to the read data; if so, determining whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device; if so, determining to receive the read data. The step of determining whether the read address signal with the same transaction number sent to other slave devices has received a response from the corresponding slave device includes: determining whether the flag bit corresponding to the read address signal with the same transaction number sent to other slave devices is an invalid flag bit; if so, it is determined that a response from the corresponding slave device has been received.

7. An electronic device, characterized in that, The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the bus transmission method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, Used to store computer-executable instructions, which, when loaded and executed by a processor, implement the bus transmission method as described in any one of claims 1 to 5.

Images