Driving method of display panel and display device

Abstract

The display panel driving method and the display device provided by the embodiments of the present disclosure can switch between different display modes according to the actual application scenario of the display panel. Moreover, when switching between different display modes, the display panel does not display a normal picture, but displays a preset setting picture. When the display panel displays the setting picture, the switching action between different display modes is performed. In this way, the display frame of the normal display picture is not occupied additionally, and the display abnormality of the normal picture can be avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a driving method of a display panel and a display device. BACKGROUND

[0002] In a display panel such as a liquid crystal display (LCD) panel and an organic light-emitting diode (OLED) display panel, a plurality of pixel units are generally included. Each pixel unit can include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. By controlling the brightness of each sub-pixel, a color image is displayed by mixing the required display color. SUMMARY

[0003] The driving method of the display panel provided by the embodiments of the present disclosure comprises:

[0004] When it is determined that the current display frame is switched to a different display mode, display data corresponding to a preset setting picture is obtained.

[0005] When the display panel is driven to display the setting picture in the current display frame according to the display data corresponding to the setting picture, the current display mode is switched to a target display mode.

[0006] In some examples, when the current display mode is switched to the target display mode, the display data to be displayed in the current display frame is also obtained.

[0007] After the display panel is driven to display the setting picture in the current display frame according to the display data corresponding to the setting picture, and the current display mode is switched to the target display mode, the display panel is driven to display a corresponding picture in the next display frame according to the display data to be displayed based on the target display mode.

[0008] In some examples, the display panel comprises a first display mode; wherein the first display mode comprises: in each display frame, driving gate lines row by row, and when the driving of the previous row of gate lines is completed and the driving of the next row of gate lines is in progress, inputting a data voltage corresponding to the display data into a data line connected to a sub-pixel in the next row of gate lines.

[0009] In some examples, the display panel comprises a second display mode; wherein the second display mode comprises: in each display frame, simultaneously driving the gate lines in at least two adjacent gate line groups, and driving the gate line groups one by one, when the gate lines in the previous gate line group are driven and the gate lines in the next gate line group are being driven, inputting the data voltage corresponding to the display data into the data line corresponding to the sub-pixels connected to the gate lines in the next gate line group.

[0010] In some examples, the display panel comprises a third display mode; wherein the third display mode comprises: in a first display frame of two adjacent display frames, driving the gate lines in the display panel row by row, and when the gate lines connected to the sub-pixels in the previous odd-numbered row are driven and the gate lines connected to the sub-pixels in the next odd-numbered row are being driven, inputting the data voltage corresponding to the display data into the data line corresponding to the next odd-numbered row of sub-pixels; and in a second display frame of two adjacent display frames, driving the gate lines in the display panel row by row, and when the gate lines connected to the sub-pixels in the previous even-numbered row are driven and the gate lines connected to the sub-pixels in the next even-numbered row are being driven, inputting the data voltage corresponding to the display data into the data line corresponding to the next even-numbered row of sub-pixels.

[0011] In some examples, the current display mode is one of the first display mode, the second display mode, and the third display mode.

[0012] The target display mode is one of the first display mode, the second display mode, and the third display mode, except the current display mode.

[0013] In some examples, the display panel comprises sub-pixels of multiple different colors.

[0014] The setting picture comprises a solid color picture.

[0015] Or the setting picture comprises a picture in which the sub-pixels of various colors are all the same gray scale value.

[0016] The display device provided by the embodiments of the present disclosure comprises:

[0017] The display panel comprises a source driving circuit.

[0018] The timing controller is configured to: when it is determined that the current display frame is switched to a different display mode, acquire and output the display data corresponding to the setting picture stored in advance; and when the display panel displays the setting picture in the current display frame according to the display data corresponding to the setting picture, switch the current display mode to a target display mode.

[0019] The source driving circuit is configured to receive display data corresponding to the setting picture, and drive the display panel to display the setting picture in the current display frame according to the display data corresponding to the setting picture.

[0020] In some examples, further comprising:

[0021] The system chip is configured to output a mode switching instruction when it is determined that the current display frame is switched to a different display mode.

[0022] The timing controller is further configured to obtain display data corresponding to a setting picture when the mode switching instruction is received.

[0023] In some examples, the system chip is further configured to output display data to be displayed in the current display frame in the current display frame.

[0024] The timing controller is further configured to obtain display data to be displayed in the current display frame, and drive the display panel to display a corresponding picture in the next display frame according to the display data to be displayed based on the target display mode.

[0025] In some examples, further comprising:

[0026] A connector, a first end of the connector being connected with the system chip, and a second end of the connector being connected with the timing controller; wherein the first end of the connector comprises a first IIC pin and a first switching instruction transmission pin; and the second end of the connector comprises a second IIC pin and a second switching instruction transmission pin.

[0027] The system chip is further configured to output the mode switching instruction through the first switching instruction transmission pin, and output a handshake signal through the first IIC pin.

[0028] The timing controller is further configured to receive the mode switching instruction through the second switching instruction transmission pin, and receive the handshake signal through the second IIC pin, and perform handshake with the system chip after receiving the handshake signal.

[0029] In some examples, the first end and the second end of the connector are 51-pin interfaces respectively.

[0030] In some examples, the first IIC pin comprises a first SDA pin and a first SCL pin.

[0031] The second IIC pin comprises a second SDA pin and a second SCL pin.

[0032] In some examples, the first end of the connector further comprises a first data transmission pin; and the second end of the connector further comprises a second data transmission pin.

[0033] The system on chip is further configured to output, through the first data transmission pin, display data of the current display frame to be displayed.

[0034] The timing controller is further configured to receive, through the second data transmission pin, display data of the current display frame to be displayed.

[0035] In some examples, the first data transmission pin comprises a first VBYONE pin; and the second data transmission pin comprises a second VBYONE pin.

[0036] The driving method and the display device provided by the embodiments of the present disclosure can switch between different display modes according to the actual application scenario of the display panel. When switching between different display modes, a normal picture is not displayed, but a preset setting picture is displayed. When driving the display panel to display the setting picture, a switching action of different display modes is performed. In this way, the display frame of the normal display picture is not occupied, and display abnormalities of the normal picture can be avoided.

[0037] In addition, the driving method and the display device provided by the embodiments of the present disclosure can switch between different display modes according to the actual application scenario of the display panel. For example, a game display picture needs a high refresh frequency. However, the high refresh frequency compresses the charging time of the sub-pixel of the display panel, resulting in insufficient charging of the sub-pixel. In the embodiments of the present disclosure, when switching from a display mode with a low refresh frequency to a display mode with a high refresh frequency, the high refresh frequency can be realized while improving the charging rate of the sub-pixel. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 FIG. 1 is a structural schematic diagram of a display device in the embodiments of the present disclosure;

[0039] Figure 2 FIG. 2 is a structural schematic diagram of a display panel in the embodiments of the present disclosure;

[0040] Figure 3 FIG. 3 is another structural schematic diagram of a display panel in the embodiments of the present disclosure;

[0041] Figure 4 FIG. 4 is a signal schematic diagram in the embodiments of the present disclosure;

[0042] Figure 5 FIG. 5 is another signal schematic diagram in the embodiments of the present disclosure;

[0043] Figure 6 Fig. 6 is another signal schematic diagram in embodiments of the present disclosure;

[0044] Figure 7 Fig. 7 is a flow chart of a driving method in embodiments of the present disclosure;

[0045] Figure 8 Fig. 8 is a structural schematic diagram of a system on chip and a timing controller in embodiments of the present disclosure;

[0046] Figure 9 Fig. 9 is a 51pin interface schematic diagram in embodiments of the present disclosure;

[0047] Figure 10 Fig. 10 is a structural schematic diagram of a timing controller in embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the general meaning understood by those of ordinary skill in the art to which the present disclosure belongs. The “first”, “second” and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. “Include” or “contain” and similar words mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects. “Connect” or “connected” and similar words are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect.

[0050] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportion, but only illustrate the content of the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0051] Reference Figure 1 With Figure 2The display device can include a display panel 100 and a timing controller 200. The display panel 100 can include a plurality of pixel units arranged in an array, a plurality of gate lines GA (for example, GA1, GA2, GA3, and GA4), a plurality of data lines DA (for example, DA1, DA2, and DA3), a gate drive circuit 110, and a source drive circuit 120. The gate drive circuit 110 is coupled to the gate lines GA1, GA2, GA3, and GA4, respectively, and the source drive circuit 120 is coupled to the data lines DA1, DA2, and DA3, respectively. The timing controller 200 can input a control signal to the gate drive circuit 110 through a level shift circuit, so as to drive the gate lines GA1, GA2, GA3, and GA4. The timing controller 200 inputs a signal to the source drive circuit 120, so as to enable the source drive circuit 120 to input a data voltage to the data lines, charge the sub-pixels SPX, and enable the sub-pixels SPX to input a corresponding data voltage, thereby realizing a picture display function. For example, the source drive circuit 120 can be provided in two, one of which is connected to half of the data lines, and the other of which is connected to the other half of the data lines. Of course, the source drive circuit 120 can also be provided in three, four, or more, which can be designed and determined according to actual application requirements, and is not limited herein.

[0052] For example, each pixel unit includes a plurality of sub-pixels SPX. For example, the pixel unit can include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to realize color display. Alternatively, the pixel unit can include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to realize color display. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and are not limited herein.

[0053] Referring to FIG. 1, Figure 2 As shown in FIG. 1, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02. One row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data line. The gate of the transistor 01 is electrically connected to the corresponding gate line, the source of the transistor 01 is electrically connected to the corresponding data line, and the drain of the transistor 01 is electrically connected to the pixel electrode 02. It should be noted that the pixel array structure of the present disclosure can also be a double-gate structure, that is, two gate lines are arranged between adjacent two rows of pixels. This arrangement can reduce half of the data lines, that is, some data lines are included between adjacent two columns of pixels, and some data lines are not included between adjacent two columns of pixels. The arrangement of the pixel arrangement structure and the data line and the scan line is not limited.

[0054] It should be noted that the display panel in the embodiments of the present disclosure can be a liquid crystal display panel, an OLED display panel, etc., which is not limited herein.

[0055] Currently, different display application scenarios require different display effects. For example, in a static picture, the power consumption is required to be reduced without pursuing a high refresh rate. In a game mode, a higher refresh rate is pursued for smoother display. However, the display mode of the display panel is generally fixed and single, which leads to poor user experience effect.

[0056] The following is described by taking a pixel unit including a red sub-pixel, a green sub-pixel and a blue sub-pixel as an example. As shown in Figure 3 a red sub-pixel R11, a green sub-pixel G11 and a blue sub-pixel B11 form a pixel unit, a red sub-pixel R12, a green sub-pixel G12 and a blue sub-pixel B12 form a pixel unit. A red sub-pixel R21, a green sub-pixel G21 and a blue sub-pixel B21 form a pixel unit, a red sub-pixel R22, a green sub-pixel G22 and a blue sub-pixel B22 form a pixel unit. A red sub-pixel R31, a green sub-pixel G31 and a blue sub-pixel B31 form a pixel unit, a red sub-pixel R32, a green sub-pixel G32 and a blue sub-pixel B32 form a pixel unit. A red sub-pixel R41, a green sub-pixel G41 and a blue sub-pixel B41 form a pixel unit, a red sub-pixel R42, a green sub-pixel G42 and a blue sub-pixel B42 form a pixel unit. A red sub-pixel R51, a green sub-pixel G51 and a blue sub-pixel B51 form a pixel unit, a red sub-pixel R52, a green sub-pixel G52 and a blue sub-pixel B52 form a pixel unit. A red sub-pixel R61, a green sub-pixel G61 and a blue sub-pixel B61 form a pixel unit, a red sub-pixel R62, a green sub-pixel G62 and a blue sub-pixel B62 form a pixel unit.

[0057] The display panel in the embodiments of the present disclosure can include a plurality of different display modes. And switching can be performed between any two display modes. Exemplarily, one of the plurality of display modes can be a first display mode. In the first display mode, in each display frame, the gate lines are driven row by row, and when the driving of the previous row of gate lines is completed and the driving of the next row of gate lines is in progress, the data voltage corresponding to the display data is input to the data line connected to the sub-pixel corresponding to the next row of gate lines. Exemplarily, the gate-on signals on the adjacent two gate lines have an overlapping time length.

[0058] For example, in combination with Figure 3 and Figure 4As shown, the working process of the display panel driven in the first display mode is described. Wherein, ga1 represents the signal loaded on the gate line GA1, ga2 represents the signal loaded on the gate line GA2, ga3 represents the signal loaded on the gate line GA3, ga4 represents the signal loaded on the gate line GA4, ga5 represents the signal loaded on the gate line GA5, and ga6 represents the signal loaded on the gate line GA6. Vda1 represents the data voltage loaded on the data line DA1. And the high level of the signals ga1-ga6 can be used as the gate opening signal to control the transistor in the sub-pixel to be turned on. When the display panel is driven in the first display mode, the gate opening signal can be sequentially loaded on the gate lines GA1-GA6. Taking one display frame F01, the data line DA1 and the red sub-pixel connected with the data line DA1 as an example, when the signal ga1 outputting the high level of the gate opening signal on the gate line GA1, the transistor in the red sub-pixel R11 is turned on. And in the T11 time period corresponding to the high level of the signal ga1, the data voltage Vr11 corresponding to the display data is loaded on the data line DA1 connected with the red sub-pixel R11, so as to make the red sub-pixel R11 input the data voltage Vr11. And in the T11 time period, the signal ga2 outputting the high level of the gate opening signal on the gate line GA2, the transistor in the red sub-pixel R21 is turned on. The data voltage Vr11 is simultaneously input to the red sub-pixel R21, so as to pre-charge the red sub-pixel R21.

[0059] And in the T12 time period corresponding to the high level of the signal ga2, the data voltage Vr21 corresponding to the display data is loaded on the data line DA1 connected with the red sub-pixel R21, so as to make the red sub-pixel R21 input the data voltage Vr21. And in the T12 time period, the signal ga3 outputting the high level of the gate opening signal on the gate line GA3, the transistor in the red sub-pixel R31 is turned on. The data voltage Vr21 is simultaneously input to the red sub-pixel R31, so as to pre-charge the red sub-pixel R31.

[0060] And in the T13 time period corresponding to the high level of the signal ga3, the data voltage Vr31 corresponding to the display data is loaded on the data line DA1 connected with the red sub-pixel R31, so as to make the red sub-pixel R31 input the data voltage Vr31. And in the T13 time period, the signal ga4 outputting the high level of the gate opening signal on the gate line GA4, the transistor in the red sub-pixel R41 is turned on. The data voltage Vr31 is simultaneously input to the red sub-pixel R41, so as to pre-charge the red sub-pixel R41.

[0061] In the T14 time period corresponding to the high level of the signal ga4, the data line DA1 connected to the red sub-pixel R41 is loaded with the data voltage Vr41 corresponding to the display data, so as to charge the red sub-pixel R41 with the data voltage Vr41. In the T14 time period, the signal ga5 on the gate line GA5 outputs a high level gate opening signal, and the transistor in the red sub-pixel R51 is turned on. The data voltage Vr41 is simultaneously input to the red sub-pixel R51, so as to pre-charge the red sub-pixel R51.

[0062] In the T15 time period corresponding to the high level of the signal ga5, the data line DA1 connected to the red sub-pixel R51 is loaded with the data voltage Vr51 corresponding to the display data, so as to charge the red sub-pixel R51 with the data voltage Vr51. In the T15 time period, the signal ga6 on the gate line GA6 outputs a high level gate opening signal, and the transistor in the red sub-pixel R61 is turned on. The data voltage Vr51 is simultaneously input to the red sub-pixel R51, so as to pre-charge the red sub-pixel R51.

[0063] In the T16 time period corresponding to the high level of the signal ga6, the data line DA1 connected to the red sub-pixel R61 is loaded with the data voltage Vr61 corresponding to the display data, so as to charge the red sub-pixel R61 with the data voltage Vr61. The next red sub-pixel is pre-charged.

[0064] The implementation of the remaining sub-pixels is sequentially similar, until the sub-pixels in the entire display panel are charged with the data voltage, which is not described herein.

[0065] It should be noted that when the display panel is driven in the first display mode. The working process of each display frame can be basically the same as the working process of the display frame F01, which is not described herein.

[0066] Exemplarily, one of the plurality of display modes can be a second display mode. The second display mode includes: in each display frame, simultaneously driving the gate lines in at least two adjacent rows of gate lines as a gate line group, and sequentially driving the gate line groups. When the driving of the gate lines in the previous gate line group is completed and the driving of the gate lines in the next gate line group is in progress, the data line corresponding to the sub-pixel connected to the gate line in the next gate line group is input with the data voltage corresponding to the display data. Exemplarily, the two adjacent rows of gate lines can be taken as a gate line group; or, the three adjacent rows of gate lines can be taken as a gate line group; or, the si adjacent rows of gate lines can be taken as a gate line group; or, more adjacent rows of gate lines can be taken as a gate line group, which is not limited herein.

[0067] For example, in combination with Figure 3 and Figure 5As shown, the working process of the display panel driven in the second display mode is described. Wherein, two adjacent rows of gate lines are a gate line group. For example, the gate lines GA1 and GA2 are a gate line group, the gate lines GA3 and GA4 are a gate line group, and the gate lines GA5 and GA6 are a gate line group.

[0068] Wherein, ga1 represents the signal loaded on the gate line GA1, ga2 represents the signal loaded on the gate line GA2, ga3 represents the signal loaded on the gate line GA3, ga4 represents the signal loaded on the gate line GA4, ga5 represents the signal loaded on the gate line GA5, and ga6 represents the signal loaded on the gate line GA6. Vda1 represents the data voltage loaded on the data line DA1. And the high level in the signals ga1-ga6 can be used as a gate opening signal to control the transistor in the sub-pixel to be turned on. When the display panel is driven in the first display mode, taking one display frame F02, the data line DA1 and the red sub-pixel connected to the data line DA1 as an example, the signal ga1 on the gate line GA1 and the signal ga2 on the gate line GA2 simultaneously output the high level gate opening signal, and the transistors in the red sub-pixels R11 and R21 are simultaneously turned on. And in the T21 time period corresponding to the high level of the signals ga1 and ga2, the data voltage Vr1-2 corresponding to the display data is input to the data line DA1 connected to the red sub-pixels R11 and R21, so that the red sub-pixels R11 and R21 are charged with the data voltage Vr1-2. And in the T21 time period, the signal ga3 on the gate line GA3 and the signal ga4 on the gate line GA4 simultaneously output the high level gate opening signal, and the transistors in the red sub-pixels R31 and R41 are simultaneously turned on. The data voltage Vr1-2 is simultaneously input to the red sub-pixels R31 and R41 to pre-charge the red sub-pixels R31 and R41.

[0069] And in the T22 time period corresponding to the high level of the signals ga3 and ga4, the data voltage Vr3-4 corresponding to the display data is loaded on the data line DA1 connected to the red sub-pixels R31 and R41, so that the red sub-pixels R31 and R41 are charged with the data voltage Vr3-4. And in the T22 time period, the signal ga5 on the gate line GA5 and the signal ga6 on the gate line GA6 simultaneously output the high level gate opening signal, and the transistors in the red sub-pixels R51 and R61 are turned on. The data voltage Vr3-4 is simultaneously input to the red sub-pixels R51 and R61 to pre-charge the red sub-pixels R51 and R61.

[0070] And in the T23 time period corresponding to the high level of the signals ga5 and ga6, the data voltage Vr5-6 corresponding to the display data is loaded on the data line DA1 connected to the red sub-pixels R51 and R61, so that the red sub-pixels R51 and R61 are charged with the data voltage Vr5-6. And the next red sub-pixel is pre-charged.

[0071] The implementation of the remaining sub-pixels is by analogy, until the sub-pixels in the entire display panel are filled with data voltages, which will not be repeated here.

[0072] It should be noted that when the display panel is driven in the second display mode. The working process of each display frame can be basically the same as the working process of the display frame F02 described above, that is, the display panel can work in the DLG display mode, which will not be repeated here.

[0073] Exemplarily, one of the plurality of display modes can be a third display mode. Wherein the third display mode comprises: in the first display frame of the two adjacent display frames, the gate lines in the display panel are driven row by row, and when the gate line connected to the upper odd-numbered row sub-pixel is driven and the gate line connected to the lower odd-numbered row sub-pixel is being driven, the data voltage corresponding to the display data is input to the data line corresponding to the lower odd-numbered row sub-pixel; and in the second display frame of the two adjacent display frames, the gate lines in the display panel are driven row by row, and when the gate line connected to the upper even-numbered row sub-pixel is driven and the gate line connected to the lower even-numbered row sub-pixel is being driven, the data voltage corresponding to the display data is input to the data line corresponding to the lower even-numbered row sub-pixel.

[0074] For example, in combination with Figure 3 With Figure 6 As shown in the figure, the working process when the display panel is driven in the third display mode is described. Wherein ga1 represents the signal loaded on the gate line GA1, ga2 represents the signal loaded on the gate line GA2, ga3 represents the signal loaded on the gate line GA3, ga4 represents the signal loaded on the gate line GA4, ga5 represents the signal loaded on the gate line GA5, and ga6 represents the signal loaded on the gate line GA6. Vda1 represents the data voltage loaded on the data line DA1. Moreover, the high level in the signal ga1-ga6 can be used as a gate opening signal to control the transistor in the sub-pixel to be turned on. When the display panel is controlled to be driven in the third display mode, the gate opening signal can be loaded on the gate lines GA1-GA6 in turn. Taking the two adjacent display frames F03 and F04, the data line DA1 and the red sub-pixel connected to the data line DA1 as an example.

[0075] In the display frame F03, the signal ga1 on the gate line GA1 outputs a high level gate opening signal, and the transistor in the red sub-pixel R11 is turned on. In the time period T31 corresponding to the high level of the signal ga1, the data voltage Vr11 corresponding to the display data of the red sub-pixel R11 is loaded to the data line DA1 connected to the red sub-pixel R11, so that the data voltage Vr11 is input to the red sub-pixel R11. In the time period T31, the signal ga2 on the gate line GA2 outputs a high level gate opening signal, and the transistor in the red sub-pixel R21 is turned on. The data voltage Vr11 is simultaneously input to the red sub-pixel R21, so that the red sub-pixel R21 is pre-charged. In the time period T31, the signal ga3 on the gate line GA3 outputs a high level gate opening signal, and the transistor in the red sub-pixel R31 is turned on. The data voltage Vr11 is simultaneously input to the red sub-pixel R31, so that the red sub-pixel R31 is pre-charged. In the time period T31, the signal ga4 on the gate line GA4 outputs a high level gate opening signal, and the transistor in the red sub-pixel R41 is turned on. The data voltage Vr11 is simultaneously input to the red sub-pixel R41, so that the red sub-pixel R41 is pre-charged. In the time period T31, the signal ga5 on the gate line GA5 outputs a high level gate opening signal, and the transistor in the red sub-pixel R51 is turned on. The data voltage Vr11 is simultaneously input to the red sub-pixel R51, so that the red sub-pixel R51 is pre-charged. In the time period T11, the signal ga6 on the gate line GA6 outputs a high level gate opening signal, and the transistor in the red sub-pixel R61 is turned on. The data voltage Vr11 is simultaneously input to the red sub-pixel R61, so that the red sub-pixel R61 is pre-charged.

[0076] In the time period T32, the signal ga1 becomes low level, and the signal ga3 is high level. The data voltage Vr31 corresponding to the display data of the red sub-pixel R31 is loaded to the data line DA1 connected to the red sub-pixel R31, so that the red sub-pixel R31 is charged with the data voltage Vr31. In the high level of the signal ga2, the data voltage Vr31 is simultaneously input to the red sub-pixel R21, so that the red sub-pixel R21 is charged. In the high level of the signal ga4, the data voltage Vr31 is simultaneously input to the red sub-pixel R41, so that the red sub-pixel R41 is pre-charged. In the high level of the signal ga5, the data voltage Vr31 is simultaneously input to the red sub-pixel R51, so that the red sub-pixel R51 is pre-charged. In the high level of the signal ga6, the data voltage Vr31 is simultaneously input to the red sub-pixel R61, so that the red sub-pixel R61 is pre-charged.

[0077] In the T33 period, the signal ga3 is low and the signal ga5 is high. The data voltage Vr51 corresponding to the display data of the red sub-pixel R51 is loaded to the data line DA1 connected to the red sub-pixel R51, so that the red sub-pixel R51 is charged with the data voltage Vr51. Meanwhile, the high level of the signal ga4, the data voltage Vr51 is input to the red sub-pixel R41 at the same time, so that the red sub-pixel R41 is charged. Meanwhile, the high level of the signal ga6, the data voltage Vr51 is input to the red sub-pixel R61 at the same time, so that the red sub-pixel R61 is pre-charged.

[0078] In the T34 period, the red sub-pixel R61 is pre-charged with the data voltage corresponding to the display data of the red sub-pixel R71. The implementation of the remaining sub-pixels is similar in turn, until the data voltage of the sub-pixels in the entire display panel is charged, which is not described here. Optionally, the display frame F03 is an odd frame, then the data voltage in the second row of sub-pixels is equivalent to the data voltage inserted into the first row of sub-pixels and the third row of sub-pixels, and the data voltage in the fourth row of sub-pixels is equivalent to the data voltage inserted into the third row of sub-pixels and the fifth row of sub-pixels, that is, the data voltage in the even row of sub-pixels is equivalent to the data voltage inserted into the adjacent two odd rows of sub-pixels.

[0079] In the display frame F04, the signal ga2 on the gate line GA2 outputs a high level gate opening signal, the transistor in the red sub-pixel R21 is turned on. And in the T41 time period corresponding to the high level of the signal ga2, the data voltage Vr21 corresponding to the display data of the red sub-pixel R21 is loaded to the data line DA1 connected to the red sub-pixel R21, so that the red sub-pixel R21 inputs the data voltage Vr21. And in the T41 time period, the signal ga1 on the gate line GA1 outputs a high level gate opening signal, the transistor in the red sub-pixel R11 is turned on. The data voltage Vr21 is simultaneously input to the red sub-pixel R11 to charge the red sub-pixel R11. And in the T41 time period, the signal ga3 on the gate line GA3 outputs a high level gate opening signal, the transistor in the red sub-pixel R31 is turned on. The data voltage Vr21 is simultaneously input to the red sub-pixel R31 to pre-charge the red sub-pixel R31. And in the T41 time period, the signal ga4 on the gate line GA4 outputs a high level gate opening signal, the transistor in the red sub-pixel R41 is turned on. The data voltage Vr21 is simultaneously input to the red sub-pixel R41 to pre-charge the red sub-pixel R41. And in the T41 time period, the signal ga5 on the gate line GA5 outputs a high level gate opening signal, the transistor in the red sub-pixel R51 is turned on. The data voltage Vr21 is simultaneously input to the red sub-pixel R51 to pre-charge the red sub-pixel R51. And in the T41 time period, the signal ga6 on the gate line GA6 outputs a high level gate opening signal, the transistor in the red sub-pixel R61 is turned on. The data voltage Vr21 is simultaneously input to the red sub-pixel R61 to pre-charge the red sub-pixel R61.

[0080] And in the T42 time period, the signal ga2 becomes low, and the signal ga4 is high. The data voltage Vr41 corresponding to the display data of the red sub-pixel R41 is loaded to the data line DA1 connected to the red sub-pixel R41, so that the red sub-pixel R41 charges the data voltage Vr41. And the high level of the signal ga3, the data voltage Vr41 is simultaneously input to the red sub-pixel R31 to charge the red sub-pixel R31. And the high level of the signal ga5, the data voltage Vr41 is simultaneously input to the red sub-pixel R51 to pre-charge the red sub-pixel R51. And the high level of the signal ga6, the data voltage Vr41 is simultaneously input to the red sub-pixel R61 to pre-charge the red sub-pixel R61.

[0081] In the T43 time period, the signal ga4 becomes low, and the signal ga6 becomes high. The data voltage Vr61 corresponding to the display data of the red sub-pixel R61 is loaded to the data line DA1 connected to the red sub-pixel R61, so that the red sub-pixel R61 is charged with the data voltage Vr61. In addition, the high level of the signal ga5, and the data voltage Vr61 is simultaneously input to the red sub-pixel R51, so as to charge the red sub-pixel R51. In addition, the other red sub-pixels are pre-charged. The implementation of the remaining sub-pixels is sequentially extended until the sub-pixels in the entire display panel are charged with the data voltage, which is not described herein. Optionally, the display frame F04 is an even frame, and the data voltage in the third row of sub-pixels is equivalent to the data voltage inserted into the second row of sub-pixels and the fourth row of sub-pixels. The data voltage in the fifth row of sub-pixels is equivalent to the data voltage inserted into the fourth row of sub-pixels and the sixth row of sub-pixels, that is, the data voltage in the odd row of sub-pixels is inserted into the data voltage in the adjacent two even rows of sub-pixels. At this time, the data voltage in the first row of sub-pixels is inserted into the data voltage in the second row of sub-pixels.

[0082] It should be noted that when the display panel is driven in the third display mode. The working processes of the remaining display frames can be basically the same as those of the display frame F03 and the display frame F04 described above, that is, the display panel can work in the HSR display mode, which is not described herein.

[0083] In the embodiments of the present disclosure, the refresh frequency of the first display mode can be less than the refresh frequency of the second display mode and the refresh frequency of the third display mode. For example, the refresh frequency of the display panel can include 30Hz, 48Hz, 60Hz, 90Hz, 96Hz, 120Hz, 144Hz, 240Hz, etc. The refresh frequency of the first display mode, the refresh frequency of the second display mode, and the refresh frequency of the third display mode can be selected from the refresh frequency supported by the display panel. For example, the refresh frequency of the first display mode includes 60Hz, the refresh frequency of the second display mode includes 120Hz, and the refresh frequency of the third display mode includes 120Hz. Of course, in actual application, the refresh frequency of the first display mode, the refresh frequency of the second display mode, and the refresh frequency of the third display mode can be determined according to the needs of actual application, which is not limited herein.

[0084] In the embodiments of the present disclosure, since the display panel includes multiple display modes, the display mode can be switched in different application scenarios. In combination with Figure 7 As shown in the figure, the driving method of the display panel can include the following steps:

[0085] S10, when it is determined that the current display frame is switched to different display modes, the display data corresponding to the preset setting picture is obtained.

[0086] S20, switch the current display mode to the target display mode when the display panel displays the setting picture according to the display data corresponding to the setting picture in the current display frame.

[0087] The driving method provided by the embodiments of the present disclosure can switch between different display modes according to the actual application scenario of the display panel. When switching between different display modes, the normal picture is not displayed, but the pre-stored setting picture is displayed. When the display panel displays the setting picture, the switching action of different display modes is performed. In this way, the display frame of the normal display picture is not occupied, and the display abnormality of the normal picture can be avoided.

[0088] In addition, the driving method provided by the embodiments of the present disclosure can switch between different display modes according to the actual application scenario of the display panel. For example, a game display picture requires a high refresh rate, however, the high refresh rate will compress the charging time of the sub-pixel of the display panel, resulting in insufficient charging of the sub-pixel. In the embodiments of the present disclosure, when switching from a display mode with a low refresh rate to a display mode with a high refresh rate, the high refresh rate can be realized while improving the charging rate of the sub-pixel.

[0089] Exemplarily, a flash memory (Flash) is arranged on the circuit board where the timing controller 200 is located, and the display data corresponding to the setting picture is stored in the flash memory, which includes the digital voltage form of the data voltage corresponding to each sub-pixel. The timing controller 200 can obtain the pre-stored display data corresponding to the setting picture from the flash memory when determining to switch between different display modes in the current display frame, and output the obtained display data corresponding to the setting picture to the source driving circuit 120. The source driving circuit 120 can receive the display data corresponding to the setting picture, and load the data voltage of the corresponding display data to the data line according to the display data corresponding to the setting picture, so as to drive the display panel to display the setting picture in the current display frame. In addition, the timing controller 200 switches the current display mode to the target display mode when the source driving circuit 120 drives the display panel to display the setting picture according to the display data corresponding to the setting picture in the current display frame.

[0090] Exemplarily, when switching between different display modes, the user can manually touch the physical key or the touch key to select the target display mode. Alternatively, the system on chip (SOC) can automatically determine the target display mode according to the picture to be displayed. Figure 1As shown, the display device can further include a system chip 300. When it is determined that the current display frame is to be switched to a different display mode, for example, when a user manually touches a touch button to select a target display mode, the system chip 300 can determine that the current display frame is to be switched to a different display mode, and can output a mode switching instruction to the timing controller 200. Upon receiving the mode switching instruction, the timing controller 200 can perform step S10: obtaining display data corresponding to the set picture.

[0091] In some examples, the current display mode can be the first display mode, and the target display mode can be the second display mode. This can enable the display panel to be switched from the first display mode to the second display mode as a DLG display mode. For example, a game display picture requires a high refresh rate, and thus, the second display mode as a DLG display mode can be used when the display panel is to display a game display picture, which can enable a high refresh rate and improve the charging rate of the sub-pixels.

[0092] In yet other examples, the current display mode can be the first display mode, and the target display mode can be the third display mode. This can enable the display panel to be switched from the first display mode to the third display mode as a HSR display mode. For example, a game display picture requires a high refresh rate, and thus, the third display mode as a HSR display mode can be used when the display panel is to display a game display picture, which can enable a high refresh rate and improve the charging rate of the sub-pixels.

[0093] In yet other examples, the current display mode can be the second display mode, and the target display mode can be the third display mode. This can enable the display panel to be switched from the second display mode as a DLG display mode to the third display mode as a HSR display mode. Since the picture resolution displayed by the display panel in the second display mode as a DLG display mode is reduced, although the picture resolution displayed by the display panel in the third display mode as a HSR display mode is also reduced, the voltages input by adjacent two rows of sub-pixels in the same column are not completely the same when the display panel is in the third display mode as a HSR display mode, and thus, the picture displayed by the display panel in the third display mode as a HSR display mode is more detailed. Thus, the third display mode as a HSR display mode can be used when the display panel is to display a game display picture, which can further improve the display quality of the picture.

[0094] In yet some examples, the current display mode can be the third display mode, and the target display mode can be the second display mode. In this way, the display panel can be switched from the third display mode as the HSR display mode to the second display mode as the DLG display mode. In this way, the second display mode as the DLG display mode can be adopted when the display panel is to display a game type display picture, so as to further improve the charging rate of the sub-pixels.

[0095] In yet some examples, the current display mode can be the second display mode, and the target display mode can be the first display mode. In this way, the display panel can be switched from the second display mode as the DLG display mode to the first display mode. For example, a static type display picture does not need a high refresh frequency, but needs a lower power consumption, so the first display mode as the normal display mode can be adopted when the display panel is to display a static type display picture, so as to reduce the power consumption.

[0096] In yet some examples, the current display mode can be the third display mode, and the target display mode can be the first display mode. In this way, the display panel can be switched from the third display mode as the HSR display mode to the first display mode. For example, a static type display picture does not need a high refresh frequency, but needs a lower power consumption, so the first display mode as the normal display mode can be adopted when the display panel is to display a static type display picture, so as to reduce the power consumption.

[0097] Gray scale, generally, the brightness between the darkest and the brightest is divided into several parts, so as to facilitate the screen brightness control. For example, the displayed image is composed of red, green and blue three colors, each of which can show different brightness levels, and different brightness levels of red, green and blue combined together can form different colors. For example, the gray scale bit number of the liquid crystal display panel is 6bit, and the three colors of red, green and blue have 64 (i.e. 2 6 ) gray scales, and the 64 gray scale values are 0-63 respectively. The gray scale bit number of the liquid crystal display panel is 8bit, and the three colors of red, green and blue have 256 (i.e. 2 8 ) gray scales, and the 256 gray scale values are 0-255 respectively. The gray scale bit number of the liquid crystal display panel is 10bit, and the three colors of red, green and blue have 1024 (i.e. 2 10 ) gray scales, and the 1024 gray scale values are 0-1023 respectively. The gray scale bit number of the liquid crystal display panel is 12bit, and the three colors of red, green and blue have 4096 (i.e. 2 12 ) gray scales, and the 4096 gray scale values are 0-4093 respectively.

[0098] In the embodiments of the present disclosure, the setting picture can include a pure color picture. For example, the setting picture can include a red pure color picture, a green pure color picture, and a blue pure color picture. For example, taking that the display panel has 0-255 gray scale values as an example, when the display panel displays the red pure color picture, each red sub-pixel in the display panel inputs a data voltage corresponding to display data of the same gray scale value (for example, 127 gray scale value, 255 gray scale value, etc.), and each green sub-pixel and each blue sub-pixel inputs a data voltage corresponding to display data of 0 gray scale value. When the display panel displays the green pure color picture, each green sub-pixel in the display panel inputs a data voltage corresponding to display data of the same gray scale value (for example, 127 gray scale value, 255 gray scale value, etc.), and each red sub-pixel and each blue sub-pixel inputs a data voltage corresponding to display data of 0 gray scale value. When the display panel displays the blue pure color picture, each blue sub-pixel in the display panel inputs a data voltage corresponding to display data of the same gray scale value (for example, 127 gray scale value, 255 gray scale value, etc.), and each green sub-pixel and each red sub-pixel inputs a data voltage corresponding to display data of 0 gray scale value.

[0099] In the embodiments of the present disclosure, the setting picture includes a picture in which sub-pixels of various colors are all of the same gray scale value. For example, taking that the display panel has 0-255 gray scale values as an example, a picture in which sub-pixels of various colors are all of 127 gray scale value. Or, a picture in which sub-pixels of various colors are all of 100 gray scale value. Or, a picture in which sub-pixels of various colors are all of 255 gray scale value. Or, a picture in which sub-pixels of various colors are all of 200 gray scale value.

[0100] In the embodiments of the present disclosure, the system on chip 300 can output display data to be displayed of the current display frame in the current display frame. When the current display mode is switched to the target display mode, the timing controller 200 can also acquire the display data to be displayed of the current display frame. And, after the current display mode is switched to the target display mode when the display panel is driven to display the setting picture according to the display data corresponding to the setting picture in the current display frame, the timing controller 200 can also drive the display panel to display a corresponding picture according to the display data to be displayed in the next display frame based on the target display mode.

[0101] In the embodiments of the present disclosure, as Figure 8As shown, the display device can further include a connector 400. The first end 410 of the connector 400 is connected with the system chip 300, and the second end 420 of the connector 400 is connected with the timing controller 200. The first end 410 of the connector 400 can include a first IIC pin 411 and a first switch instruction transmission pin 412, and the second end 420 of the connector 400 can include a second IIC pin 421 and a second switch instruction transmission pin 422. For example, the system chip 300 outputs a handshake signal through the first IIC pin 410, the timing controller 200 receives the handshake signal through the second IIC pin 421, and performs handshake with the system chip 300 after receiving the handshake signal. After the handshake is completed, it is indicated that the system chip 300 and the timing controller 200 are connected, and signal transmission can be performed. The system chip 300 can output a mode switching instruction through the first switch instruction transmission pin 412, and the timing controller 200 can receive the mode switching instruction output by the system chip 300 through the second switch instruction transmission pin 422.

[0102] In the embodiment of the present disclosure, as shown in Figure 8 The first end 410 of the connector 400 can further include a first data transmission pin 413, and the second end 420 of the connector 400 can further include a second data transmission pin 423. The system chip 300 can output display data to be displayed of a current display frame through the first data transmission pin 413. The timing controller 200 receives the display data to be displayed of the current display frame through the second data transmission pin 423.

[0103] In the embodiment of the present disclosure, the first end 410 of the connector 400 and the second end 420 of the connector 400 can be 51 pin interfaces respectively. The first IIC pin includes a first SDA pin and a first SDA pin, and the first data transmission pin includes a first VBYONE pin. The second IIC pin includes a second SDA pin and a second SDA pin, and the second data transmission pin includes a second VBYONE pin. By setting the first VBYONE pin and the second VBYONE pin, the Video by one mode can be used to transmit display data of the LVDS differential signal through a wire, thereby reducing the PCN wiring.

[0104] The following takes the 51 pin interface as an example to illustrate the second end 420 of the connector 400. In combination with Figure 8 to Figure 10As shown, the second end 420 of the connector 400 includes a 51-pin interface having 51 pins: pin1-pin51. Among them, pin1-pin8 can perform the function of transmitting voltage VDDIN. pin10-pin14, pin24, pin27, pin30, pin33, pin36, pin39, pin42, pin45, pin48 and pin51 are grounded. pin9, pin15, pin16, pin17 and pin20 are floating (represented by "x" in the middle) Figure 9 Among them, pin18 can perform the function of SDA, pin19 can perform the function of SCL, pin21 performs the function of VX1_BIST, pin22 performs the function of VX1_SECTION, pin23 performs the function of VX1_HSR, pin25 performs the function of VX1_HTPDN, pin26 performs the function of VX1_LOCKN, pin28 performs the function of RX0N, pin29 performs the function of RX0P, pin31 performs the function of RX1N, pin32 performs the function of RX1P, pin34 performs the function of RX2N, pin35 performs the function of RX2P, pin37 performs the function of RX3N, pin38 performs the function of RX3P, pin40 performs the function of RX4N, pin41 performs the function of RX4P, pin43 performs the function of RX5N, pin44 performs the function of RX5P, pin46 performs the function of RX6N, pin47 performs the function of RX6P, pin49 performs the function of RX7N, and pin50 performs the function of RX7P. Among them, pin23 is the second switching instruction transmission pin, pin18 is the second SDA pin, pin19 is the second SCL pin, pin28, pin29, pin31, pin32, pin34, pin35, pin37, pin38, pin40, pin41, pin43, pin44, pin46, pin47, pin49 and pin50 are the second VBYONE pin. It should be noted that Figure 10 The pin angle represented by "x" in the middle.

[0105] pin 21 of the pin interface 51 is connected to the pin PX_LOCK_N in the timing controller 200, the pin 25 of the pin interface 51 is connected to the corresponding pin foot in the timing controller 200, the pin 28 of the pin interface 51 is connected to the pin VX1_0N in the timing controller 200, the pin 29 of the pin interface 51 is connected to the pin VX1_0P in the timing controller 200, the pin 31 of the pin interface 51 is connected to the pin VX1_1N in the timing controller 200, the pin 32 of the pin interface 51 is connected to the pin VX1_1P in the timing controller 200, the pin 34 of the pin interface 51 is connected to the pin VX1_2N in the timing controller 200, the pin 35 of the pin interface 51 is connected to the pin VX1_2P in the timing controller 200, the pin 37 of the pin interface 51 is connected to the pin VX1_3N in the timing controller 200, the pin 38 of the pin interface 51 is connected to the pin VX1_3P in the timing controller 200, the pin 40 of the pin interface 51 is connected to the pin VX1_4N in the timing controller 200, the pin 41 of the pin interface 51 is connected to the pin VX1_4P in the timing controller 200, the pin 43 of the pin interface 51 is connected to the pin VX1_5N in the timing controller 200, the pin 44 of the pin interface 51 is connected to the pin VX1_5P in the timing controller 200, the pin 46 of the pin interface 51 is connected to the pin VX1_6N in the timing controller 200, the pin 47 of the pin interface 51 is connected to the pin VX1_6P in the timing controller 200, the pin 49 of the pin interface 51 is connected to the pin VX1_7N in the timing controller 200, and the pin 50 of the pin interface 51 is connected to the pin VX1_7P in the timing controller 200.

[0106] In addition, the other pin feet in the timing controller 200 and the functions performed by the pin feet are basically the same as those in the related art, and thus are not described herein. Figure 10

[0107] ​Exemplarily, the mode switching instruction can be sent in the form of digital signal. For example, the mode switching instruction can be in binary, decimal, hexadecimal, etc. For example, in hexadecimal, as shown in Table 1, the instruction output by the system chip 300 to the timing controller can be composed of 5 bytes. Specifically, the mode switching instruction includes Byte0, Byte1, Byte2, Byte3, Byte4. Wherein, Byte0, Byte1, Byte2, Byte3, Byte4 are 7-bit digital signals respectively. FA, EA, DG, NG and HG represent the instructions output by the system chip 300 to the timing controller. The specific application of these instructions is described later.

[0108]

[0109] Table 1

[0110] Exemplarily, in combination with Figure 8 to Figure 10 As shown in FIG. 5, the system chip 300 defaults to the first display mode in the initial state, and drives the display panel to display the picture. When the display panel works in the first display mode, if the display mode is to be switched in the current display frame, the user can manually touch the touch key to select the second display mode as the DLG display mode. The system chip 300 can output the mode switching instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 corresponding to FA in Table 1) through the first switching instruction transmission pin 412 in the first end 410 of the 51 pin interface. The timing controller 200 receives the FA mode switching instruction through the second switching instruction transmission pin 422 in the second end 420 of the 51 pin interface. The timing controller 200 can obtain the display data corresponding to a preset setting picture from the flash memory according to the mode switching instruction, and output the display data to the source driving circuit 120 in the form of VBO signal through the pin TX_0N, TX_0P, TX_1N, TX_1P, …, TX_10N, TX_10P, TX_11N, TX_11P of the timing controller 200. After the source driving circuit 120 receives the display data corresponding to the setting picture, the source driving circuit 120 controls each sub-pixel to input the corresponding data voltage in the first display mode in the current display frame, so that the display panel displays the setting picture.

[0111] At this time, the system chip 300 outputs a mode selection instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 in Table 1 corresponding to DG) through the first switch instruction transmission pin 412 in the first end 410 of the 51pin interface, and the timing controller 200 receives the DG mode selection instruction through the second switch instruction transmission pin 422 in the second end 420 of the 51pin interface. The timing controller 200 switches the first display mode to the second display mode according to the DG mode selection instruction while the display panel displays the set picture, and completes the switching process between different display modes. In addition, the system chip 300 receives the 8K 4K 60Hz display data to be displayed in the current display frame, converts the received display data to be displayed into 8K 2K 120Hz display data, and transmits the 8K 2K 120Hz display data to the timing controller 200 through the first VBYONE pin 413 in the first end 410 of the 51pin interface. The timing controller 200 receives the 8K 2K 120Hz display data through the second VBYONE pin 423 in the second end 420 of the 51pin interface.

[0112] Then, the system chip 300 outputs a mode exit instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 in Table 1 corresponding to EA) through the first switch instruction transmission pin 412 in the first end 410 of the 51pin interface, and the timing controller 200 receives the EA mode exit instruction through the second switch instruction transmission pin 422 in the second end 420 of the 51pin interface. The timing controller 200 outputs the 8K 2K 120Hz display data to the source drive circuit 120 in the form of VBO signal through the pins TX_0N, TX_0P, TX_1N, TX_1P, …, TX_10N, TX_10P, TX_11N, TX_11P of the timing controller 200. After receiving the display data, the source drive circuit 120 can control each sub-pixel to input the corresponding display data according to the display data to be displayed obtained in the current display frame based on the second display mode in the next display frame, so that the display panel displays the corresponding picture, thereby realizing the driving process in the second display mode.

[0113] For example, in combination with Figure 8 to Figure 10As shown, the system chip 300 defaults to the second display mode in the initial state, and drives the display panel to display a picture. When the display panel is working in the second display mode, if different display modes are to be switched in the current display frame, the user can manually touch the touch button to select the first display mode as the normal display mode, and the system chip 300 can output a mode switching instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 in Table 1 corresponding to FA) through the first switching instruction transmission pin 412 in the first end 410 of the 51pin interface, and the timing controller 200 receives the FA mode switching instruction through the second switching instruction transmission pin 422 in the second end 420 of the 51pin interface. The timing controller 200 can obtain the display data corresponding to a preset setting picture from the flash memory according to the mode switching instruction, and output the display data to the source driving circuit 120 in the form of a VBO signal through the pin TX_0N, TX_0P, TX_1N, TX_1P, …, TX_10N, TX_10P, TX_11N, TX_11P of the timing controller 200. After the source driving circuit 120 receives the display data corresponding to the setting picture, the source driving circuit 120 controls each sub-pixel to input the corresponding data voltage in the second display mode in the current display frame, so that the display panel displays the setting picture.

[0114] At this time, the system chip 300 outputs a mode selection instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 in Table 1 corresponding to NG) through the first switching instruction transmission pin 412 in the first end 410 of the 51pin interface, and the timing controller 200 receives the NG mode selection instruction through the second switching instruction transmission pin 422 in the second end 420 of the 51pin interface. The timing controller 200 switches the second display mode to the first display mode according to the NG mode selection instruction while the display panel displays the setting picture, and completes the switching process between different display modes. In addition, the system chip 300 receives the 8K 2K 120Hz display data to be displayed in the current display frame, converts the received display data to be displayed into 8K 4K 60Hz display data, and transmits the 8K 4K 60Hz display data to the timing controller 200 through the first VBYONE pin 413 in the first end 410 of the 51pin interface. The timing controller 200 receives the 8K 4K 60Hz display data through the second VBYONE pin 423 in the second end 420 of the 51pin interface.

[0115] Afterwards, the system chip 300 outputs a mode exit instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 corresponding to EA in Table 1) through the first switch instruction transmission pin 412 in the first end 410 of the 51 pin interface, and the timing controller 200 receives the EA mode exit instruction through the second switch instruction transmission pin 422 in the second end 420 of the 51 pin interface. The timing controller 200 outputs the display data of 8K 4K 60Hz to the source driving circuit 120 in the form of VBO signal through the pin TX_0N, TX_0P, TX_1N, TX_1P, ……TX_10N, TX_10P, TX_11N, TX_11P of the timing controller 200. After the source driving circuit 120 receives the display data, in the next display frame, the source driving circuit 120 can control each sub-pixel to input the corresponding display data according to the display data obtained in the current display frame based on the first display mode, so that the display panel displays the corresponding picture, so as to realize the driving process in the first display mode.

[0116] For example, in combination with Figure 8 to Figure 10 As shown in the figure, the system chip 300 defaults to the first display mode in the initial state to drive the display panel to display the picture. When the display panel works in the first display mode, if different display modes are to be switched in the current display frame, the user can manually touch the touch button to select the second display mode as the DLG display mode, and the system chip 300 can output a mode switching instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 corresponding to FA in Table 1) through the first switch instruction transmission pin 412 in the first end 410 of the 51 pin interface, and the timing controller 200 receives the FA mode switching instruction through the second switch instruction transmission pin 422 in the second end 420 of the 51 pin interface. The timing controller 200 can obtain the display data corresponding to a preset picture from the flash memory according to the mode switching instruction, and output the display data to the source driving circuit 120 in the form of VBO signal through the pin TX_0N, TX_0P, TX_1N, TX_1P, ……TX_10N, TX_10P, TX_11N, TX_11P of the timing controller 200. After the source driving circuit 120 receives the display data corresponding to the preset picture, in the current display frame, the source driving circuit 120 controls each sub-pixel to input the corresponding display data in the first display mode, so that the display panel displays the preset picture.

[0117] And at this time, the system chip 300 outputs the mode selection instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 corresponding to HG in Table 1) through the first switch instruction transmission pin 412 in the first end 410 of the 51pin interface, and the timing controller 200 receives the HG mode selection instruction through the second switch instruction transmission pin 422 in the second end 420 of the 51pin interface. The timing controller 200 switches the first display mode to the third display mode while the display panel displays the set picture according to the DG mode selection instruction, and completes the switching process between different display modes. In addition, the system chip 300 receives the 8K 4K 60Hz display data to be displayed in the current display frame, converts the received display data to be displayed into 8K 2K 120Hz display data, and transmits the 8K 2K 120Hz display data to the timing controller 200 through the first VBYONE pin 413 in the first end 410 of the 51pin interface. The timing controller 200 receives the 8K 2K 120Hz display data through the second VBYONE pin 423 in the second end 420 of the 51pin interface.

[0118] After that, the system chip 300 outputs the mode exit instruction (for example, Byte0, Byte1, Byte2, Byte3, Byte4 corresponding to EA in Table 1) through the first switch instruction transmission pin 412 in the first end 410 of the 51pin interface, and the timing controller 200 receives the EA mode exit instruction through the second switch instruction transmission pin 422 in the second end 420 of the 51pin interface. The timing controller 200 outputs the 8K 2K 120Hz display data to the source drive circuit 120 in the form of a VBO signal through the pin TX_0N, TX_0P, TX_1N, TX_1P, …, TX_10N, TX_10P, TX_11N, TX_11P of the timing controller 200. After receiving the display data, the source drive circuit 120 can control each sub-pixel to input the corresponding display data based on the third display mode in the next display frame, so as to drive the process in the third display mode.

[0119] In specific implementation, in the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those skilled in the art, and are not described here in detail, nor should they be regarded as a limitation on the present disclosure.

[0120] The driving method and the display device provided by the embodiments of the present disclosure can switch between different display modes according to the actual application scenario of the display panel. When switching between different display modes, the display device does not display a normal picture, but displays a preset setting picture. When the display panel displays the setting picture, the switching action of different display modes is performed. In this way, the display frame for displaying a normal picture is not occupied, and the display abnormality of the normal picture can be avoided.

[0121] In addition, the driving method and the display device provided by the embodiments of the present disclosure can switch between different display modes according to the actual application scenario of the display panel. For example, a game display picture needs a high refresh frequency. However, the high refresh frequency will compress the charging time of the sub-pixel of the display panel, resulting in insufficient charging of the sub-pixel. In the embodiments of the present disclosure, when switching from a display mode with a low refresh frequency to a display mode with a high refresh frequency, the high refresh frequency can be realized while improving the charging rate of the sub-pixel.

[0122] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure belong to the scope of the claims of the present disclosure and the equivalent technologies thereof, the present disclosure also intends to include these modifications and variations.

Claims

1. A driving method for a display panel, characterized in that, include: When it is determined that the current display frame is switching between different display modes, the display data corresponding to the pre-stored set screen is obtained; The display data corresponding to the pre-stored preset screen is obtained from the flash memory of the timing controller; When the display panel displays the set screen in the current display frame according to the display data corresponding to the set screen, the current display mode is switched to the target display mode; The display panel includes a first display mode; wherein the first display mode includes: driving the gate lines line by line in each display frame, and when the previous row of gate lines has been driven and the next row of gate lines is being driven, inputting the data voltage corresponding to the data line of the sub-pixel connected to the next row of gate lines; The display panel includes a second display mode; wherein, the second display mode includes: in each display frame, taking at least two adjacent rows of gate lines as a gate line group, simultaneously driving the gate lines in the same gate line group, and driving the gate line groups one by one; when the gate lines in the previous gate line group are driven and the gate lines in the next gate line group are being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group; The display panel includes a third display mode; wherein the third display mode includes: in the first display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous odd-numbered row of sub-pixels are driven and the gate lines connected to the next odd-numbered row of sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next odd-numbered row of sub-pixels; and in the second display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous even-numbered row of sub-pixels are driven and the gate lines connected to the next even-numbered row of sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next even-numbered row of sub-pixels; The current display mode is one of the first display mode, the second display mode, and the third display mode; the target display mode is one of the first display mode, the second display mode, and the third display mode other than the current display mode.

2. The driving method as described in claim 1, characterized in that, When switching the current display mode to the target display mode, the method further includes: obtaining the display data to be displayed for the current display frame; After switching the current display mode to the target display mode when the display panel is driven to display the set screen in the current display frame according to the display data corresponding to the set screen, the method further includes: based on the target display mode, in the next display frame, driving the display panel to display the corresponding screen according to the display data to be displayed.

3. The driving method according to any one of claims 1-2, characterized in that, The display panel includes sub-pixels of various colors; The set screen includes a solid color screen; Or the set screen may include a screen in which all sub-pixels of various colors have the same grayscale value.

4. A display device, characterized in that, include: Display panel, including source drive circuitry; The timing controller is configured to, when it is determined that the current display frame is switching between different display modes, retrieve and output display data corresponding to a pre-stored setting screen from the flash memory of the timing controller; and, when the display panel is driven to display the setting screen in the current display frame according to the display data corresponding to the setting screen, switch the current display mode to the target display mode. The display panel includes a first display mode; wherein the first display mode includes: driving the gate lines line by line in each display frame, and when the previous row of gate lines has been driven and the next row of gate lines is being driven, inputting the data voltage corresponding to the data line of the sub-pixel connected to the next row of gate lines; The display panel includes a second display mode; wherein, the second display mode includes: in each display frame, taking at least two adjacent rows of gate lines as a gate line group, simultaneously driving the gate lines in the same gate line group, and driving the gate line groups one by one; when the gate lines in the previous gate line group are driven and the gate lines in the next gate line group are being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group; The display panel includes a third display mode; wherein the third display mode includes: in the first display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous odd-numbered row of sub-pixels are driven and the gate lines connected to the next odd-numbered row of sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next odd-numbered row of sub-pixels; and in the second display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous even-numbered row of sub-pixels are driven and the gate lines connected to the next even-numbered row of sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next even-numbered row of sub-pixels; The current display mode is one of the first display mode, the second display mode, and the third display mode; the target display mode is one of the first display mode, the second display mode, and the third display mode, other than the current display mode. The source drive circuit is configured to receive display data corresponding to the set screen, and drive the display panel to display the set screen in the current display frame according to the display data corresponding to the set screen.

5. The display device as claimed in claim 4, characterized in that, Also includes: The system-on-a-chip is configured to output a mode switching command when it is determined that the current display frame is switching between different display modes; The timing controller is further configured to: upon receiving the mode switching instruction, acquire the display data corresponding to the set screen.

6. The display device as claimed in claim 5, characterized in that, The system-on-a-chip is also configured to output the display data to be displayed for the current display frame in the current display frame; The timing controller is further configured to acquire display data to be displayed in the current display frame; and, based on the target display mode, drive the display panel to display the corresponding image in the next display frame according to the display data to be displayed.

7. The display device as claimed in claim 6, characterized in that, Also includes: A connector; the first end of the connector is connected to the system-on-a-chip, and the second end of the connector is connected to the timing controller; wherein, the first end of the connector includes a first IIC pin and a first switching command transmission pin; the second end of the connector includes a second IIC pin and a second switching command transmission pin; The system-on-a-chip is also configured to output the mode switching instruction via the first switching instruction transmission pin, and to output a handshake signal via the first IIC pin; The timing controller is also configured to receive the mode switching instruction via the second switching instruction transmission pin, and to receive the handshake signal via the second IIC pin, and to perform a handshake with the system-on-a-chip after receiving the handshake signal.

8. The display device as claimed in claim 7, characterized in that, The first and second ends of the connector are both 51-pin interfaces.

9. The display device as claimed in claim 8, characterized in that, The first IIC pin includes a first SDA pin and a first SDA pin; The second IIC pin includes a second SDA pin and a second SDA pin.

10. The display device as claimed in claim 9, characterized in that, The first end of the connector further includes a first data transmission pin; the second end of the connector further includes a second data transmission pin. The system-on-a-chip is also configured to output the display data to be displayed for the current display frame through the first data transmission pin; The timing controller is also configured to receive the display data to be displayed in the current display frame via the second data transmission pin.

11. The display device as claimed in claim 10, characterized in that, The first data transmission pin includes a first VBYONE pin; the second data transmission pin includes a second VBYONE pin.

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