Metal interconnect structure and method of making same

Abstract

The present invention discloses a metal interconnect structure and a method for fabricating the same. The method for fabricating the metal interconnect structure includes forming a first metal interconnect in a first intermetal dielectric layer on a substrate, forming a cap layer on the first metal interconnect, forming a second intermetal dielectric layer on the cap layer, removing part of the second intermetal dielectric layer to form an opening by a first etching fabrication process, performing a plasma treatment fabrication process, and removing part of the cap layer by a second etching fabrication process.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201810933058.X, application date: August 16, 2018, invention title: metal interconnect structure and manufacturing method thereof). Technical Field

[0002] This invention relates to a metal interconnect structure, and more particularly to a metal interconnect structure with a cover layer of different thicknesses. Background Technology

[0003] With the increasing integration density and high performance requirements of integrated circuits, the fabrication of low-resistance multilevel interconnects has gradually become an essential method in many semiconductor integrated circuit manufacturing processes. The copper dual damascene technique combined with an inter-metal dielectric (IMD) layer made of a low-dielectric-constant material is currently the most popular combination of metal interconnect fabrication processes. Especially for the manufacturing of high-integration, high-speed logic integrated circuit chips and deep sub-micron semiconductor fabrication processes below 0.18 micrometers, copper dual damascene interconnect technology has become increasingly important in integrated circuit manufacturing processes and is bound to become the standard interconnect technology for the next generation of semiconductor manufacturing processes.

[0004] However, in current copper-metal dual damascene interconnect fabrication processes, etching processes can cause copper discontinuities at the bottom of the via conductor near the underlying trench conductor, thus affecting device performance. Therefore, improving the current copper interconnect fabrication process to solve this problem is an important issue. Summary of the Invention

[0005] One embodiment of the present invention discloses a method for fabricating a metal interconnect structure. First, a first metal interconnect is formed in a first inter-metal dielectric layer on a substrate. Then, a masking layer is formed on the first metal interconnect, and a second inter-metal dielectric layer is formed on the masking layer. A first etching process is performed to remove part of the second inter-metal dielectric layer to form an opening. A plasma processing process is then performed, followed by a second etching process to remove part of the masking layer.

[0006] Another embodiment of the present invention discloses a metal interconnect structure, which mainly includes a first metal interconnect disposed in an inter-metal dielectric layer on a substrate, wherein the upper surface of the first metal interconnect is flush with the upper surface of the inter-metal dielectric layer; a second metal interconnect disposed on the first metal interconnect; and a cover layer disposed between the surface of the first metal interconnect and the second metal interconnect, wherein the cover layer comprises a conductive material. Attached Figure Description

[0007] Figures 1 to 5 This is a schematic diagram of a method for fabricating a metal interconnect structure according to a preferred embodiment of the present invention;

[0008] Figure 6 This is a schematic diagram of a metal interconnect structure according to an embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 12 substrates, 14 interlayer dielectric layers

[0011] 16 First intermetallic dielectric layer 18 Metal interconnect

[0012] 20 Barrier layer 22 Padding layer

[0013] 24 Metal layer 26 Covering layer

[0014] 28 Stop layer 30 Second intermetallic dielectric layer

[0015] 32 Patterned Mask 34 First Etching Process

[0016] 36 Opening 38 Polymer

[0017] 40 Plasma treatment fabrication process 42 Second etching fabrication process

[0018] 44 Stepped section 46 Barrier layer

[0019] 48 Padding layer 50 Metal layer

[0020] 52 Metal interconnects 54 Pores

[0021] T1 First thickness T2 Second thickness

[0022] T3 Third Thickness W1 First Width

[0023] W2 Second Width W3 Third Width Detailed Implementation

[0024] Please refer to Figures 1 to 5 , Figures 1 to 5This is a schematic diagram illustrating a method for fabricating a metal interconnect structure according to a preferred embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. The substrate 12 may contain active elements (active devices) such as metal-oxide-semiconductor (MOS) transistors, passive elements, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 14 covering it. More specifically, the substrate 12 may contain MOS transistor elements such as planar or non-planar (e.g., fin structure transistors), wherein the MOS transistor may include a metal gate and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, etc. The interlayer dielectric layer may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistor. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well-known technologies in this field, they will not be described in detail here.

[0025] Then, a metal interconnect structure is sequentially formed on the interlayer dielectric layer 14 to electrically connect the aforementioned contact plug. Preferably, the metal interconnect structure includes a selective stop layer (not shown) disposed on the interlayer dielectric layer 14, a first intermetallic dielectric layer 16, and at least one metal interconnect 18 embedded within the first intermetallic dielectric layer 16. Preferably, the upper surface of each metal interconnect 18 is flush with the upper surface of the first intermetallic dielectric layer 16. It should be noted that although this embodiment only uses a single metal interconnect 18 formed within the first intermetallic dielectric layer 16 as an example, the number of metal interconnects 18 is not limited to this and can be adjusted according to manufacturing process requirements.

[0026] Secondly, while the metal interconnects 18 in the metal interconnect structure are preferably composed of a single trench conductor, they are not limited thereto. According to other embodiments of the present invention, each metal interconnect 18 may include a trench conductor, a via conductor, or a combination thereof. Each metal interconnect 18 is preferably embedded in the first intermetallic dielectric layer 16 and / or the stop layer using a dual damascene fabrication process and is electrically connected to each other. Since the dual damascene fabrication process is well known in the art, it will not be described in detail here. Structurally, the metal interconnect 18 preferably includes a barrier layer 20, a pad layer 22 disposed on the barrier layer 20, and a metal layer 24 disposed on the pad layer 22. The barrier layer 20 and the pad layer 22 are preferably U-shaped, and their upper surfaces are preferably flush with the upper surface of the first intermetallic dielectric layer 16. In terms of materials, the barrier layer 20 preferably contains tantalum nitride (TaN), the pad layer 22 preferably contains cobalt (Co), the metal layer 24 preferably contains copper, the first intermetallic dielectric layer 16 preferably contains silicon oxide, and the stop layer contains silicon nitride, but none of them are limited to these.

[0027] Next, a masking layer 26 is formed and covers the surface of the first intermetallic dielectric layer 16 and the metal interconnect 18.

[0028] Then, a photolithography and etching process is performed to remove part of the masking layer 26 located on the first intermetallic dielectric layer 16, so that the remaining masking layer 26 covers the surface of the metal interconnect 18, and the edges of the masking layer 26 are preferably flush with the edges of the metal interconnect 18, exposing the upper surfaces of the first intermetallic dielectric layer 16 on both sides again. In this embodiment, the masking layer 26 preferably contains the same material as the padding layer 22 in the metal interconnect 18, for example, both contain conductive or metallic materials composed of cobalt. Subsequently, a stop layer 28 and a second intermetallic dielectric layer 30 are sequentially formed on the masking layer 26, wherein the stop layer 28 preferably conformally covers the upper surface of the first intermetallic dielectric layer 16 and the upper surface and sidewalls of the masking layer 26, while the second intermetallic dielectric layer 30 completely covers the stop layer 28. In this embodiment, the stop layer 28 may contain a dielectric material such as silicon nitride, and the second intermetallic dielectric layer 30 and the first intermetallic dielectric layer 16 may contain the same material, such as silicon oxide.

[0029] like Figure 2As shown, a patterned mask 32 is first formed on the surface of the second intermetallic dielectric layer 30, and then a first etching process 34 is performed to sequentially remove a portion of the second intermetallic dielectric layer 30 and a portion of the stop layer 28 to form an opening 36. In this embodiment, the patterned mask 32 may comprise a single-layer structure composed of a patterned photoresist, or it may comprise a three-layer structure composed of an organic dielectric layer (ODL), a silicon-containing hard mask and an anti-reflective coating (SHB) layer, and a patterned photoresist. The step of forming the opening 36 in the patterned mask 32 can be achieved by using the patterned photoresist to remove a portion of the silicon-containing hard mask, the anti-reflective layer, and a portion of the organic dielectric layer.

[0030] Furthermore, the first etching process 34 performed in this stage preferably includes a dry etching process, which preferably uses a fluorine-containing gas, such as carbon tetrafluoride (CF4), to remove part of the second intermetallic dielectric layer 30 and part of the stop layer 28, exposing the surface of the masking layer 26 to form an opening 36. It should be noted that when removing part of the second intermetallic dielectric layer 30 to form an opening 36 and expose the top of the masking layer 26 using the first etching process 34 or the dry etching process in this stage, part of the masking layer 26 composed of cobalt may be oxidized, thereby forming a polymer 38 composed of cobalt oxide (CoO) or fluorine-containing polymer 38 deposited at the bottom of the opening 36, especially at the corner where the stop layer 28 and the masking layer 26 meet.

[0031] like Figure 3 As shown, a plasma processing fabrication process 40 is then performed to remove the polymer 38 generated during the first etching process 34 within the opening 36. More specifically, the plasma processing fabrication process 40 in this stage preferably utilizes a gas or combination of gases, such as hydrogen and / or nitrogen, to reduce the amount of polymer 38 deposited at the bottom of the opening 36, so that the thickness of the subsequent cover layer 26 is not reduced. It should be noted that, ideally, although the plasma processing fabrication process 40 in this stage preferably removes most of the polymer 38, in reality, a small amount of polymer 38 may still remain in the corner at the bottom of the opening 36 after the plasma processing fabrication process 40 is completed. In this embodiment, the nitrogen flow rate used in the plasma processing fabrication process 40 is preferably approximately 50 standard cubic centimeters per minute (sccm), and the hydrogen flow rate is approximately 100 standard cubic centimeters per minute.

[0032] Subsequently, as Figure 4 As shown, a second etching process 42 is performed to further remove the polymer 38 deposited at the bottom of the opening 36, particularly to completely remove the polymer 38 remaining at the bottom corner of the opening 36. In this embodiment, the second etching process 42 preferably includes a wet etching process, which preferably uses an etchant containing, for example, hydrogen peroxide (H2O2) to remove the polymer 38 deposited at the bottom corner of the opening 36 while rotating the substrate 12 or the semiconductor wafer. The rotational speed of the chuck used to support the substrate 12 or the semiconductor wafer during the second etching process 42 or the wet etching process is preferably between 200 and 2000 rpm, and the flow rate of the etchant, such as hydrogen peroxide, is preferably between 0.5 and 2.0 liters per minute.

[0033] It is worth noting that, in this embodiment, when removing the remaining polymer 38 using the second etching process 42, it is preferable to simultaneously remove a portion of the masking layer 26 directly below the opening 36 without exposing the metal interconnect 18 below the masking layer 26, so that the upper surface of the remaining masking layer 26 directly below the opening 36 is slightly lower than the upper surfaces of the masking layers 26 on both sides. Furthermore, it should be noted that, in this embodiment, when removing the portion of the masking layer 26 directly below the opening 36 using the second etching process 42, a small portion of the masking layer 26 on both sides of the opening 36 may also be removed due to a diffusion effect, forming a stepped portion 44.

[0034] In detail, after the second etching process 42 is completed in this embodiment, the remaining masking layer 26 covering the surface of the metal interconnect 18 preferably includes three thicknesses. The masking layer 26 directly below the opening 36 includes a first thickness T1. The portion of the masking layer 26 on both sides of the first thickness T1 that is affected by the diffusion of the aforementioned etchant includes a second thickness T2. The masking layer 26 on both sides of the second thickness T2 up to the edge of the metal interconnect 18 includes a third thickness T3. The first thickness T1 is preferably less than the second thickness T2, and the second thickness T2 is preferably less than the third thickness T3.

[0035] In this embodiment, the first thickness T1 is preferably between 8 and 25 angstroms, the second thickness T2 is preferably between 15 and 50 angstroms, and the third thickness T3 is preferably between 20 and 100 angstroms. Furthermore, in terms of width range, the first thickness T1 preferably includes a first width W1 from left to right, the second thickness T2 preferably includes a second width W2 from left to right, and the third thickness T3 preferably includes a third width W3 from left to right or the entire interconnect width 18 of the metal. The first width W1 is preferably about 34 nanometers, the second width W2 is preferably about 68 nanometers, and the third width W3 is preferably greater than 100 nanometers.

[0036] It should be noted that this embodiment is better than the one described above. Figure 2 No masking layer 26 is removed during the first etching process 34 or the dry etching process until... Figure 4 The second etching process 42 removes part of the masking layer 26, but it is not limited to this. According to one embodiment of the present invention, when the first etching process 34 removes part of the second intermetallic dielectric layer 30 and part of the stop layer 28 to form the opening 36, part of the masking layer 26 can be removed simultaneously, so that the masking layer 26 directly below the opening 36 is slightly lower than the masking layers 26 on both sides to form a stepped portion 44. Then the process is carried out sequentially. Figure 3 Plasma processing manufacturing process 40 and Figure 4 The second etching process 42 or wet etching process is used to form such as Figure 4 The three thicknesses of the cover layer 26 shown are also within the scope of this invention.

[0037] like Figure 5 As shown, the patterned mask 32 is then removed, and a barrier layer 46 is sequentially formed within the opening 36, a pad layer 48 is formed on the barrier layer 46, and a metal layer 50 is formed on the pad layer 48 to fill the opening 36. Next, a planarization process is performed, for example, using chemical mechanical polishing (CMP) to remove portions of the metal layer 50, the pad layer 48, and the barrier layer 46 to form another metal interconnect 52 or, more specifically, a contact hole conductor. Similar to the composition of the metal interconnect 18 or trench conductor below, the barrier layer 46 preferably comprises tantalum nitride (TaN), the pad layer 48 preferably comprises cobalt (Co), and the metal layer 50 preferably comprises copper, but these are not limited to these components. This completes the fabrication of a metal interconnect structure according to an embodiment of the present invention.

[0038] Please refer to again Figure 5 , Figure 5 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 5 As shown, the semiconductor device mainly includes a metal interconnect 18 disposed within a first intermetallic dielectric layer 16, another metal interconnect 52 disposed above the metal interconnect 18, a cover layer 26 disposed on the surface of the metal interconnect 18 and in direct contact with the metal interconnects 18 and 52, a stop layer 28 covering and contacting the upper surfaces of the first intermetallic dielectric layer 16 and the cover layer 26, and a second intermetallic dielectric layer 30 disposed on the stop layer 28 and surrounding the metal interconnect 52.

[0039] In detail, the cover layer 26 includes a first thickness T1 located between the metal interconnects 18 and 52, a second thickness T2 located on both sides of the first thickness T2, and a third thickness T3 located on both sides of the second thickness T2. Preferably, the first thickness T1 is less than the second thickness T2, and the second thickness T2 is preferably less than the third thickness T3. In terms of materials, the cover layer 26 and the padding layers 22 and 48 in the metal interconnects 18 and 52 preferably contain the same material, for example, all three contain a conductive or metallic material composed of cobalt. The stop layer 28 may be composed of a dielectric material such as silicon nitride or silicon carbide nitride.

[0040] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a metal interconnect structure according to an embodiment of the present invention. Figure 6 As shown, the present invention is Figure 4 Remove part of the masking layer 26 to Figure 5 When the barrier layer 46, the padding layer 48, and the metal layer 50 are filled to form the metal interconnect 52, the manufacturing process parameters can be adjusted according to the manufacturing process requirements to form pores 54 in the cover layer 26 on both sides of the metal interconnect 52. Structurally, each pore 54 is preferably surrounded by the cover layer 26, the barrier layer 46, and the stop layer 28. It should also be noted that although the upper surface of the pore 54 in this embodiment is approximately flush with the upper surface of the cover layer 26, it is not limited to this. According to other embodiments of the present invention, the upper surface of the pore 54 may be slightly higher or slightly lower than the upper surface of the cover layer 26. These variations are all within the scope of the present invention.

[0041] Generally, in existing metal interconnect fabrication processes, when etching is used to remove the inter-metal dielectric layer to form the metal interconnect opening, the cobalt-based masking layer at the top of the metal interconnect is often removed due to the lack of precise control during the etching process. This results in a discontinuous masking layer, causing the subsequently filled conductive material to directly contact the underlying metal interconnect. This discontinuous masking layer can affect the reliability of the entire batch of components and cause electromigration. To solve this problem, the present invention preferably first performs a first etching process or dry etching process to remove part of the inter-metal dielectric layer to form an opening. Then, a plasma treatment process is used to remove most of the polymer accumulated at the bottom corner of the opening. Next, a second etching process or wet etching process is performed, while simultaneously adjusting the etching speed and the flow rate of the etchant to remove the remaining polymer without etching through the masking layer. Finally, conductive material is filled into the opening to directly contact the masking layer and form the metal interconnect. According to a preferred embodiment of the present invention, the remaining masking layer covering the surface of the underlying metal interconnect is preferably structurally formed with varying thicknesses during the etching process, or, from another perspective, produced with one or more steps, but overall remains a continuous masking layer covering the surface of the metal interconnect. This improves the overall reliability of the component and reduces the probability of component failure.

[0042] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A metal interconnect structure, characterized in that, Include: A first metal interconnect is disposed within an inter-metal dielectric layer on a substrate, wherein the upper surface of the first metal interconnect is flush with the upper surface of the inter-metal dielectric layer. A shielding layer is disposed on the first metal interconnect, wherein the shielding layer comprises a conductive material; A stop layer is provided on the cover layer; The second metal interconnect is disposed on the first metal interconnect and passes through the stop layer and part of the cover layer. as well as The pores are located between the stop layer and the cover layer on both sides of the second metal interconnect.

2. The metal interconnect structure as claimed in claim 1, wherein the covering layer includes a first thickness between the first metal interconnect and the second metal interconnect, and a second thickness adjacent to both sides of the first thickness.

3. The metal interconnect structure as claimed in claim 2, wherein the second thickness is greater than the first thickness.

4. The metal interconnect structure as claimed in claim 2, wherein the covering layer includes a third thickness adjacent to both sides of the second thickness.

5. The metal interconnect structure as claimed in claim 4, wherein the third thickness is greater than the second thickness.

6. The metal interconnect structure as claimed in claim 1, wherein the second metal interconnect comprises: Barrier layer, in contact with the covering layer; A padding layer is disposed on the barrier layer; and A metal layer is disposed on the padding layer.

7. The metal interconnect structure as claimed in claim 6, wherein the barrier layer and the padding layer are U-shaped.

8. The metal interconnect structure of claim 6, wherein the covering layer and the padding layer comprise the same material.

9. The metal interconnect structure of claim 6, wherein the cover layer and the pad layer comprise cobalt.

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