Level shifter, method of manufacturing the same, and semiconductor device

Abstract

The application provides a level shifter, a preparation method thereof and a semiconductor device. A buried doped region of a first doped type is arranged on one side of an isolation doped region close to a field effect transistor, so as to increase the ion concentration of the first doped type in the side region of the isolation doped region, and to facilitate the enhancement of the lateral depletion degree of the isolation doped region and the longitudinal depletion degree of the substrate, and to improve the withstand voltage performance of the device. Furthermore, the buried doped region is arranged, so that the breakdown point of the device can be transferred from the PN junction position corresponding to the isolation doped region to the inside of the substrate below the drain region, and the level shifter as a whole has a high withstand voltage, and the isolation structure also has a high withstand voltage, and the leakage problem between the high-voltage side circuit and the drain region of the field effect transistor is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a level shifter and its fabrication method. Background Technology

[0002] High-voltage power gate driver chips are typically implemented using compatible processes for both high-voltage and low-voltage circuits. A level shifter converts control signals from the low-voltage side circuit into control signals for the high-voltage side circuit, which are then transmitted to control the high-voltage side circuit, thus achieving level conversion between the two circuits.

[0003] An isolation structure is set around the periphery of the level shifter to isolate the high-voltage side circuit and the level shifter, preventing leakage current from affecting the functionality of the devices. Commonly used isolation structures include: dielectric isolation (using insulating media such as oxides to isolate the device structure within the substrate), self-isolation (relying on the depletion layer withstand voltage of the device itself to achieve isolation between devices), and junction isolation (using the principle of PN reverse bias for isolation). When setting up the isolation structure, it is usually necessary to consider both the withstand voltage performance of the level shifter and the sufficient withstand voltage performance of the isolation structure itself to ensure the isolation performance between the high-voltage side circuit and the level shifter, avoiding leakage current problems.

[0004] Therefore, how to improve the breakdown voltage of the level shifter and ensure the withstand voltage performance of the isolation structure has always been an important research topic in the field. Summary of the Invention

[0005] The purpose of this invention is to provide a level shifter and its manufacturing method, which can effectively improve the breakdown voltage of the level shifter and optimize the withstand voltage performance of the device.

[0006] To this end, the present invention provides a level shifter, comprising: a substrate having a doped layer of a first doping type; a field-effect transistor including a drain region of the first doping type, a source region of the first doping type, and a gate structure, the gate structure being formed on the substrate and located between the source region and the drain region; an isolation structure located around the field-effect transistor, the isolation structure including at least one isolation doped region of a second doping type formed within the doped layer; and at least one buried doped region of the first doping type, buried within the doped layer and maintaining a predetermined distance from the top surface of the doped layer, and formed on at least one side of the isolation doped region.

[0007] Optionally, the buried doped region is disposed on the side of the isolation doped region closer to the field-effect transistor; and / or, the buried doped region is disposed on the side of the isolation doped region away from the field-effect transistor.

[0008] Optionally, the buried doped region is disposed between the drain region and the isolation doped region in a direction parallel to the substrate surface.

[0009] Optionally, the substrate includes a second-doped substrate and a first-doped epitaxial layer disposed sequentially from bottom to top, the field-effect transistor is formed on the epitaxial layer, the isolation structure penetrates the epitaxial layer and reaches the substrate, and the buried doped region is formed within the epitaxial layer.

[0010] Optionally, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked from bottom to top, wherein the buried doped region is formed on the top surface region of the first epitaxial layer and extends upward to the second epitaxial layer.

[0011] Optionally, the isolation structure includes at least two isolation doped regions arranged sequentially from bottom to top and interconnected with each other, wherein the bottom isolation doped region extends upward from the substrate into the epitaxial layer, and the buried doped region faces the boundary position of the two adjacent isolation doped regions in a direction parallel to the substrate surface.

[0012] Optionally, the isolation doped region in the isolation structure includes a first buried region of a second doping type, a first deep well region of a second doping type, and a first shallow well region of a second doping type, which are arranged sequentially from bottom to top and connected to each other. The buried doped region is directly opposite the boundary position of the first buried region and the first deep well region in a direction parallel to the substrate surface.

[0013] Optionally, the level shifter further includes a second shallow well region of a second doped type, a second deep well region of a second doped type, and a second buried region of a second doped type, which are sequentially connected from bottom to top and located on the side of the gate structure near the source region, with the source region formed within the second shallow well region. Specifically, the first shallow well region extends from the outside of the drain region, surrounding the field-effect transistor, to the second shallow well region and connects to it; the first deep well region extends from the outside of the drain region, surrounding the field-effect transistor, to the second deep well region and connects to it; and the first buried region extends from the outside of the drain region, surrounding the field-effect transistor, to the second buried region and connects to it.

[0014] Optionally, the level shifter further includes a plurality of third buried regions arranged side by side, the plurality of third buried regions being arranged between the source region and the drain region, and the third buried regions extending upward from the substrate into the epitaxial layer.

[0015] Optionally, the level shifter further includes a third well region of a first doping type, the third well region being located on the side of the gate structure near the drain region, the drain region being formed within the third well region; and a buried doping region being disposed between the drain region and the isolation doping region, the buried doping region at least partially overlapping the third well region on the side of the third well region near the isolation doping region.

[0016] Optionally, N buried doped regions are provided on the same side of the isolation doped region, and the N buried doped regions are arranged sequentially from bottom to top; and the doped layer includes N+1 epitaxial layers, and the buried doped regions are formed at the boundary region of two adjacent epitaxial layers.

[0017] Optionally, the dopant ions in the buried doped region include antimony ions.

[0018] The present invention also provides a method for fabricating a level shifter, comprising: forming a field-effect transistor on a substrate, the field-effect transistor including a drain region of a first doped type, a source region of a first doped type, and a gate structure, the drain region and the source region being formed within the substrate, and the gate structure being formed on the substrate and located between the source region and the drain region. The substrate has a doped layer of the first doped type. The fabrication method further comprises: forming an isolation structure around the field-effect transistor, the isolation structure including forming at least one isolation doped region of a second doped type within the doped layer, and further forming at least one buried doped region of the first doped type on at least one side of the isolation doped region.

[0019] Optionally, the substrate includes a second-doped substrate and a first-doped epitaxial layer disposed sequentially from bottom to top. The method for fabricating the isolation structure includes: performing a second-doped ion implantation process on the substrate before forming the epitaxial layer to form a first buried region of the second-doped type in the substrate; and, during the epitaxial process to form the epitaxial layer on the substrate, ions from the first buried region diffuse upwards into the epitaxial layer, and the epitaxial layer is subjected to two second-doped ion implantation processes sequentially to form a first deep well region and a first shallow well region sequentially, wherein the bottom of the first deep well region is connected to the first buried region, and the bottom of the first shallow well region is connected to the first deep well region.

[0020] Optionally, when fabricating the first buried region of the isolation structure, a second buried region is also formed on the low-voltage side of the transistor region, the first buried region extending from the high-voltage side of the transistor region to the low-voltage side of the transistor region to connect the second buried region; when fabricating the first deep well region of the isolation structure, a second deep well region is also formed on the low-voltage side of the transistor region, the first deep well region extending from the high-voltage side of the transistor region to the low-voltage side of the transistor region to connect the second deep well region; and when fabricating the first shallow well region of the isolation structure, a second shallow well region is also formed on the low-voltage side of the transistor region, the first shallow well region extending from the high-voltage side of the transistor region to the low-voltage side of the transistor region to connect the second shallow well region.

[0021] Optionally, the method for preparing the buried doped region includes: forming a first epitaxial layer and performing an ion implantation process of a first doping type on the first epitaxial layer to form a buried doped region; and epitaxially forming a second epitaxial layer on the first epitaxial layer to bury the buried doped region in the interface region between the first epitaxial layer and the second epitaxial layer.

[0022] The present invention also provides a semiconductor device including the level shifter described above.

[0023] In the level shifter provided by this invention, by setting a buried doped region of the first doping type on one side of the isolation doped region, the ion concentration of the first doping type in the side region of the isolation doped region is increased. This is beneficial to enhancing the lateral depletion degree of the isolation doped region and the longitudinal depletion degree of the substrate, thereby improving the overall breakdown voltage performance of the level shifter. In particular, when the buried doped region is set on the side of the isolation doped region close to the field-effect transistor, it is also beneficial to increase the longitudinal depletion degree of the underlying substrate, further improving the overall breakdown voltage of the device. In addition, by setting the buried doped region, the breakdown point of the device can be transferred from the PN junction position corresponding to the isolation doped region to the interior of the substrate (e.g., the substrate below the drain region), ensuring that the isolation structure has a high breakdown voltage (e.g., up to 50V, which is much greater than the 15V breakdown voltage requirement), improving the isolation performance between the high-voltage side circuit and the drain region of the field-effect transistor, and greatly improving the leakage current problem between the high-voltage side circuit and the drain region.

[0024] Furthermore, in this invention, the buried doped region is placed inside the doped layer and maintained at a predetermined distance from the top surface of the doped layer. This prevents the doping concentration of the doped layer above the buried doped region from being too high, effectively improving the problem of leakage caused by premature breakdown of the isolation structure on the top surface of the doped layer, and improving the overall withstand voltage performance of the device. Attached Figure Description

[0025] Figure 1This is a schematic diagram of the structure of a semiconductor device with a level shifter according to an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram illustrating the interconnect structure of a semiconductor device with a level shifter according to an embodiment of the present invention.

[0027] Figure 3 This is a simulation comparison of the depletion line when testing the breakdown voltage of a level shifter with and without a buried doped region.

[0028] Figure 4 This is a comparison chart of the simulated breakdown voltages of a level shifter with and without a buried doped region when the drain terminal and the high-voltage side circuit are short-circuited.

[0029] Figure 5 This is a simulation diagram of the breakdown voltage between the high-voltage side circuit and the drain terminal of a level shifter with a buried doped region in operation.

[0030] Figures 6-15 This is a schematic diagram of the semiconductor device with a level shifter in an embodiment of the present invention during its fabrication process.

[0031] The reference numerals in the attached figures are as follows:

[0032] 100-substrate;

[0033] 110P-substrate;

[0034] 120N - Epitaxial layer;

[0035] 121N - First epitaxial layer;

[0036] 122N - Second epitaxial layer;

[0037] 200- Field-Effect Transistor;

[0038] 200S-Source Region;

[0039] 200D - Leakage Area;

[0040] 200G gate structure;

[0041] 200B - First Contact Area;

[0042] 210 - Second isolation oxide layer;

[0043] 220-field oxide layer;

[0044] 300 - Isolation structure;

[0045] 310 - First isolation oxide layer;

[0046] 400N - Buried doped region;

[0047] 510 / 520 / 530 / 540 / 550 / 560 / 570 - Mask layer;

[0048] 610 - Interlayer dielectric layer;

[0049] 620 - Conductive plug;

[0050] 630 - Electrode conductive layer;

[0051] PBL1 - First Burial Zone;

[0052] PBL2 - Second Burial Zone;

[0053] PBL3 - Third Burial Zone;

[0054] NBL - Fourth Burial Zone;

[0055] DPW1 - First deep well region;

[0056] DPW2 - Second deep well region;

[0057] PW1 - First shallow well region;

[0058] PW2 - Second shallow well region;

[0059] NW1 - Third well region;

[0060] NW2 - Fourth well region. Detailed Implementation

[0061] The level shifter and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. It should be understood that relative terms such as "above," "below," "top," "bottom," and "upper" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described, for example, as being "above" another element will now be below that element.

[0062] Figure 1 This is a schematic diagram of the level shifting device in one embodiment of the present invention, as shown below. Figure 1 As shown, the level shifting device includes: a substrate 100, a field-effect transistor 200 formed on the substrate 100, and an isolation structure 300 formed on the outside of the field-effect transistor 200.

[0063] The substrate 100 has a doped layer of a first doping type. In a specific example, the substrate 100 includes a substrate 110P and an epitaxial layer 120N formed on the substrate 110P. Specifically, the substrate 110P is a substrate of a second doping type, and the epitaxial layer 120N is an epitaxial layer of the first doping type. Therefore, the epitaxial layer 120N constitutes the first doped layer of the substrate 100. In this embodiment, the epitaxial layer 120N further includes a first epitaxial layer 121N and a second epitaxial layer 122N. The first epitaxial layer 121N and the second epitaxial layer 122N more precisely define the depth of the buried doped region 400N within the epitaxial layer 120N, which will be explained in detail later.

[0064] It should be noted that the first doping type and the second doping type are opposite doping types. For example, if the first doping type is N-type, then the second doping type is P-type; or, if the first doping type is P-type, then the second doping type is N-type. In this embodiment, the explanation will be based on the example of the first doping type being N-type and the second doping type being P-type.

[0065] Furthermore, the field-effect transistor 200 specifically includes a drain region 200D of a first doped type, a source region 200S of a first doped type, and a gate structure 200G. The drain region 200D and the source region 200S are specifically formed within a first doped type doped layer (i.e., epitaxial layer 120N) of the substrate 100, and the gate structure 200G is formed on the substrate 100 and located between the source region 200S and the drain region 200D. In this embodiment, the field-effect transistor 200 is, for example, an LDMOS transistor, wherein the epitaxial layer 120N located within the transistor region can be used to constitute the drift region of the LDMOS transistor.

[0066] Continue to refer to Figure 1 As shown, an isolation structure 300 is provided on the outside of the field-effect transistor 200. The isolation structure 300 is used to isolate the high-voltage side circuit and the field-effect transistor 200 to prevent leakage current from affecting the function between the devices. In one example, the isolation structure 300 can surround the transistor region from the high-voltage side (i.e., the side near the drain region 200D) to the low-voltage side (i.e., the side near the source region 200S) of the transistor region.

[0067] The isolation structure 300 includes at least one isolation doped region of a second doping type. The second doped isolation doped region (e.g., a P-type isolation region) is specifically formed within the doped layer of the first doping type of the substrate 100 to achieve device isolation using PN junction isolation technology. By applying a PN reverse bias to the PN junction isolation, the PN junction isolation structure can undergo depletion layer expansion to improve the device's breakdown resistance.

[0068] In a specific example, the isolation structure 300 is formed on the epitaxial layer 120N and extends through the epitaxial layer 120N to the substrate 110P. Further, the isolation structure 300 includes at least two isolation doped regions arranged sequentially from bottom to top and interconnected, thereby penetrating the epitaxial layer 120N in the height direction. The bottommost isolation doped region extends upwards from the substrate 110P into the epitaxial layer 120N. In this embodiment, the isolation structure 300 includes three isolation doped regions, namely, a first buried region PBL1 of a second doping type, a first deep well region DPW1 of a second doping type, and a first shallow well region PW1 of a second doping type, arranged sequentially from bottom to top and interconnected. Here, the first shallow well region PW1 is a well region with a doping depth shallower than the first deep well region DPW1, and the first deep well region DPW1 is a well region with a doping depth deeper than the first shallow well region PW1. Specifically, the first shallow well region PW1 extends inward from the top surface of the substrate 100 and partially overlaps with the first deep well region DPW1 below it in the height direction. The first deep well region DPW1 also partially overlaps with the first buried region PBL1 below it in the height direction. The first buried region PBL1 spans the interface between the epitaxial layer 120N and the substrate 110P, so that the first shallow well region PW1, the first deep well region DPW1, and the first buried region PBL1 are connected vertically and penetrate the epitaxial layer 120N.

[0069] It should be understood that the isolation structure 300 in this embodiment includes three isolation doped regions, while in other examples, the isolation structure 300 may include two or more isolation doped regions, as long as the isolation doped regions in the isolation structure 300 can be interconnected and penetrate the epitaxial layer 120N.

[0070] Furthermore, the isolation structure 300 may further include a first isolation oxide layer 310, which is formed on the top surface of the substrate 100 and located above the isolation doped region. The first isolation oxide layer 310 may be formed, for example, using a local oxidation of silicon (LOCOS) process. When the substrate 100 is a silicon substrate, the field oxide layer 310 may be a silicon oxide layer.

[0071] In this embodiment, the substrate 100 further includes a buried doped region 400N of a first doping type. The buried doped region 400N is specifically formed on at least one side of the isolation doped region. For example, the buried doped region 400N can be formed on the side of the isolation doped region closer to the field-effect transistor 200; or, it can be formed on the side of the isolation doped region farther from the field-effect transistor; or, it can be formed on both sides of the isolation doped region. By providing a buried doped region 400N of the first doping type, the concentration of the first doped ion in the side region of the isolation doped region can be effectively increased, which is beneficial for enhancing the lateral depletion degree of the isolation doped region and the longitudinal depletion degree of the substrate, thereby improving the breakdown voltage performance of the device. The buried doped region 400N is formed within the epitaxial layer 120N, where the epitaxial layer 120N is, for example, N-type doped, and the buried doped region 400N is correspondingly N-type doped, thus increasing the concentration of N-type doped ions in the side region of the isolation doped region. The N-type dopant ions in the buried doping region 400N may include antimony (Sb) dopant, or may be other N-type dopant ions, such as phosphorus ions, arsenic ions, etc.

[0072] In a specific example, the buried doped region 400N can maintain a certain distance from the isolation doped region in a horizontal direction parallel to the substrate surface. The lateral spacing between the buried doped region 400N and the isolation doped region can be adjusted according to their doping concentrations, thereby controlling the depletion degree of the isolation doped region and facilitating the regulation of its isolation effect.

[0073] Furthermore, the buried doped region 400N can be positioned horizontally to face the boundary between two adjacent isolation doped regions. For example, the buried doped region 400 can have a portion in the horizontal direction facing the boundary between the first deep well region DPW1 and the first buried region PBL1. Specifically, the first buried region PBL1 and the first deep well region DPW1 are interconnected through ion diffusion. Therefore, the ion concentration at the boundary between the first deep well region DPW1 and the first buried region PBL1 is typically low, which effectively increases the lateral depletion of the isolation doped region.

[0074] In this embodiment, the buried doped region 400N can be buried within the doped layer (i.e., the epitaxial layer 120N) and maintained at a predetermined distance from the top surface of the epitaxial layer 120N. This prevents the doping concentration of the epitaxial layer above the buried doped region 400N from becoming too high. It should be noted that if the doping concentration of the epitaxial layer above the buried doped region 400N is too high (e.g., the N-type doping concentration in the top surface region of the epitaxial layer 120N is too high), premature breakdown on the surface of the epitaxial layer 120N can easily occur, leading to leakage and reducing the overall breakdown voltage performance of the device. In this embodiment, maintaining a predetermined distance between the buried doped region 400N and the top surface of the epitaxial layer 120N prevents the doping concentration of the epitaxial layer 120N above the buried doped region 400N from becoming too high, effectively improving the problem of premature breakdown of the isolation structure on the top surface of the doped layer leading to leakage, and improving the overall breakdown voltage performance of the device.

[0075] Furthermore, the buried doped region 400N and the drain region 200D can be spaced apart to avoid the buried doped region 400N affecting the drain region 200D and to prevent excessively high doping concentration at the bottom of the drain region 200D from causing a decrease in the device's breakdown voltage. In one example, the spacing between the buried doped region 400N and the drain region 200D can be greater than or equal to 2 μm.

[0076] In an optional scheme, the spacing between the buried doped region 400N and the drain region 200D in the height direction and the spacing between the buried doped region 400N and the top surface of the epitaxial layer 120N can be adjusted by controlling the thickness and doping concentration of the second epitaxial layer 122N and the first epitaxial layer 121N. In addition, the spacing between the buried doped region 400N and the substrate 110P can also be adjusted to regulate the depletion region width of the longitudinal PN junction between the drain region 200D and the substrate 110P.

[0077] As described above, the epitaxial layer 120N may include a first epitaxial layer 121N and a second epitaxial layer 122N to precisely control the depth of the buried doped region 400N. Specifically, the buried doped region 400N is formed in the interface region between the first epitaxial layer 121N and the second epitaxial layer 122N. Therefore, by controlling the thickness of the first epitaxial layer 121N, the distance from the buried doped region 400N to the substrate 110P can be adjusted. For example, the thickness of the first epitaxial layer 121N can be controlled between 2μm and 4μm. And, by adjusting the thickness of the second epitaxial layer 122N, the distance from the buried doped region 400N to the top surface of the substrate (i.e., the top surface of the epitaxial layer 120N) can be adjusted. For example, the thickness of the second epitaxial layer 122N can be controlled between 3μm and 5μm.

[0078] In a specific example, the buried doped region 400N is formed within the epitaxial layer 120N and disposed above the substrate 110P with a gap. That is, the buried doped region 400N is disposed with a gap from the substrate 110P in the height direction. At this time, the second doped substrate 110P, the epitaxial layer 120N and the buried doped region 400N can form a longitudinally gradient junction, which is beneficial to expanding the depletion width of the substrate 110P and further improving the breakdown performance of the device.

[0079] Furthermore, the ion doping concentration of the substrate 110P is lower than that of the first shallow well region PW1. Therefore, the distance between the buried doped region 400N and the substrate 110P in the height direction can be greater than the distance between the buried doped region 400N and the isolation doped region in the horizontal direction. By increasing the distance between the buried doped region 400N and the substrate 110P in the height direction, the depletion width of the substrate 110P can be expanded to a greater extent.

[0080] In a further embodiment, a second shallow well region PW2 of a second doped type is formed in the substrate 100. The second shallow well region PW2 extends downward from the top surface of the substrate 100 into the substrate interior, and is formed on the low-voltage side of the transistor region (i.e., on the side of the gate structure 200G near the source region 200S). The source region 200S can be formed within the second shallow well region PW2. Furthermore, the portion of the gate structure 200G near the source region 200S also covers the second shallow well region PW2. When a turn-on voltage is applied to the gate structure 200G of the field-effect transistor 200, a conductive channel will be inverted within the second shallow well region PW2 covered by the gate structure 200G to achieve current flow between the source region 200S, the conductive channel, the drift region, and the drain region 200D. That is, the second well region PW2 is used to constitute the body region of the channel inversion of the field-effect transistor 200.

[0081] Within the second shallow well region PW2, a first contact region 200B (specifically a bulk contact region) of a second doping type is formed. The ion doping concentration of the first contact region 200B is greater than that of the second shallow well region PW2, so as to electrically lead out the second shallow well region PW2 through the first contact region 200B. In this embodiment, the first contact region 200B is formed on the side of the source region 200S away from the gate structure 200G, and a second isolation oxide layer 210 is also provided between the first contact region 200B and the source region 200S.

[0082] In a specific example, the second shallow well region PW2 can have the same doping depth and doping concentration as the first shallow well region PW1 in the isolation structure 300. Specifically, the second shallow well region PW2 and the first shallow well region PW1 can be formed simultaneously in the same ion implantation process, thereby making the second shallow well region PW2 and the first shallow well region PW1 have the same parameters. In particular, the first shallow well region PW1 of the isolation structure 300 can be horizontally extended from the outside of the drain region 200D around the field-effect transistor 200 to the low-voltage side of the transistor region, such that the first shallow well region PW1 is horizontally connected to the second shallow well region PW2, thereby making the interconnected first shallow well region PW1 and second shallow well region PW2 surround the field-effect transistor 200.

[0083] In this embodiment, a second deep well region DPW2 of a second doped type and a second buried region PBL2 of a second doped type are also formed within the substrate 100. The second deep well region DPW2 and the second buried region PBL2 are sequentially formed below the second shallow well region PW2 and are interconnected. The second deep well region DPW2 can have the same doping depth and doping concentration as the first deep well region DPW1 within the isolation structure 300, and the second buried region PBL2 can have the same doping depth and doping concentration as the first buried region PBL1 within the isolation structure 300. Specifically, the second deep well region DPW2 and the first deep well region DPW1 can be formed simultaneously in the same ion implantation process, and the second buried region PBL2 and the first buried region PBL1 can also be formed simultaneously in the same ion implantation process. That is, the second shallow well region PW2 extends inward from the top surface of the substrate 100 and partially overlaps with the second deep well region DPW2 below it in the height direction. The second deep well region DPW2 also partially overlaps with the second buried region PBL2 below it in the height direction. The second buried region PBL2 extends downward from the epitaxial layer 120N to the substrate 110P, so that the second shallow well region PW2, the second deep well region DPW2, and the second buried region PBL2 are connected vertically and penetrate the epitaxial layer 120N.

[0084] Similarly, the first buried region PBL1 and the first deep well region DPW1 in the isolation structure 300 can both extend horizontally from the outside of the drain region 200D around the field-effect transistor 200 to the low-voltage side of the transistor region (i.e., the side near the source region 200S), such that the first deep well region DPW1 is connected to the second deep well region DPW2 in the horizontal direction, and the first buried region PBL1 is connected to the second buried region PBL2 in the horizontal direction, thereby making the interconnected first deep well region DPW1 and second deep well region DPW2, and the interconnected first buried region PBL1 and second buried region PBL2 all surround the field-effect transistor 200.

[0085] It can be considered that on the low-voltage side of the transistor region (i.e., the side closer to the source region 200S), the vertically connected second shallow well region PW2, second deep well region DPW2, and second buried region PBL2 also serve as isolation, horizontally connected to the isolation structure 300 to isolate the field-effect transistor 200. That is, the first shallow well region PW1, first deep well region DPW1, and first buried region PBL1 within the isolation structure 300 are connected one-to-one to the second shallow well region PW2, second deep well region DPW2, and second buried region PBL2, thereby forming an isolation ring surrounding the field-effect transistor 200.

[0086] In other words, the isolation doped region of the isolation structure 300 in this embodiment can be adjusted according to the doping situation on the low-voltage side. For example, on the low-voltage side (i.e., the side near the source region 200S), the depth of the second shallow well region PW2 designed to meet the performance requirements of the field-effect transistor 200 is relatively small. In this case, a second deep well region DPW2 can be additionally provided so that the upper and lower connected second shallow well region PW2, second deep well region DPW2 and second buried region PBL2 can reach the substrate 110P to achieve isolation. At this time, the isolation structure 300 can be correspondingly provided with the first shallow well region PW1, the first deep well region DPW1 and the first buried region PBL1. Conversely, when the depth of the designed second shallow well region PW2 is relatively large and can be connected to the lower second buried region PBL2, the second deep well region DPW2 can be omitted. At this time, the isolation structure 300 can be correspondingly omitted with the first deep well region DPW1, and only the first shallow well region PW1 and the first buried region PBL1 are provided.

[0087] Continue to refer to Figure 1 As shown, a third well region NW1 of the first doping type is also formed within the substrate 100. The third well region NW1 is located on the high-voltage side of the transistor region (i.e., on the side of the gate structure 200G near the drain region 200D), and the drain region 200D is formed within the third well region NW1. The ion doping concentration of the third well region NW1 can be between the ion doping concentration of the drain region 200D and the ion doping concentration of the epitaxial layer 120N, thereby utilizing the third well region NW1 to form a buffer and avoid large changes in ion doping concentration when moving directly from the drain region 200D to the epitaxial layer 120N.

[0088] In this embodiment, a buried doped region 400N is disposed between the drain region 200D and the isolation doped region. Specifically, the buried doped region 400N can be formed on the side of the third well region NW1 near the isolation doped region. Furthermore, the buried doped region 400N can partially overlap with the third well region NW1 on the side of the third well region NW1 near the isolation doped region. In this embodiment, the buried doped region 400N specifically overlaps with the third well region NW1 below the drain region 200D. This adjusts the electric field morphology below the transistor drain, effectively improving the overall breakdown voltage of the device. Furthermore, it optimizes the radius of curvature of the depletion line within the substrate 110P and the epitaxial layer 120N, ensuring the depletion line is as smooth as possible, mitigating the problem of excessively high electric fields at steep slopes in the depletion line, which can easily lead to breakdown, and further improving breakdown resistance.

[0089] It should be noted that the overlapping area of ​​the buried doped region 400N and the third well region NW1 can be adjusted according to the actual situation, as long as the depletion line can be made more gently horizontal. Furthermore, the side boundary of the buried doped region 400N near the source region 200S can be controlled to not exceed the side boundary of the third well region NW1 near the source region 200S, thereby adjusting the influence on the drain electric field of the field-effect transistor.

[0090] In an optional embodiment, a field oxide layer 220 is further formed on the surface of the substrate 100. The field oxide layer 220 is located between the second shallow well region PW2 and the drain region 200D, and the gate structure 200G further extends to cover the field oxide layer 220 to form a field plate structure. The field oxide layer 220 can be formed, for example, using a local oxidation of silicon (LOCOS) process. When the substrate 100 is a silicon substrate, the field oxide layer 220 can be a silicon oxide layer. In this embodiment, the drain region 200D is formed between the field oxide layer 220 and the first isolation oxide layer 310. Furthermore, the field oxide layer 220, the first isolation oxide layer 310, and the second isolation oxide layer 210 can be formed simultaneously in the same process step using a local oxidation of silicon (LOCOS) process.

[0091] Continue to refer to Figure 1As shown, in one example, a plurality of third buried regions PBL3 are also formed side-by-side within the substrate 100. These third buried regions PBL3 are arranged within the transistor region, specifically between the source region 200S and the drain region 200D, and more specifically below the gate structure 200G and the field oxide layer 220. Furthermore, the third buried regions PBL3 extend downwards from the epitaxial layer 120N into the substrate 110P (or alternatively, they extend upwards from the substrate 110P into the epitaxial layer 120N). By providing the third buried regions PBL3, the depletion of the drift region of the field-effect transistor 200 below the field oxide layer 220 (within the epitaxial layer 120N) is further increased. Furthermore, the arrangement of multiple small-width third buried regions PBL3 side by side (the width of the third buried region PBL3 can be smaller than that of the first buried region PBL1) can effectively prevent the concentration of second-doped ions in this region from being too high.

[0092] Furthermore, in the semiconductor device having the level shifter as described above, the semiconductor device also includes a high-voltage side circuit, which is disposed on the high-voltage side of the level shifter (i.e., the side near the drain region 200D) and located on the side of the isolation structure 300 away from the field-effect transistor 200. The high-voltage side circuit includes a fourth well region NW2 of a first doping type, and a second contact region of the first doping type is also formed within the fourth well region NW2 for achieving electrical connection with the outside. Additionally, the high-voltage side circuit also includes a fourth buried region NBL of the first doping type, which extends upward from the substrate 110P into the epitaxial layer 120N.

[0093] Furthermore, the semiconductor device may also include interconnect structures. See details. Figure 2 As shown, the interconnect structure includes: an interlayer dielectric layer 610 formed on a substrate 100, a plurality of conductive plugs 620 formed within the interlayer dielectric layer 610, and a plurality of electrode conductive layers 630 formed on the interlayer dielectric layer 610. The interlayer dielectric layer 610 covers the semiconductor devices on the substrate 100. The plurality of conductive plugs 620 include plugs electrically connected to the source region 200S of a field-effect transistor, plugs electrically connected to the drain region 200D of a field-effect transistor, plugs electrically connected to the gate structure 200G of a field-effect transistor, plugs electrically connected to the first contact region 200B within the second shallow well region PW2, and plugs electrically connected to the second contact region within the fourth well region NW2. The plurality of electrode conductive layers 630 cover the corresponding conductive plugs 620 to electrically connect the source region 200S, the drain region 200D, and the gate structure 200G to corresponding signal ports.

[0094] Specifically, during the operation of the semiconductor device, the bulk contact region (i.e., the first contact region 200B) and the source region 200S can be connected to a low-potential port, the gate structure 200G can be connected to the operating voltage (e.g., 25V), and the drain region 200D and the high-voltage side circuit (e.g., the second contact region in the fourth well region NW2) can be connected to a high-potential port (where the drain region 200D is, for example, 600V, and the high-voltage side circuit is, for example, 615V). During this process, the isolation between the drain region 200D and the high-voltage side circuit can be achieved by the isolation structure 300.

[0095] As described above, in this embodiment, by setting a buried doped region 400N (e.g., an N-type doped region), the concentration of another type of ion doping (e.g., N-type doping concentration) on the side of the isolation doped region (e.g., a P-type isolation region) can be increased, thereby increasing the lateral depletion of the isolation doped region and also increasing the longitudinal depletion width between the high-voltage side (i.e., the side near the drain region 200D) and the P-type substrate.

[0096] For details, please refer to [link / reference]. Figure 3 The exhaustion line comparison diagram shown is in Figure 3 Part (a) illustrates the device depletion line at 400N without a buried doped region. Figure 3 Part (b) illustrates the device depletion line with a 400N buried doped region, compared with... Figure 3 From the depletion lines L1 within the isolation doped regions in portions (a) and (b), it can be seen that the depletion degree (near complete depletion) within the isolation doped region with a buried doped region of 400N is higher than the depletion degree within the isolation doped region without a buried doped region of 400N; and, Figure 3 In part (b), the depletion line L2 within the substrate 110P and the depletion line L3 within the epitaxial layer 120N are much wider than Figure 3 The widths of the depletion line L2 in the substrate 110P and the depletion line L3 in the epitaxial layer 120N in part (a) are such that the longitudinal depletion degree of the substrate 110P and the lateral depletion degree of the isolation doped region when the buried doped region 400N is provided are much greater than the longitudinal depletion degree of the substrate 110P and the lateral depletion degree of the isolation doped region when the buried doped region 400N is not provided.

[0097] Continue to refer to Figure 3The depletion line L3 in the epitaxial layer 120N shown in part (b) is made more horizontal by adjusting the overlap area between the buried doped region 400N and the third well region NW1, so that the depletion line L2 in the substrate 110P and the depletion line L3 in the epitaxial layer 120N can be more gently horizontal. The curvature radius of the depletion line L2 and the depletion line L3 is optimized to ensure that the bending degree of the depletion line L2 and the depletion line L3 is as smooth as possible, and to alleviate the problem that the depletion line L2 and the depletion line L3 are prone to breakdown due to steep slopes.

[0098] Furthermore, simulations reveal that without the buried doped region 400N, the breakdown point of the device is concentrated on the PN junction between the drain and the isolation doped region. However, with the buried doped region 400N, the breakdown point shifts to between the drain and the substrate 110P, effectively improving the breakdown voltage BV_D at the drain and the breakdown voltage BV_H between the high-voltage side circuit and the drain.

[0099] Refer to the simulation results shown in Figure 4, which compares the breakdown voltage BV_D of the device when the drain and high-voltage side circuits are shorted with and without the buried doped region 400N (i.e., a comparison of the overall withstand voltage performance of the potentiometer). Figure 4 As shown, the breakdown voltage BV_D1 without the buried doped region 400N is only 173.7V, but the breakdown voltage BV_D2 with the buried doped region 400N can be increased to 786.1V, which greatly improves the withstand voltage performance of the device.

[0100] Next, refer to Figure 5 Another simulation result shown simulates the breakdown voltage BV_H between the high-voltage side circuit and the drain when the buried doped region 400N is in operation. This breakdown voltage BV_H is obtained, for example, by keeping the drain region 200D connected to a 600V potential and applying a scan voltage that gradually increases from 600V to the high-voltage side circuit (specifically, by continuously increasing the scan voltage from 600V to the second contact region of the fourth well region NW4) until breakdown occurs. Figure 5 As shown, after setting the buried doped region 400N, the breakdown voltage BV_H between the high-voltage side circuit and the drain terminal can reach 50V, which is much greater than the withstand voltage requirement of the isolation structure 300 (greater than 15V), ensuring that there is no leakage between the high-voltage side circuit and the drain terminal.

[0101] It should be noted that this embodiment uses the formation of a buried doped region 400N within the epitaxial layer 120N as an example. However, in other embodiments, N buried doped regions 400N arranged sequentially from bottom to top can be provided within the epitaxial layer 120N, where N≥2. In this case, N+1 epitaxial layers can be provided, and each buried doped region 400N is formed in the boundary region between two adjacent epitaxial layers. That is, in two adjacent epitaxial layers, the buried doped region 400N extends upward from the lower epitaxial layer to the upper epitaxial layer. The specific number of buried doped regions 400N can be determined based on the doping concentration of the actual isolation doped region and the total thickness of the epitaxial layer 120.

[0102] Regarding the level shifter described above, its fabrication method will be explained in detail below. (This can be combined with...) Figure 1 As shown, the fabrication method of the level shifter in this embodiment specifically includes: forming a field-effect transistor 200 on a substrate 100, the field-effect transistor 200 including a drain region 200D of a first doped type, a source region 200S of a first doped type, and a gate structure 200G, the drain region 200D and the source region 200S being formed within the substrate 100, and the gate structure 200G being formed on the substrate 100 and located between the source region 200S and the drain region 200D. Furthermore, the fabrication method further includes: forming an isolation structure 300 around the field-effect transistor 200, the isolation structure 300 including at least one isolation doped region of a second doped type, and forming at least one buried doped region 400N of a first doped type on the side of the isolation doped region near the field-effect transistor 200, the buried doped region 400N being formed within the doped layer and maintaining a predetermined distance from the top surface of the doped layer.

[0103] The substrate 100 has a doped layer of a first doping type. In this embodiment, the substrate 100 includes a substrate 110P and an epitaxial layer 120N formed on the substrate 110P. Specifically, the substrate 110P is a substrate of a second doping type, and the epitaxial layer 120N is an epitaxial layer of a first doping type. Therefore, the epitaxial layer 120N constitutes the doped layer of the first doping type of the substrate 100.

[0104] Furthermore, the fabrication method of the isolation structure 300 may include: sequentially forming at least two isolation doped regions of a second doping type (e.g., P-type isolation doped regions) within the substrate 100, wherein the at least two isolation doped regions are sequentially arranged from bottom to top and interconnected, and the bottommost isolation doped region extends downward from the epitaxial layer 120N into the substrate 110P (or, alternatively, the bottommost isolation doped region extends upward from the substrate 110P into the epitaxial layer 120N). In a specific example, the isolation doped region may also extend from the high-voltage side of the transistor region around the transistor region to the low-voltage side of the transistor region. In this embodiment, the isolation structure 300 specifically includes: a first buried region PBL1 of the second doping type, a first deep well region DPW1 of the second doping type, and a first shallow well region PW1 of the second doping type, sequentially interconnected from bottom to top.

[0105] In an optional embodiment, the fabrication method of the isolation structure 300 can be referred to Figure 7 , Figure 9 , Figures 11-13 As shown: First refer to Figure 7 As shown, a substrate 110P is provided, and a patterned mask layer 520 is formed on the substrate 110P before forming the epitaxial layer 120N; a second doping type ion implantation process (e.g., a P-type ion implantation process) is performed on the substrate 110P under the mask of the mask layer 520 to form a first buried region PBL1; then referring to Figure 9 As shown, an epitaxial process is performed to form an epitaxial layer 120N on the substrate 110P, and during the epitaxial formation of the epitaxial layer 120N, ions in the first buried region PBL1 can diffuse upward into the epitaxial layer 120N; then refer to Figure 11 and Figure 13 As shown, the epitaxial layer 120N is subjected to two second-type ion implantation processes (e.g., P-type ion implantation process) to sequentially form a first deep well region DPW1 and a first shallow well region PW1.

[0106] In addition, while preparing the first buried region PBL1, the first deep well region DPW1, and the first shallow well region PW1 of the isolation structure 300, a second buried region PBL2, a second deep well region DPW2, and a second shallow well region PW2 are also formed on the low-pressure side. The first buried region PBL1 and the second buried region PBL2 are connected to each other to form a ring structure, the first deep well region DPW1 and the second deep well region DPW2 are connected to each other to form a ring structure, and the first shallow well region PW1 and the second shallow well region PW2 are connected to each other to form a ring structure, thereby forming a ring-shaped isolation ring.

[0107] In one example, the method for preparing the isolation structure 300 further includes: preparing a first isolation oxide layer 310, as detailed in [reference needed]. Figure 12 As shown, the first isolation oxide layer 310 can be formed using a Localized Oxidation Isolation (LOCOS) process. In this embodiment, a second isolation oxide layer 210 and a field oxide layer 220 are also formed simultaneously with the preparation of the first isolation oxide layer 310.

[0108] Furthermore, the buried doped region 400N can be buried within the doped layer (i.e., epitaxial layer 120N) of the substrate 100. In a specific example, the epitaxial layer 120N can be formed using two epitaxial processes, and a first doping type ion implantation process (e.g., N-type ion implantation process) can be performed between adjacent epitaxial processes to form the buried doped region 400N. Then, the epitaxial process continues. This allows the buried doped region 400N to be precisely defined at a predetermined depth within the epitaxial layer 120N, thus creating a space between it and the top surface of the epitaxial layer 120N. In particular, when performing an N-type ion implantation process with implanted ions including antimony (Sb), due to the large molecular weight of antimony ions, splitting the epitaxial process before implantation is more advantageous for implanting antimony ions to the predetermined depth and also allows for better control of the diffusion range of the antimony doped region within the epitaxial layer 120N, preventing the diffusion range of the antimony doped region from becoming too large.

[0109] For details, please refer to [link / reference]. Figures 8-9 As shown, the method for preparing the buried doped region 400N includes: epitaxially forming a first epitaxial layer 121N on the substrate 110P; then, as shown... Figure 8 As shown, a patterned mask layer 530 is formed on the first epitaxial layer 121N, and an ion implantation process of a first doping type (e.g., N-type ion implantation process) is performed on the first epitaxial layer 121N under the mask of the mask layer 530 to form a buried doped region 400N; then, referring to Figure 9 As shown, a second epitaxial layer 122N is epitaxially formed on the first epitaxial layer 121N to bury the buried doped region 400N in the interface region between the first epitaxial layer 121N and the second epitaxial layer 122N, and ions in the buried doped region 400N can diffuse upward into the second epitaxial layer 122N during the epitaxial formation of the second epitaxial layer 122N.

[0110] The following combination Figures 6-15 A specific method for fabricating a semiconductor device with a level shifter is described in detail. This specific method includes the fabrication process of the level shifter and the fabrication process of other circuits (e.g., high-voltage side circuits).

[0111] First refer to Figure 6As shown, a substrate 110P is provided, which is a substrate of the second doping type. In this embodiment, the substrate 110P is a P-type substrate, which may be doped with boron ions (B) at a concentration of, for example, 1E13cm⁻¹. -3 -1.5E20cm -3 Next, a mask layer 510 is formed on the substrate 110P, and an ion implantation process of the first doping type (e.g., N-type ion implantation process) is performed under the mask of the mask layer 510 to form a fourth buried region NBL in the region of the high-voltage side circuit. The mask layer 510 can then be removed.

[0112] Next, refer to Figure 7 As shown, a mask layer 520 is formed on the substrate 110P. This mask layer 520 defines the patterns of a first buried region PBL1 and a second buried region PBL2. The pattern of the first buried region PBL1 is located within an isolation region, and the pattern of the second buried region PBL2 is located on the low-voltage side of the transistor region. The first buried region PBL1 surrounds the periphery of the transistor region and connects to the second buried region PBL2. Then, a second doping type ion implantation process (e.g., a P-type ion implantation process) can be performed under the mask of the mask layer 520 to form the first buried region PBL1 and the second buried region PBL2 within the substrate 110P. In this embodiment, a third buried region PBL3 pattern is also defined within the mask layer 520. The pattern of the third buried region PBL3 is located within the transistor region, so that when performing the second doping type ion implantation process (e.g., a P-type ion implantation process), the third buried region PBL3 can be formed simultaneously within the transistor region.

[0113] Next, refer to Figure 8 As shown, a first epitaxial layer 121N is epitaxially formed on the substrate 110P. During the epitaxial formation of the first epitaxial layer 121N, ions in the first buried region PBL1, the second buried region PBL2, the third buried region PBL3, and the fourth buried region NBL can extend upward from the substrate 110P into the first epitaxial layer 121N. Specifically, the first epitaxial layer 121N is an epitaxial layer of a first doping type, with a thickness of, for example, 2 μm-4 μm; and, for example, the first epitaxial layer 121N is phosphorus-doped, with a doping concentration of, for example, 1E14 cm⁻¹. -3 -1.6E20 cm -3 By controlling the thickness of the first epitaxial layer 121N, the distance between the subsequently formed buried doped region 400N and the substrate 110P can be adjusted accordingly.

[0114] Continue to refer to Figure 8As shown, a mask layer 530 is formed on the first epitaxial layer 121N, exposing the area of ​​the buried doped region 400N to be formed. Then, an ion implantation process of a first doping type (e.g., N-type ion implantation) can be performed under the mask of the mask layer 530 to form the buried doped region 400N within the first epitaxial layer 121N. In this embodiment, the buried doped region 400N is, for example, an Sb doped region, with an implantation energy of, for example, 10 KeV-5000 KeV, and an ion doping concentration of, for example, 1E14 cm⁻¹. -3 -1E20cm -3 .

[0115] Next, refer to Figure 9 As shown, a second epitaxial layer 122N is epitaxially formed on the first epitaxial layer 121N. Specifically, the second epitaxial layer 122N is a first-doped epitaxial layer with a thickness of, for example, 3μm-5μm. By controlling the thickness of the second epitaxial layer 122N, the distance between the buried doped region 400N and the top surface of the substrate is adjusted accordingly. Furthermore, during the epitaxial formation of the second epitaxial layer 122N, ions in the buried doped region 400N can be extended upwards from the first epitaxial layer 121N into the second epitaxial layer 122N. In this embodiment, the buried doped region 400N is an Sb doped region. Due to the large molecular weight of Sb ions, the diffusion range of Sb ions can be effectively controlled, avoiding excessive diffusion of Sb ions. In addition, during the epitaxial formation of the second epitaxial layer 122N, the first buried region PBL1 can be further extended upwards, which is beneficial for its connection with the subsequently formed first deep well region DPW1.

[0116] Next, refer to Figure 10 As shown, a mask layer 540 is formed on the second epitaxial layer 122N. The mask layer 540 defines the pattern of a third well region, and a first doping type ion implantation process (e.g., N-type ion implantation process) can be performed under the mask layer 540 to form a third well region NW1 within the epitaxial layer 120N. In this embodiment, a fourth well region NW2 pattern is also defined within the mask layer 540. The pattern of the fourth well region NW2 is located in the region of the high-voltage side circuit, so that when the first doping type ion implantation process (e.g., N-type ion implantation process) is performed, the fourth well region NW2 can be formed simultaneously in the region of the high-voltage side circuit. Afterwards, the mask layer 540 can be removed.

[0117] Next, refer to Figure 11As shown, a mask layer 550 is formed on the second epitaxial layer 122N. The mask layer 550 defines the patterns of a first deep well region DPW1 and a second deep well region DPW2, wherein the first deep well region DPW1 surrounds the transistor region and connects to the second deep well region DPW2. Then, a second doping type ion implantation process (e.g., a P-type ion implantation process) can be performed under the mask of the mask layer 550 to form the first deep well region DPW1 and the second deep well region DPW2 within the epitaxial layer 120N. The bottom of the first deep well region DPW1 is connected to the first buried region PBL1 below it, and the bottom of the second deep well region DPW2 is connected to the second buried region PBL2 below it.

[0118] In this embodiment, the buried doped region 400 may have a portion facing the boundary between the first deep well region DPW1 and the first buried region PBL1. Specifically, the first buried region PBL1 and the first deep well region DPW1 are interconnected through ion diffusion. Therefore, the ion concentration at the boundary between the first deep well region DPW1 and the first buried region PBL1 is usually low, which can effectively increase the depletion degree within the isolation doped region.

[0119] Next, refer to Figure 12 As shown, a first isolation oxide layer 310 is formed on the surface of the epitaxial layer 120N. The first isolation oxide layer 310 is formed above the isolation doped region to form the isolation structure 300 and enhance the isolation performance of the isolation structure 300. The first isolation oxide layer 310 can be formed, for example, using a local oxidation of silicon (LOCOS) process, specifically including: forming a mask layer 560 on the epitaxial layer 120N, then performing an oxidation process to form the first isolation oxide layer 310, and then removing the mask layer 560. In this embodiment, a field oxide layer 220 and a second isolation oxide layer 210 are also formed simultaneously with the formation of the first isolation oxide layer 310.

[0120] Next, refer to Figure 13As shown, a mask layer 570 is formed on the epitaxial layer 120N. The mask layer 570 defines the patterns of a first shallow well region PW1 and a second shallow well region PW2, wherein the first shallow well region PW1 surrounds the periphery of the transistor region and connects to the second shallow well region PW2. Then, a second doping type ion implantation process (e.g., a P-type ion implantation process) is performed under the mask of the mask layer 570 to form the first shallow well region PW1 and the second shallow well region PW2 within the epitaxial layer 120N. Furthermore, the bottom of the first shallow well region PW1 is connected to the first deep well region DPW1 below it, and the bottom of the second shallow well region PW2 is connected to the second deep well region DPW2 below it. In this way, an isolation ring is formed on the periphery of the transistor region, and the second shallow well region PW2 also serves to constitute the body region of the channel inversion of the field-effect transistor.

[0121] For details, please refer to the following: Figure 14 As shown, an oxidation process is performed to form a gate oxide layer on the epitaxial layer 120N, followed by the formation of a gate structure 200G on the epitaxial layer 120N. The gate structure 200G covers a portion of the second shallow well region PW2. In this embodiment, the gate structure 20G further extends to cover a field oxide layer 220 to form a field plate structure, improving the device's breakdown voltage performance.

[0122] In a further embodiment, sidewalls (not shown in the figure) can be formed on the sidewalls of the gate structure 200G. The method for fabricating the sidewalls specifically includes: depositing a sidewall material that covers the top surface and sidewalls of the gate structure 200G, and also covers the substrate surface outside the gate structure; then, performing an etch-back process to remove the sidewall material on the top surface of the gate structure and the sidewall material on the top surface of the substrate, leaving the sidewall material of the gate structure 200G sidewalls intact to form the sidewalls.

[0123] Next, refer to Figure 15 As shown, an ion implantation process of the first doping type (e.g., N-type ion implantation process) is performed to form a source region 200S and a drain region 200D. The source region 200S is formed within the second shallow well region PW2, and the drain region 200D is formed within the third well region NW1. In this embodiment, a second contact region of the first doping type may also be formed simultaneously in the fourth well region NW2 during the step.

[0124] Continue to refer to Figure 15 As shown, a second type of doping ion implantation process (e.g., P-type ion implantation process) is performed to form a first contact region 200B, which is formed within a second shallow well region PW2, and the ion doping concentration of the first contact region 200B is higher than that of the second shallow well region PW2.

[0125] In a further embodiment, an interconnect structure is formed on the substrate 100, the interconnect structure electrically connecting devices on the substrate 100. Specifically, this can be combined with... Figure 2 As shown, the method for fabricating the interconnect structure includes: forming an interlayer dielectric layer 610 on a substrate 100, the interlayer dielectric layer 610 covering semiconductor devices on the substrate 100; then, forming a plurality of conductive plugs 620 within the interlayer dielectric layer 610, the plurality of conductive plugs 620 including plugs electrically connected to the source region 200S of a field-effect transistor, plugs electrically connected to the drain region 200D of a field-effect transistor, plugs electrically connected to the gate structure 200G of a field-effect transistor, plugs electrically connected to the first contact region 200B within the second shallow well region PW2, and plugs electrically connected to the second contact region within the fourth well region NW2; subsequently, forming a plurality of electrode conductive layers 630 on the interlayer dielectric layer 610, the plurality of electrode conductive layers 630 covering the corresponding conductive plugs 620, so as to electrically connect the source region 200S, the drain region 200D, and the gate structure 200G to corresponding signal ports.

[0126] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Furthermore, although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention using the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, still fall within the scope of protection of the present invention.

[0127] It should also be understood that, unless otherwise specified or indicated, the terms "first," "second," "third," etc., used in the specification are merely for distinguishing individual components, elements, steps, etc., and are not for indicating logical or sequential relationships between them. Furthermore, it should be recognized that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" implies a reference to one or more steps or devices, and may include secondary steps and secondary devices.

Claims

1. A level shifter, characterized in that, include: A substrate having a doped layer of a first doping type; A field-effect transistor includes a drain region of a first doping type, a source region of a first doping type, and a gate structure, wherein the gate structure is formed on the substrate and located between the source region and the drain region; An isolation structure is located around the field-effect transistor, the isolation structure including at least one isolation doped region of a second doping type formed within the doped layer; At least one buried doped region of a first doping type is buried within the doped layer and maintains a predetermined distance from the top surface of the doped layer, and is formed on at least one side of the isolated doped region; The substrate includes a second doped substrate and a first doped epitaxial layer arranged sequentially from bottom to top. The field-effect transistor is formed on the epitaxial layer. The isolation structure penetrates the epitaxial layer and reaches the substrate. The buried doped region is formed in the epitaxial layer. The isolation structure includes at least two isolation doped regions arranged sequentially from bottom to top and interconnected with each other, wherein the isolation doped region located at the bottom layer extends upward from the substrate into the epitaxial layer; The isolation doped region in the isolation structure includes a first buried region of the second doping type, a first deep well region of the second doping type, and a first shallow well region of the second doping type, which are arranged sequentially from bottom to top and connected to each other. The buried doped region is directly opposite the boundary position of the first buried region and the first deep well region in a direction parallel to the substrate surface.

2. The level shifter as described in claim 1, characterized in that, The buried doped region is disposed on the side of the isolation doped region closer to the field-effect transistor; and / or, the buried doped region is disposed on the side of the isolation doped region farther from the field-effect transistor.

3. The level shifter as described in claim 2, characterized in that, The buried doped region is disposed between the drain region and the isolation doped region in a direction parallel to the substrate surface.

4. The level shifter as described in claim 1, characterized in that, The epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked from bottom to top, and the buried doped region is formed in the surface region of the first epitaxial layer and extends upward to the second epitaxial layer.

5. The level shifter as described in claim 1, characterized in that, The level shifter further includes a second shallow well region of a second doped type, a second deep well region of a second doped type, and a second buried region of a second doped type, which are connected sequentially from bottom to top and located on the side of the gate structure near the source region. The source region is formed within the second shallow well region. The first shallow well region extends from the outside of the drain region around the field-effect transistor to the second shallow well region and connects with the second shallow well region; The first deep well region extends from the outside of the drain region around the field-effect transistor to the second deep well region to connect with the second deep well region; The first buried region extends from the outside of the drain region around the field-effect transistor to the second buried region and connects with the second buried region.

6. The level shifter as described in claim 1, characterized in that, The level shifter also includes a plurality of third buried regions arranged side by side, the plurality of third buried regions being arranged between the source region and the drain region, and the third buried regions extending upward from the substrate into the epitaxial layer.

7. The level shifter as described in claim 1, characterized in that, The level shifter further includes a third well region of a first doping type, the third well region being located on the side of the gate structure near the drain region, the drain region being formed within the third well region; and a buried doping region being disposed between the drain region and the isolation doping region, the buried doping region at least partially overlapping the third well region on the side of the third well region near the isolation doping region.

8. The level shifter as described in claim 1, characterized in that, N buried doped regions are provided on the same side of the isolation doped region, and the N buried doped regions are arranged sequentially from bottom to top; and the doped layer includes N+1 epitaxial layers, and the buried doped regions are formed at the boundary region of two adjacent epitaxial layers.

9. The level shifter according to any one of claims 1-8, characterized in that, The dopant ions in the buried doped region include antimony ions.

10. A method for preparing a level shifter, characterized in that, include: A field-effect transistor is formed on a substrate. The field-effect transistor includes a drain region of a first doped type, a source region of a first doped type, and a gate structure. The drain region and the source region are formed in the substrate, and the gate structure is formed on the substrate and located between the source region and the drain region. The substrate has a doped layer of a first doping type, and the fabrication method further includes: forming an isolation structure around the field-effect transistor, the isolation structure including forming at least one isolation doped region of a second doping type in the doped layer, and forming at least one buried doped region of the first doping type on at least one side of the isolation doped region, the buried doped region being formed in the doped layer and maintaining a predetermined distance from the top surface of the doped layer; The substrate includes a second-doped substrate and a first-doped epitaxial layer disposed sequentially from bottom to top; wherein, the method for fabricating the isolation structure includes: Prior to forming the epitaxial layer, a second-doped ion implantation process is performed on the substrate to form a first buried region of the second-doped type in the substrate; and, During the epitaxial process to form the epitaxial layer on the substrate, ions from the first buried region diffuse upward into the epitaxial layer, and the epitaxial layer is subjected to two second-type ion implantation processes to form a first deep well region and a first shallow well region in sequence. The bottom of the first deep well region is connected to the first buried region, and the bottom of the first shallow well region is connected to the first deep well region.

11. The method for preparing a level shifter as described in claim 10, characterized in that, When preparing the first buried region of the isolation structure, a second buried region is also formed on the low-voltage side of the transistor region. The first buried region extends from the high-voltage side of the transistor region around the transistor region to the low-voltage side of the transistor region to connect the second buried region. During the fabrication of the first deep well region of the isolation structure, a second deep well region is also formed on the low-voltage side of the transistor region. The first deep well region extends from the high-voltage side of the transistor region around the transistor region to the low-voltage side of the transistor region to connect to the second deep well region; and... When fabricating the first shallow well region of the isolation structure, a second shallow well region is also formed on the low-voltage side of the transistor region. The first shallow well region extends from the high-voltage side of the transistor region around the transistor region to the low-voltage side of the transistor region to connect the second shallow well region.

12. The method for preparing a level shifter as described in claim 11, characterized in that, The method for preparing the buried doped region includes: A first epitaxial layer is formed, and an ion implantation process of a first doping type is performed on the first epitaxial layer to form a buried doped region; and, A second epitaxial layer is formed on the first epitaxial layer to bury the buried doped region in the interface region between the first epitaxial layer and the second epitaxial layer.

13. A semiconductor device, characterized in that, Including the level shifter as described in any one of claims 1-9.

Images