A method for preparing a selective emitter cell and a selective emitter cell

Abstract

The present application discloses a method for preparing an SE cell and an SE cell, belonging to the field of solar cells. The method includes: performing at least two diffusions, at least two drives, at least two annealings and diffusions on a silicon wafer in sequence to obtain a first silicon wafer with a target sheet resistance; forming an SE structure on the front surface of the first silicon wafer by laser irradiation to obtain a second silicon wafer with a target sheet resistance; coating the second silicon wafer to obtain a third silicon wafer; printing a conductive paste on the surface of the third silicon wafer by using a knotless screen plate to form an electrode, thereby obtaining an SE cell; the knotless screen plate includes a screen fabric and a photosensitive resin film layer coated on the screen fabric; the screen fabric is a knotless screen fabric. The present application uses a high mesh count and narrow line width screen plate to match a high resistance and low surface concentration process, which can further improve the printing performance and thus enhance the cell conversion efficiency.

Description

Technical Field

[0001] This application relates to the field of solar cells, and particularly to a method for manufacturing a selective emitter cell and a selective emitter cell. Background Art

[0002] An SE (Selective Emitter) cell, i.e., a selective emitter cell, forms a highly doped and deeply diffused region in the fine grid contact area and a low-doped and shallowly diffused region in the light-irradiated area. By selectively doping the emitter region, different sheet resistances are achieved in the grid contact area and other areas, reducing the series resistance and increasing the short-circuit current, ultimately improving the cell conversion efficiency.

[0003] Currently, the mainstream cell size in the industry is a single-crystalline 182mm PERC (Passivated Emitter Rear Cell) selective emitter cell, and the number of sub-grid lines also increases as the cell size becomes larger. To ensure an effective increase in efficiency, it is necessary to minimize the shading area to the greatest extent on the basis of the increase in grid lines, that is, to reduce the grid line width. The efficiency improvement advantage of the knotless narrow line width needs to be fully exerted by matching the high-resistance and low-surface-concentration diffusion process. Since the knotless screen grid lines are finer, the knotless technology has higher requirements for the sheet resistance of diffusion. The existing conventional cell diffusion process has a relatively deep junction depth, low sheet resistance, and high surface concentration, and its electrical performance shows a low open-circuit voltage and low short-circuit current, and the improvement range of the cell efficiency is limited. Therefore, a method for manufacturing a selective emitter cell is needed to solve the problem of low cell conversion efficiency caused by the difficulty of matching the conventional diffusion process with a high-mesh knotless screen in the existing cell manufacturing process. Summary of the Invention

[0004] The purpose of this application is to provide a method for manufacturing a selective emitter cell and a selective emitter cell, thereby improving the cell conversion efficiency.

[0005] To achieve the above purpose, this application provides a method for manufacturing a selective emitter cell, including:

[0006] Diffusing, pushing, annealing, and diffusing a silicon wafer at least twice in sequence to obtain a first silicon wafer with a target diffusion sheet resistance;

[0007] Forming an SE structure on the front surface of the first silicon wafer by laser irradiation to obtain a second silicon wafer with a target sheet resistance;

[0008] Coating the second silicon wafer to obtain a third silicon wafer;

[0009] An electrode is formed by printing a conductive paste on the surface of the third silicon wafer using a knotless screen printing plate, and a selective emitter cell is obtained; the knotless screen printing plate includes a screen mesh and a photosensitive resin film layer coated on the screen mesh; the screen mesh is a knotless screen mesh.

[0010] Optionally, the step of forming an electrode by printing a conductive paste on the surface of the third silicon wafer using a knotless positive electrode screen printing plate to obtain a selective emitter cell includes:

[0011] An electrode is formed by printing a conductive paste on the surface of the third silicon wafer using a knotless positive electrode screen printing plate, and a selective emitter cell is obtained; the viscosity range of the conductive paste is from 220,000 mPa·s to 3,200,000 mPa·s, including both ends of the value.

[0012] Optionally, the mesh number range of the screen mesh is from 480 meshes to 520 meshes, including both ends of the value.

[0013] Optionally, the range of the target diffusion sheet resistance is from 160 Ω / □ to 170 Ω / □, including both ends of the value; the range of the target sheet resistance is from 80 Ω / □ to 90 Ω / □, including both ends of the value.

[0014] Optionally, positive electrode pattern holes are provided on the photosensitive resin film layer, the positive electrode pattern holes include a plurality of positive electrode main grids and a plurality of positive electrode sub-grids, and the number range of the positive electrode sub-grids is from 150 to 170, including both ends of the value.

[0015] Optionally, the at least two diffusions include:

[0016] The first diffusion step: Phosphorus oxychloride and oxygen are introduced at a constant temperature; the range of the first temperature is from 760 °C to 780 °C, including both ends of the value;

[0017] The second diffusion step: The temperature is raised from the first temperature to the second temperature, and phosphorus oxychloride and oxygen are introduced; the range of the second temperature is from 780 °C to 800 °C, including both ends of the value;

[0018] The third diffusion step: The temperature is raised from the second temperature to the third temperature, and phosphorus oxychloride and oxygen are introduced; the range of the third temperature is from 840 °C to 860 °C, including both ends of the value.

[0019] Optionally, the at least two pushes include:

[0020] The first push step: Oxygen is introduced, and the flow rate of the oxygen is 110 sccm; the range of the fourth temperature is from 840 °C to 860 °C, including both ends of the value;

[0021] The second push step: The range of the fifth temperature is from 840 °C to 860 °C, including both ends of the value.

[0022] Optionally, the at least two annealing processes include:

[0023] The first annealing: cooling from the fifth temperature to the sixth temperature and introducing oxygen; the sixth temperature is 825 °C;

[0024] Cooling: cooling from the sixth temperature to the seventh temperature; the seventh temperature is 810 °C;

[0025] The second annealing: cooling from the seventh temperature to the eighth temperature and introducing oxygen; the eighth temperature is 790 °C.

[0026] Optionally, the diffusion includes:

[0027] The fourth diffusion: introducing phosphorus oxychloride and oxygen at a constant temperature; the ninth temperature is 780 °C; the time is 540 s; the flow rate of phosphorus oxychloride is 1500 sccm; the flow rate of oxygen is 500 sccm.

[0028] To achieve the above object, the present application also provides a selective emitter cell, including: a selective emitter cell prepared by the above-mentioned selective emitter cell preparation method.

[0029] A method for preparing a selective emitter cell provided by the present application includes: sequentially performing at least two diffusions, at least two drives, at least two annealing processes and a diffusion on a silicon wafer to obtain a first silicon wafer with a target diffusion sheet resistance; forming an SE structure on the front surface of the first silicon wafer by laser irradiation to obtain a second silicon wafer with a target sheet resistance; coating the second silicon wafer to obtain a third silicon wafer; printing a conductive paste on the surface of the third silicon wafer using a knotless screen to form an electrode, thereby obtaining a selective emitter cell; the knotless screen includes a screen mesh and a photosensitive resin film layer coated on the screen mesh; the screen mesh is a knotless screen mesh.

[0030] Obviously, the use of a high-mesh narrow line-width screen printing in the present application can effectively reduce the printing line width of the solar cell. The reduction of the line width can greatly reduce the shading area. At the same time, matching with the high-resistance low-surface-concentration process can further improve the printing performance, thereby improving the cell conversion efficiency. The present application also provides a selective emitter cell. Compared with the cell obtained by the traditional cell preparation method, the cell conversion efficiency is increased by 0.05% - 0.1%. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0032] Figure 1 This is a flowchart of a method for fabricating a selective emitter cell provided by an embodiment of the present application;

[0033] Figure 2 This is a schematic flow diagram of a method for fabricating a selective emitter cell provided by an embodiment of the present application;

[0034] Figure 3 This is a schematic flow diagram of a high-resistance, low-surface-concentration, low-pressure diffusion process provided by an embodiment of the present application;

[0035] Figure 4 This is a schematic structural diagram of a knotless screen provided by an embodiment of the present application;

[0036] Figure 5 This is a schematic diagram of 160 positive secondary grids provided by an embodiment of the present application.

[0037] Appendix Figure 4 In the following, the reference signs are explained as follows:

[0038] 1 - wire mesh;

[0039] 2 - photosensitive resin film layer;

[0040] 3 - positive secondary grid. Detailed implementation manners

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0042] Please refer to Figure 1 , Figure 1 This is a flowchart of a method for fabricating a selective emitter cell provided by an embodiment of the present application, and the method may include:

[0043] S101: Diffuse, push, anneal, and diffuse the silicon wafer at least twice in sequence to obtain a first silicon wafer with a target diffusion sheet resistance.

[0044] The present embodiment does not limit the specific value of the target diffusion sheet resistance, as long as it can match the use of the knotless screen in the present embodiment. For example, the range of the target diffusion sheet resistance may be 160 Ω / sq to 170 Ω / sq, including both ends of the values.

[0045] This embodiment does not limit the specific manner and specific parameter values for performing multiple diffusions, as long as it is ensured that the first silicon wafer with the target diffusion sheet resistance can be obtained. For example, the at least two diffusions may include: The first diffusion: Constantly introducing phosphorus oxychloride (POCl3) and oxygen; the first temperature ranges from 760 °C to 780 °C, including both ends; the time is 300 s; the flow rate range of phosphorus oxychloride is from 600 sccm to 700 sccm, including both ends; the flow rate of oxygen is 500 sccm; The second diffusion: Heating from the first temperature to the second temperature and introducing phosphorus oxychloride and oxygen; the second temperature ranges from 780 °C to 800 °C, including both ends; the time is 120 s; the flow rate range of phosphorus oxychloride is from 600 sccm to 700 sccm, including both ends; the flow rate of oxygen is 500 sccm; The third diffusion: Heating from the second temperature to the third temperature and introducing phosphorus oxychloride and oxygen; the third temperature ranges from 840 °C to 860 °C, including both ends; the time is 60 s; the flow rate range of phosphorus oxychloride is from 600 sccm to 700 sccm, including both ends; the flow rate of oxygen is 500 sccm. It should be noted that in the first diffusion, constantly introducing the phosphorus source (POCl3, phosphorus oxychloride) can improve the sheet resistance uniformity; in the second and third diffusions, introducing the phosphorus source with variable temperature can reduce the heating time.

[0046] This embodiment does not limit the specific manner and specific parameter values for performing multiple pushes, as long as it is ensured that the first silicon wafer with the target diffusion sheet resistance can be obtained. For example, the at least two pushes may include: The first push: Introducing oxygen, and the flow rate of the oxygen is 110 sccm; the fourth temperature ranges from 840 °C to 860 °C, including both ends; the time is 480 s; The second push: The fifth temperature ranges from 840 °C to 860 °C, including both ends; the time is 480 s. It should be noted that in the first push, the surface concentration can be reduced through aerobic pushing; in the second push, the junction depth can be increased through high-temperature pushing.

[0047] This embodiment does not limit the specific manner and specific parameter values for performing multiple annealings, as long as it is ensured that the first silicon wafer with the target diffusion sheet resistance can be obtained. For example, the at least two annealings may include: The first-step annealing: cooling from the fifth temperature to the sixth temperature and introducing oxygen; the sixth temperature is 825 °C; the time is 280 s; the flow rate of the oxygen is 240 sccm; Cooling: cooling from the sixth temperature to the seventh temperature; the seventh temperature is 810 °C; the time is 560 s; The second-step annealing: cooling from the seventh temperature to the eighth temperature and introducing oxygen; the eighth temperature is 790 °C; the time is 280 s; the flow rate of the oxygen is 500 sccm. It should be noted that by introducing oxygen at a low temperature in the first-step annealing and the second-step annealing, the surface concentration can be reduced.

[0048] This embodiment does not limit the specific manner and specific parameter values for performing diffusion, as long as it is ensured that the first silicon wafer with the target diffusion sheet resistance can be obtained. For example, the diffusion may include: The fourth-step diffusion: constantly introducing phosphorus oxychloride and oxygen at a constant temperature; the ninth temperature is 780 °C; the time is 540 s; the flow rate of the phosphorus oxychloride is 1500 sccm; the flow rate of the oxygen is 500 sccm. It should be noted that by adding the fourth-step diffusion to deposit a phosphorus source before taking out the boat and combining with SE and high-resistance silver paste, the problem of the contact between the silver paste and the PN junction caused by high resistance can be effectively solved.

[0049] Furthermore, in order to improve the light-trapping effect of the silicon wafer and increase light absorption, this embodiment may further include texturing the silicon wafer before step S101.

[0050] S102: Form an SE structure on the front surface of the first silicon wafer by laser irradiation to obtain a second silicon wafer with the target sheet resistance.

[0051] This embodiment does not limit the specific value of the target sheet resistance, as long as it is ensured that it can match the use of the knotless stencil in this embodiment. For example, the range of the target sheet resistance may be from 80 Ω / sq to 90 Ω / sq, including both end values.

[0052] S103: Coat the second silicon wafer to obtain a third silicon wafer.

[0053] This embodiment does not limit the specific method of coating the second silicon wafer, and traditional battery coating methods can be referred to. Further, in order to remove the phosphorus edge and prevent short - circuit, before coating the second silicon wafer, this embodiment may further include etching the second silicon wafer. This embodiment does not limit the specific method of etching the second silicon wafer, and traditional battery etching methods can be referred to. Further, in order to more flexibly and accurately remove the thin film plated on the surface of the second silicon wafer to form a metallized contact area, after coating the second silicon wafer, this embodiment may further include laser grooving the coated second silicon wafer. This embodiment does not limit the specific method of laser grooving the coated second silicon wafer, and traditional battery laser grooving methods can be referred to.

[0054] S104: Print conductive paste on the surface of the third silicon wafer using a knot - free screen printing plate to form electrodes, and obtain a selective emitter cell; the knot - free screen printing plate includes a screen mesh and a photosensitive resin film layer coated on the screen mesh; the screen mesh is a knot - free screen mesh.

[0055] It should be noted that by using a high - viscosity paste, the printing height of the grid lines can be increased, the best aspect ratio can be obtained, the grid line resistance can be reduced, the short - circuit current can be increased, and thus the battery conversion efficiency can be improved. This embodiment does not limit the specific value of the viscosity of the conductive paste, as long as it can match the knot - free screen printing plate of this embodiment. For example, the viscosity range of the conductive paste can be from 220000 mPa·s to 3200000 mPa·s, including both ends. This embodiment does not limit the specific type of the conductive paste, as long as the paste has conductivity. For example, the conductive paste can be silver paste. The printing performance and ohmic contact performance of Juhua S163 silver paste are better. Further, in order to improve the battery conversion efficiency, this embodiment can use a knot - free positive electrode screen printing plate to print Juhua S163 silver paste on the surface of the third silicon wafer to form electrodes, and obtain a selective emitter cell. It should be noted that through the test instrument Broolfield Visc (high - temperature rotational viscometer): CAP 2000 +, under the test conditions: 1 r / min, 25 °C, select Juhua S163 silver paste with a viscosity between 220000 and 3200000 mPa·s for use. It should be noted that through the above - mentioned high - resistance low - pressure diffusion process, using Juhua S163 silver paste to match the high - mesh narrow - line - width screen printing can further improve the printing performance and enhance the battery conversion efficiency.

[0056] This embodiment does not limit the specific mesh number of the screen mesh, as long as it can match the high - resistance low - surface - concentration process of this example. For example, the mesh number range of the screen mesh can be from 480 meshes to 520 meshes, including both ends.

[0057] A positive electrode pattern hole is provided on the photosensitive adhesive film layer. The positive electrode pattern hole includes a plurality of positive electrode main grids and a plurality of positive electrode sub-grids. The number of the positive electrode sub-grids ranges from 150 to 170, including the values at both ends. In this embodiment, the specific number of the positive electrode sub-grids is not limited, and the specific number of the positive electrode sub-grids can be determined according to the actual situation.

[0058] Based on the above embodiments, the application uses a high-mesh narrow line-width screen printing to effectively reduce the printing line width of the solar cell. The reduction of the line width can greatly reduce the light-shielding area. At the same time, matching the high-resistance low-surface-concentration process can further improve the printing performance, thereby improving the battery conversion efficiency.

[0059] The embodiment of the application also provides a selective emitter cell, including: a selective emitter cell prepared by the selective emitter cell preparation method described above.

[0060] Based on the above embodiments, the selective emitter cell prepared by the application using a high-mesh narrow line-width screen to match the high-resistance low-surface-concentration process has a battery conversion efficiency increased by 0.05% - 0.1% compared with the battery obtained by the traditional battery preparation method. The selective emitter cell of the application is based on the SE and knotless screen superposition low-pressure diffusion technology and is applicable to 182 mm silicon wafers; it can also be matched with larger 210 mm silicon wafers, and combined with the multi-main-grid half-cell design, it can realize the mass production of high-efficiency and high-power modules. After being made into modules, the average power is increased by at least 0.5 W (a 0.1% efficiency increase at the battery end corresponds to a power increase of about 1 W).

[0061] The following combines specific examples to illustrate the above selective emitter cell preparation process. Please refer to Figure 2 、 Figure 3 、 Figure 4 and Figure 5 , and the process is as follows:

[0062] Texturize the silicon wafer; diffuse a phosphorus source on the surface of the silicon wafer by using a high-resistance low-surface-concentration low-pressure diffusion process to form a PN junction; form an SE structure on the front surface of the silicon wafer by laser irradiation; remove the phosphorus edge by wet etching; perform oxidation annealing; deposit AlOx (aluminum oxide) on the front surface of the silicon wafer to form a passivation layer; deposit P-SiNx (silicon nitride) thin films on the front and back surfaces; perform laser grooving on the back surface; form electrodes on both sides of the silicon wafer by screen printing; sinter the electrodes printed on the surface of the silicon wafer at a high temperature; finally, test the performance of the obtained battery.

[0063] The diffusion uses a high-resistance low-surface-concentration low-pressure diffusion process, and the specific process flow is as follows. See Figure 2 :

[0064] (1) The first diffusion: 770 °C, 300 s + 650 sccm POCl3 + 500 sccm O2;

[0065] (2)Second diffusion: 790 °C, 120 s + 650 sccm POCl3 + 500 sccm O2;

[0066] (3)Third diffusion: 850 °C, 60 s + 650 sccm POCl3 + 500 sccm O2;

[0067] (4)First push: 850 °C, 480 s, 110 sccm O2;

[0068] (5)Second push: 850 °C, 480 s;

[0069] (6)First annealing: 825 °C, 280 s, 240 sccm O2;

[0070] (7)Cooling: 810 °C, 560 s;

[0071] (8)Second annealing: 790 °C, 280 s, 500 sccm O2;

[0072] (9)Diffusion: 780 °C, 540 s + 1500 sccm POCl3 + 500 sccm O2.

[0073] Through the above diffusion process, the diffusion sheet resistance is designed to be 165 Ω / sq; after forming the SE structure by laser irradiation, the sheet resistance is designed to be 85 Ω / sq.

[0074] Referring to Table 1, compared with the conventional diffusion process on the production line, the differences in the high-resistance, low-surface-concentration, low-pressure diffusion process of this application are mainly in the diffusion time and temperature, phosphorus source concentration (phosphorus source POCl3 is carried in small nitrogen), the time of two-step pushing, and the time and temperature of annealing.

[0075] Table 1 Comparison between the conventional diffusion process on the production line and the high-resistance, low-surface-concentration, low-pressure diffusion process of this application

[0076]

[0077] See Figure 4, the matching knotless screen printing stencil is a PI (polyimide film) knotless positive electrode stencil applied to single-crystal selective emitter cells. Among them, the most important thing is that the screen mesh 1 uses a 480-mesh knotless screen mesh with a wire diameter of 11μm, that is, there are 480 mesh holes per square inch, and the wire diameter of the wire mesh is 11μm. The thickness of the screen mesh 1 is 15μm after heavy rolling, and the thickness of the photosensitive resin film layer 2 is 4μm. There are positive electrode pattern holes on the photosensitive resin film layer 2. The positive electrode pattern holes are formed by the perpendicular arrangement of the positive electrode main grid and several positive electrode sub-grids 3. When printing, the positive silver paste leaks out from the positive electrode pattern holes to form a positive electrode on the battery chip. The number of positive electrode main grids is 11. The line width of the positive electrode sub-grid 3 is 15μm, and the number of roots is 160. See Figure 5 . The SE laser grooving pattern is also 160. During the plate-making process, the drawing of 160 SE patterns is input through a laser scanning device to make the stencil completely fit the SE pattern. Using a 520-mesh PI knotless stencil with a wire diameter of 11μm, the same effect can be achieved when the number of positive electrode sub-grids is between 150 and 170. The matching positive silver paste is the polymer S163 positive silver paste. Through the test instrument Broolfield Visc: CAP2000+, under the test conditions: 1r / min, 25°C, select the polymer S163 positive silver paste with a viscosity between 220000 and 3200000 mPa·s for use.

[0078] See Table 2. Table 2 takes the sheet resistance controlled by different processes as a single variable, and compares different electrical performance parameters of the low-pressure diffusion process and the conventional process under the same stencil and paste. Among them, Eta is the conversion efficiency; Uoc is the open-circuit voltage; Isc is the short-circuit current; FF is the fill factor; Rs is the series resistance; Rsh is the parallel resistance; Irev2 is the reverse leakage current. Compared with the conventional process, the conversion efficiency of the low-pressure diffusion process has increased by 0.08%, and the increase range is 3%.

[0079] Table 2 Comparison of different electrical performance parameters of the low-pressure diffusion process and the conventional process using a 480-mesh screen mesh with a wire diameter of 11μm

[0080]

[0081] See Table 3. Taking the sheet resistance controlled by different processes as a single variable, using a 520-mesh screen mesh with a wire diameter of 11μm under the same paste, the efficiency of the low-pressure diffusion process is also improved compared with the conventional process.

[0082] Table 3 Comparison of different electrical performance parameters of the low-pressure diffusion process and the conventional process using a 520-mesh screen mesh with a wire diameter of 11μm

[0083]

[0084] In this text, specific examples are used to elaborate on the principles and implementation manners of the present application, and the various embodiments have a progressive relationship. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the selective emitter cell disclosed in the embodiments, reference can be made to the corresponding method section for description. The description of the above embodiments is only used to help understand the method and its core idea of the present application. For those of ordinary skill in the art of this technology, without departing from the principle of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0085] It should also be noted that in this specification, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of another identical element in the process, method, article or device comprising the element.

Claims

1. A method for fabricating a selective emitter solar cell, characterized in that, Including: Successively performing the following operations on a silicon wafer: The first diffusion step: at a first temperature, constantly introducing phosphorus oxychloride and oxygen; The second diffusion step: heating from the first temperature to a second temperature, and introducing phosphorus oxychloride and oxygen; The third diffusion step: heating from the second temperature to a third temperature, and introducing phosphorus oxychloride and oxygen; The first drive step: at a fourth temperature, introducing oxygen; the range of the fourth temperature is from 840 °C to 860 °C, and includes the values at both ends; The second drive step: at a fifth temperature; the range of the fifth temperature is from 840 °C to 860 °C, and includes the values at both ends; The first annealing step: cooling from the fifth temperature to a sixth temperature, and introducing oxygen; Cooling: cooling from the sixth temperature to a seventh temperature; The second annealing step: cooling from the seventh temperature to an eighth temperature, and introducing oxygen; The fourth diffusion step: at a ninth temperature, constantly introducing phosphorus oxychloride and oxygen to obtain a first silicon wafer with a target diffusion sheet resistance; Forming an SE structure on the front surface of the first silicon wafer by laser irradiation to obtain a second silicon wafer with a target sheet resistance; Coating the second silicon wafer to obtain a third silicon wafer; Printing a conductive paste on the surface of the third silicon wafer using a knotless screen to form an electrode, thereby obtaining the selective emitter solar cell; the knotless screen includes a mesh and a photosensitive resin film layer coated on the mesh; the mesh is a knotless mesh.

2. The method for manufacturing a selective emitter solar cell according to claim 1, characterized in that, The step of printing a conductive paste on the surface of the third silicon wafer using a knotless positive electrode screen to form an electrode, thereby obtaining the selective emitter solar cell, includes: Printing a conductive paste on the surface of the third silicon wafer using a knotless positive electrode screen to form an electrode, thereby obtaining the selective emitter solar cell; the viscosity range of the conductive paste is from 22,0000 mPa·s to 32,00000 mPa·s, and includes the values at both ends.

3. The method for preparing a selective emitter solar cell according to claim 1, wherein The mesh count range of the mesh is from 480 meshes to 520 meshes, and includes the values at both ends.

4. The method for manufacturing a selective emitter solar cell according to claim 1, characterized in that, The range of the target diffusion sheet resistance is from 160 Ω / □ to 170 Ω / □, and includes the values at both ends; the range of the target sheet resistance is from 80 Ω / □ to 90 Ω / □, and includes the values at both ends.

5. The method for preparing a selective emitter solar cell according to claim 1, characterized in that, Positive electrode pattern holes are provided on the photosensitive resin film layer, the positive electrode pattern holes include a plurality of positive main grids and a plurality of positive sub - grids, and the number of the positive sub - grids ranges from 150 to 170, and includes the values at both ends.

6. The method for preparing a selective emitter solar cell according to any one of claims 1 to 5, characterized in that: The first diffusion step: the range of the first temperature is from 760 °C to 780 °C, and includes the values at both ends; The second diffusion step: the range of the second temperature is from 780 °C to 800 °C, and includes the values at both ends; The third diffusion step: the range of the third temperature is from 840 °C to 860 °C, and includes the values at both ends.

7. The method for preparing a selective emitter solar cell according to claim 6, characterized in that: The first drive step: the flow rate of the oxygen is 110 sccm.

8. The method for preparing a selective emitter solar cell according to claim 6, characterized in that: The first annealing step: the sixth temperature is 825 °C; Cooling: the seventh temperature is 810 °C; Second annealing: The eighth temperature is 790 °C.

9. The method for manufacturing a selective emitter solar cell according to claim 6, characterized in that: Fourth diffusion: The ninth temperature is 780 °C; the time is 540 s; the flow rate of phosphorus oxychloride is 1500 sccm; the flow rate of oxygen is 500 sccm.

10. A selective emitter solar cell, characterized in that, Comprising: A selective emitter solar cell prepared by the method for manufacturing a selective emitter solar cell according to any one of claims 1 to 9.

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