A circuit structure and control method of a low noise amplifier

Abstract

The present invention relates to the field of amplifier circuit technology, and in particular to a circuit structure and control method of a low-noise amplifier. The circuit structure comprises: a second power supply, a third resistor, a second switch tube, a first capacitor, and a second capacitor; the second power supply is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first end of the second switch tube; the second end of the second switch tube is connected to the third end of the active amplifier tube; the third end of the second switch tube is grounded; the first end of the third switch tube is connected to the first power supply, the second end of the third switch tube is connected to the second end of the first capacitor, and the first end of the second capacitor is connected to the first end of the second DC-blocking capacitor; the third end of the third switch tube is connected to the first end of the second capacitor; and the second end of the second capacitor is grounded. The circuit structure provided by the present invention improves the reliability of the low-noise amplifier as a whole.

Description

Technical Field

[0001] The present invention relates to the technical field of amplifier circuits, and in particular to a circuit structure and a control method of a low-noise amplifier. Background Art

[0002] A low-noise amplifier (LNA) is a key element in wireless communication links. It amplifies weak signals carrying information received from the antenna and transmits the resulting information to the next stage of the circuit. However, LNAs generate noise, and during the amplification of weak signals, this noise can cause interference and affect signal accuracy. To mitigate this issue, bypass modules are integrated into LNA circuit designs to improve the receiver's dynamic range.

[0003] In an LNA with an integrated bypass module, when the LNA receives a low-power signal, the LNA enters the amplification mode, amplifying the received signal and outputting it to the next stage circuit. When a high-power signal is received, the LNA enters the bypass mode, attenuating the high-power signal and transmitting it to the next stage circuit. Figure 1 As shown, Figure 1 This is an existing LNA structure with an integrated bypass module, in which M1 is an active amplifier, DC_Block is a DC-blocking capacitor, and DC_Feed is an AC-blocking inductor. The input and output matching networks ensure that the active amplifier M1 operates within a specified frequency band. When the LNA input LNA_IN receives a low-power signal, the circuit power supply Vbias and the device operating power supply VDD provide a bias voltage for the amplifier M1, causing M1 to operate in the saturation amplification region. After amplification by the active amplifier M1, the low-power signal is output to the next stage circuit through the LNA output LNA_OUT. When the LNA input LNA_IN receives a high-power signal, the power supply Vbias and the device operating voltage VDD are deactivated, causing the active amplifier M1 to operate in the cutoff region. The first power supply VC1 provides a high-level voltage signal, causing the switch SW1 to operate in the linear resistance region. The high-power signal is then output through the switch SW1 to LNA_OUT.

[0004] However, in the existing LNA structure, when the effective voltage of a high-power signal received at the LNA input exceeds the maximum gate-source withstand voltage of the active amplifier M1, the gate-source of the active amplifier M1 may easily break down, causing the signal received at the input to leak from the M1 source to ground. This can cause the LNA circuit to cease normal operation and reduce the reliability of the LNA. Summary of the Invention

[0005] The present invention provides a circuit structure and a control method of a low noise amplifier, which are used to improve the reliability of the low noise amplifier.

[0006] On one hand, the present invention provides a circuit structure of a low-noise amplifier, including a circuit power supply, a device working power supply, an AC inductor, a first DC blocking capacitor, a second DC blocking capacitor, an input matching network, an output matching network, an active amplifier tube, a first resistor, a second resistor, a first power supply, and a first switching tube. The first end of the input matching network is connected to the input end of the low-noise amplifier, the second end of the input matching network is connected to the first end of the first DC blocking capacitor, the circuit power supply is connected to the first resistor and is connected to the second end of the first DC blocking capacitor through the first resistor, the first end of the active amplifier tube is connected to the second end of the first DC blocking capacitor, and the active amplifier tube is connected to the second end of the first DC blocking capacitor. The second end of the source amplifier tube is respectively connected to the second end of the AC-resistance inductor and the first end of the output matching network, the first end of the AC-resistance inductor is connected to the device working power supply, the second end of the output matching network is connected to the first end of the second DC-blocking capacitor, the second end of the second DC-blocking capacitor is connected to the output end of the low-noise amplifier, the first power supply is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the first switching tube, the second end of the first switching tube is connected to the output end of the low-noise amplifier, and the third end of the first switching tube is connected to the input end of the low-noise amplifier. The existing circuit structure also includes:

[0007] A second power supply, a third resistor, a second switch tube, a first capacitor, and a second capacitor;

[0008] The second power supply is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first end of the second switch tube;

[0009] The second end of the second switching tube is connected to the third end of the active amplifier tube;

[0010] The third terminal of the second switch tube is grounded;

[0011] The first end of the third switch tube is connected to the first power supply, the second end of the third switch tube is connected to the second end of the first capacitor, and the first end of the second capacitor is connected to the first end of the second DC blocking capacitor;

[0012] The third terminal of the third switch tube is connected to the first terminal of the second capacitor;

[0013] The second terminal of the second capacitor is grounded.

[0014] Optionally, it further includes: an attenuation module;

[0015] The attenuation module is arranged in a path between the first switch tube and the output end of the low noise amplifier.

[0016] Optionally, the attenuation module includes: a T-type attenuation network, a fourth resistor and a fourth switch tube;

[0017] The first end of the T-type attenuation network is connected to the second end of the first switch tube;

[0018] The second end of the T-type attenuation network is connected to the third end of the fourth switch tube;

[0019] The first end of the fourth switch is connected to the second end of the fourth resistor, and the first end of the fourth resistor is connected to the first power supply;

[0020] The second end of the fourth switch tube is connected to the output end of the low noise amplifier.

[0021] Optionally, the T-type attenuation network includes: a fifth resistor, a sixth resistor, a seventh resistor, and a third capacitor;

[0022] The first end of the fifth resistor is connected to the second end of the first switch tube;

[0023] The second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor respectively;

[0024] The second end of the sixth resistor is connected to the third end of the fourth switch tube;

[0025] The second end of the seventh resistor is connected to the first end of the third capacitor;

[0026] A second terminal of the third capacitor is grounded.

[0027] Optionally, the second switch tube is a field effect tube, the first end of the second switch tube is a gate, the second end is a drain, and the third end is a source.

[0028] Optionally, the third switch tube is a field effect tube, the first end of the third switch tube is a gate, the second end is a drain, and the third end is a source.

[0029] Optionally, the fourth switch tube is a field effect tube, the first end of the fourth switch tube is a gate, the second end is a drain, and the third end is a source.

[0030] Optionally, the second switch tube is a PMOS tube.

[0031] Optionally, the third switch tube is a PMOS tube.

[0032] Another aspect of the present invention provides a control method, which is applied to the circuit structure described above, and the method includes:

[0033] When the input end of the low noise amplifier receives a low-power signal, the control circuit power supply and the device working power supply are normally powered, and the first power supply is controlled to output a low level, and the second power supply is controlled to output a high level;

[0034] When the input end of the low noise amplifier receives a high-power signal, the circuit power supply and the device working power supply are controlled to stop supplying power, and the first power supply is controlled to output a high level, and the second power supply is controlled to output a low level.

[0035] It can be seen from the above technical solutions that the present invention has the following advantages:

[0036] By adding a second switching tube and connecting it to the active amplifier tube, the present invention increases the voltage withstand range of the active amplifier tube, reducing the risk of breakdown of the active amplifier tube when the input terminal receives a high-power signal. Furthermore, through the leakage path formed by the first capacitor, the third switching tube, and the second capacitor, most of the power signal flowing back from the output terminal is discharged to ground, further reducing the risk of high-power signals at the output terminal of the low-noise amplifier flowing back to the active amplifier tube, causing breakdown of the active amplifier tube, and thus improving the reliability of the low-noise amplifier. Furthermore, when receiving a low-power signal, the present invention controls the first power supply to a low level, placing the first and third switching tubes in a cutoff region. This allows the input power signal to be amplified by the active amplifier tube before being output to the output terminal of the low-noise amplifier. This improves the reliability of the low-noise amplifier without affecting the performance of the original low-noise amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 Schematic diagram of the existing low noise amplifier structure.

[0039] Figure 2 A schematic diagram of the circuit structure of a low noise amplifier provided in an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the circuit structure of a low noise amplifier provided in another embodiment of the present invention;

[0041] Figure 4A schematic diagram of a control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] An embodiment of the present invention provides a circuit structure of a low noise amplifier, which is used to improve the reliability of the low noise amplifier.

[0043] In order to make the purpose, features, and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0044] See also Figure 1 , Figure 1 A schematic diagram of the circuit structure of a low noise amplifier provided by an embodiment of the present invention.

[0045] The present invention provides a circuit structure of a low-noise amplifier, including a circuit power supply Vbias, a device operating power supply VDD, a resistive alternating current inductor DC_Feed, a first DC blocking capacitor DC_Block1, a second DC blocking capacitor DC_Block2, an input matching network, an output matching network, an active amplifier tube M1, a first resistor R1, a second resistor R2, a first power supply, and a first switch tube SW1. The first end of the input matching network is connected to the input end LNA_IN of the low-noise amplifier, the second end of the input matching network is connected to the first end of the first DC blocking capacitor DC_Block1, the circuit power supply Vbias is connected to the first resistor R1, and is connected to the second end of the first DC blocking capacitor DC_Block1 through the first resistor R1. The first end of the active amplifier tube M1 is connected to the first DC blocking capacitor DC_Block The circuit structure further comprises: a first terminal of the first switching transistor SW1 is connected to the second end of the first resistor R2; a second terminal of the second resistor R2 is connected to the first end of the first switching transistor SW1; a second terminal of the first switching transistor SW1 is connected to the output terminal LNA_OUT of the low noise amplifier; and a third terminal of the first switching transistor SW1 is connected to the input terminal LNA_IN of the low noise amplifier.

[0046] A second power supply, a third resistor R3, a second switch SW2, a first capacitor C1, and a second capacitor C2;

[0047] The second power supply is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the first end of the second switch tube SW2;

[0048] The second end of the second switch tube SW2 is connected to the third end of the active amplifier tube M1;

[0049] The third terminal of the second switch tube SW2 is grounded;

[0050] A first end of the third switch SW3 is connected to the first power supply, a second end of the third switch SW3 is connected to the second end of the first capacitor C1, and a first end of the second capacitor C2 is connected to the first end of the second DC blocking capacitor DC_Block2;

[0051] The third terminal of the third switch tube SW3 is connected to the first terminal of the second capacitor C2;

[0052] A second terminal of the second capacitor C2 is grounded.

[0053] It should be noted that this embodiment provides a circuit structure of a low-noise amplifier, which is an improvement based on the existing circuit structure. The specific improvements are: 1) the active amplifier tube M1 is not directly grounded, but is connected to the second switch tube SW2 and then grounded; 2) a ground path consisting of the first capacitor C1, the third switch tube SW3, and the second capacitor C2 is connected in parallel between the second DC blocking capacitor DC_Block2 and the output terminal LNA_OUT.

[0054] In this embodiment, when the low-noise amplifier input terminal LNA_IN receives a low-power signal, the circuit power supply Vbias and the device operating power supply VDD provide a DC bias voltage for the active amplifier M1, causing the active amplifier M1 to operate in the saturation amplification region. Furthermore, by controlling the first power supply VC1 to output a low level, the first switch SW1 and the third switch SW3 are in the cutoff region. By controlling the second power supply VC2 to output a high level, the second switch SW2 is in the linear resistance region. As a result, the input low-power signal is amplified by the active amplifier M1 and then output to the low-noise amplifier output terminal LNA_OUT.

[0055] When the input terminal LNA_IN of the low noise amplifier receives a high power signal, the circuit power supply Vbias and the device working power supply VDD stop supplying power, so that the active amplifier tube M1 is in the cut-off region, and by controlling the second power supply VC2 to a low level, the second switch tube SW2 is in the cut-off region. At this time, the withstand voltage range of the active amplifier tube M1 is V GSmax +V DSmax , where V GSmaxis the maximum gate-source voltage of M1, V DSmax is the maximum withstand voltage at the drain-source terminal of the second switch SW2. Therefore, this embodiment improves the withstand voltage range of the active amplifier M1 and reduces the risk of breakdown of the active amplifier M1. Furthermore, by controlling the first power supply VC1 to a high level, this embodiment places the first and third switches SW1 and SW3 in a linear resistance region, allowing the input high-power signal to be output to the output terminal LNA_OUT of the low-noise amplifier through the first switch SW1. Furthermore, through the leakage path formed by the first capacitor C1, the third switch SW3, and the second capacitor C2, most of the power signal returning from the output terminal LNA_OUT is discharged to ground, effectively reducing the risk of the high-power signal at the output terminal LNA_OUT of the low-noise amplifier returning to the active amplifier M1 and causing breakdown of the active amplifier M1.

[0056] Therefore, when receiving a high-power signal, this embodiment increases the voltage withstand range of the active amplifier M1 and reduces the risk of breakdown of the active amplifier M1 by adding the second switch SW2 connected to the active amplifier M1. Furthermore, through the leakage path formed by the first capacitor C1, the third switch SW3, and the second capacitor C2, most of the power signal flowing back from the output terminal LNA_OUT is discharged to ground. This further reduces the risk of the high-power signal at the output terminal LNA_OUT of the low-noise amplifier flowing back to the active amplifier M1 and causing breakdown of the active amplifier M1, thereby improving the reliability of the low-noise amplifier. When receiving a low-power signal, this embodiment controls the first power supply VC1 to a low level, placing the first switch SW1 and the third switch SW3 in a cutoff region. This allows the input power signal to be amplified by the active amplifier M1 and then output to the output terminal LNA_OUT of the low-noise amplifier. Therefore, this embodiment improves the reliability of the low-noise amplifier without affecting the original performance of the low-noise amplifier.

[0057] In a preferred embodiment, the low noise amplifier further comprises: an attenuation module;

[0058] The attenuation module is disposed in a path between the first switch tube SW1 and the output terminal LNA_OUT of the low noise amplifier.

[0059] It should be noted that the attenuation module further attenuates high-power signals, thereby reducing the power of the signal reaching the low-noise amplifier's output terminal, LNA_OUT. This prevents excessive signal power at the output terminal, LNA_OUT, from damaging the drain of active amplifier M1 and potentially causing breakdown of the active amplifier. Furthermore, the addition of the attenuation module improves the isolation between the low-noise amplifier's amplification path and the bypass path, further enhancing the reliability of the low-noise amplifier.

[0060] In a preferred embodiment, the attenuation module includes a T-type attenuation network, a fourth resistor R4 and a fourth switch SW4;

[0061] The first end of the T-type attenuation network is connected to the second end of the first switch tube SW1;

[0062] The second end of the T-type attenuation network is connected to the third end of the fourth switch tube SW4;

[0063] A first end of the fourth switch tube SW4 is connected to the second end of the fourth resistor R4, and a first end of the fourth resistor R4 is connected to the first power supply VC1;

[0064] A second end of the fourth switch tube SW4 is connected to the output end LNA_OUT of the low noise amplifier.

[0065] In this embodiment, when the input terminal LNA_IN receives a low-power signal, the circuit power supply Vbias and the device operating power supply VDD provide a DC bias voltage for the active amplifier M1, causing the active amplifier M1 to operate in the saturation amplification region. Furthermore, by controlling the first power supply VC1 to a low level, the first, third, and fourth switches SW1, SW3, and SW4 are in the cutoff region. By controlling the second power supply VC2 to a high level, the second switch SW2 is in the linear resistance region. As a result, the input low-power signal is amplified by the active amplifier M1 and output to the low-noise amplifier's output terminal LNA_OUT.

[0066] In this embodiment, when the input terminal LNA_IN receives a high-power signal, the circuit power supply Vbias and the device operating power supply VDD stop supplying power, so that the active amplifier tube M1 is in the cut-off region, and by controlling the second power supply VC2 to a low level, the second switch tube SW2 is in the cut-off region. At this time, the voltage range of the active amplifier tube M1 is V GSmax +V DSmax , where V GSmax is the maximum gate-source voltage of M1, V DSmaxis the maximum withstand voltage at the drain-source terminal of the second switch SW2. Therefore, this embodiment increases the withstand voltage range of the active amplifier M1 and reduces the risk of breakdown of the active amplifier M1. Simultaneously, the first power supply VC1 is controlled to a high level, placing the first, third, and fourth switches SW1, SW3, and SW4 in the linear resistance region. This allows the input high-power signal to sequentially pass through the first switch SW1, the T-type attenuation network, and the fourth switch SW4 to be output to the output terminal LNA_OUT of the low-noise amplifier. Furthermore, through the leakage path formed by the first capacitor C1, the third switch SW3, and the second capacitor C2, most of the power signal returning from the output terminal LNA_OUT is discharged to ground, effectively reducing the risk of the high-power signal at the output terminal LNA_OUT of the low-noise amplifier returning to the active amplifier M1 and causing breakdown of the active amplifier M1.

[0067] This embodiment further attenuates high-power signals by adding a T-type attenuation network, a fourth switch SW4, and a fourth resistor R4, thereby reducing the power of the signal reaching the low-noise amplifier output terminal LNA_OUT. This prevents excessive signal power at the output terminal LNA_OUT from damaging the drain of the active amplifier M1 and causing breakdown of the active amplifier M1, thereby improving the dynamic range of the LNA circuit. Furthermore, the addition of the fourth switch SW4 and fourth resistor R4 enhances the isolation between the low-noise amplifier's amplification path and the bypass path, further improving the reliability of the low-noise amplifier.

[0068] In a preferred embodiment, the T-type attenuation network includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a third capacitor C3;

[0069] A first end of the fifth resistor R5 is connected to the second end of the first switch tube SW1;

[0070] The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7 respectively;

[0071] The second end of the sixth resistor R6 is connected to the third end of the fourth switch tube SW4;

[0072] The second end of the seventh resistor R7 is connected to the first end of the third capacitor C3;

[0073] A second terminal of the third capacitor C3 is grounded.

[0074] In a preferred embodiment, the second switch tube SW2 is a field effect tube, the first end of the second switch tube SW2 is a gate, the second end is a drain, and the third end is a source.

[0075] In a preferred embodiment, the third switch tube SW3 is a field effect tube, the first end of the third switch tube SW3 is a gate, the second end is a drain, and the third end is a source.

[0076] In a preferred embodiment, the fourth switch tube SW4 is a field effect tube, the first end of the fourth switch tube SW4 is a gate, the second end is a drain, and the third end is a source.

[0077] In a preferred embodiment, the second switch tube SW2 is a PMOS tube.

[0078] In a preferred embodiment, the third switch tube SW3 is a PMOS tube.

[0079] In a preferred embodiment, the fourth switch transistor SW4 is a PMOS transistor.

[0080] In a preferred embodiment, the gate width ratio of the second switch transistor SW2 is 8000:1, and the unit is nm.

[0081] In a preferred embodiment, the value of the third resistor R3 is 20 kΩ.

[0082] In a preferred embodiment, the value of the first capacitor C1 is 3 pF.

[0083] In a preferred embodiment, the value of the second capacitor C2 is 3 pF.

[0084] In a preferred embodiment, the value of the fourth resistor R4 is 20 kΩ.

[0085] In a preferred embodiment, the value of the fifth resistor R5 is 10Ω.

[0086] In a preferred embodiment, the value of the sixth resistor R6 is 10Ω.

[0087] In a preferred embodiment, the value of the seventh resistor R7 is 140Ω.

[0088] In a preferred embodiment, the value of the third capacitor C3 is 2 pF.

[0089] In a preferred embodiment, the gate width ratio of the fourth switch transistor SW4 is preferably 500:1, with the unit being nm.

[0090] In a preferred embodiment, the gate width ratio of the third switch transistor SW3 is preferably 2500:1, with the unit being nm.

[0091] In a preferred embodiment, the value of the first DC blocking capacitor DC_Block1 is 8 pF.

[0092] In a preferred embodiment, the value of the second DC blocking capacitor DC_Block2 is 8 pF.

[0093] In a preferred embodiment, the DC_Feed has a value of 2 nH.

[0094] In a preferred embodiment, the value of the first resistor R1 is 20 kΩ.

[0095] In a preferred embodiment, the value of the second resistor R2 is 20 kΩ.

[0096] In a preferred embodiment, the gate width ratio of the first switch transistor SW1 is 500:1, and the unit is nm.

[0097] In another preferred embodiment, the values ​​of the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the first DC blocking capacitor, the second DC blocking capacitor, and the AC inductor can also be dynamically adjusted based on the above embodiments according to the attenuation requirements and the operating frequencies of the input network and the output network. For example, when the values ​​of the components in the T-type attenuation network remain unchanged, when the attenuation requirement is greater, the gate width ratio of the first switching tube and the gate width ratio of the fourth switching tube are smaller. Therefore, the gate width ratio of the first switching tube and the gate width ratio of the fourth switching tube can be dynamically adjusted according to the simulation results displayed by the simulation software until the attenuation requirement is met.

[0098] See also Figure 4 , Figure 4 A schematic diagram of a control method provided by an embodiment of the present invention.

[0099] This embodiment provides a control method, characterized in that it is applied to the circuit structure of the above embodiment, wherein the method includes:

[0100] 101. When the input end of the low noise amplifier receives a low-power signal, the control circuit power supply and the device working power supply are normally powered, and the first power supply is controlled to output a low level, and the second power supply is controlled to output a high level;

[0101] 102. When the input end of the low noise amplifier receives a high-power signal, the control circuit power supply and the device working power supply stop supplying power, and the first power supply is controlled to output a high level, and the second power supply is controlled to output a low level.

[0102] This embodiment controls the operating states of the circuit power supply, the device power supply, the first power supply, and the second power supply according to the type of signal received at the input end of the low noise amplifier, thereby further improving the reliability of the low noise amplifier.

[0103] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0104] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0105] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A circuit structure of a low-noise amplifier, comprising a circuit power supply, a device operating power supply, an AC-resistance inductor, a first DC-blocking capacitor, a second DC-blocking capacitor, an input matching network, an output matching network, an active amplifier tube, a first resistor, a second resistor, a first power supply, and a first switching tube, wherein a first end of the input matching network is connected to an input end of the low-noise amplifier, a second end of the input matching network is connected to a first end of the first DC-blocking capacitor, the circuit power supply is connected to the first resistor and is connected to the second end of the first DC-blocking capacitor via the first resistor, a first end of the active amplifier tube is connected to the second end of the first DC-blocking capacitor, and a first end of the active amplifier tube is connected to the second end of the first DC-blocking capacitor. The second end is respectively connected to the second end of the AC-resistance inductor and the first end of the output matching network, the first end of the AC-resistance inductor is connected to the device working power supply, the second end of the output matching network is connected to the first end of the second DC-blocking capacitor, the second end of the second DC-blocking capacitor is connected to the output end of the low-noise amplifier, the first power supply is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the first switching tube, the second end of the first switching tube is connected to the output end of the low-noise amplifier, and the third end of the first switching tube is connected to the input end of the low-noise amplifier. The existing circuit structure is characterized in that Also includes: A second power supply, a third resistor, a second switch tube, a first capacitor, and a second capacitor; The second power supply is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first end of the second switch tube; The second end of the second switching tube is connected to the third end of the active amplifier tube; The third terminal of the second switch tube is grounded; A first end of a third switch tube is connected to the first power supply, a second end of the third switch tube is connected to the second end of the first capacitor, and a first end of the second capacitor is connected to the first end of the second DC blocking capacitor; The third terminal of the third switch tube is connected to the first terminal of the second capacitor; The second terminal of the second capacitor is grounded.

2. The circuit structure according to claim 1, wherein: Also includes: Attenuation module; The attenuation module is arranged in a path between the first switch tube and the output end of the low noise amplifier.

3. The circuit structure according to claim 2, wherein: The attenuation module includes: a T-type attenuation network, a fourth resistor and a fourth switch tube; The first end of the T-type attenuation network is connected to the second end of the first switch tube; The second end of the T-type attenuation network is connected to the third end of the fourth switch tube; The first end of the fourth switch is connected to the second end of the fourth resistor, and the first end of the fourth resistor is connected to the first power supply; The second end of the fourth switch tube is connected to the output end of the low noise amplifier.

4. The circuit structure according to claim 3, wherein: The T-type attenuation network includes: a fifth resistor, a sixth resistor, a seventh resistor, and a third capacitor; The first end of the fifth resistor is connected to the second end of the first switch tube; The second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor respectively; The second end of the sixth resistor is connected to the third end of the fourth switch tube; The second end of the seventh resistor is connected to the first end of the third capacitor; A second terminal of the third capacitor is grounded.

5. The circuit structure according to claim 1, wherein: The second switch tube is a field effect tube, the first end of the second switch tube is a gate, the second end is a drain, and the third end is a source.

6. The circuit structure according to claim 1, wherein: The third switch tube is a field effect tube, the first end of the third switch tube is a gate, the second end is a drain, and the third end is a source.

7. The circuit structure according to claim 3, characterized in that: The fourth switch tube is a field effect tube, the first end of the fourth switch tube is a gate, the second end is a drain, and the third end is a source.

8. The circuit structure according to claim 5, characterized in that: The type of the second switch tube includes a PMOS tube.

9. The circuit structure according to claim 6, characterized in that: The type of the third switch tube includes a PMOS tube.

10. A control method, characterized in that: Applied to the circuit structure according to any one of claims 1 to 9, the method comprises: When the input end of the low noise amplifier receives a low-power signal, the control circuit power supply and the device working power supply are normally powered, and the first power supply is controlled to output a low level, and the second power supply is controlled to output a high level; When the input end of the low noise amplifier receives a high-power signal, the circuit power supply and the device working power supply are controlled to stop supplying power, and the first power supply is controlled to output a high level, and the second power supply is controlled to output a low level.

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