A floating dynamic amplifier and charge-sharing based switched-capacitor integrator

Abstract

The application discloses a kind of based on floating space dynamic amplifier and charge sharing's switched capacitor integrator, including the sampling module, integral module and charge sharing module connected in turn, wherein, sampling module is according to from the first enable signal, second enable signal, third enable signal and fourth enable signal from outside in sampling stage collection differential signal from outside, store differential signal, and in integral stage differential signal is output to integral module;Integral module is according to the first enable signal and fourth enable signal control operational amplifier in integral module in sampling stage charging and stop running, in integral stage differential signal is integrated;Charge sharing module is according to from the fifth enable signal from outside, in integral stage integral differential signal is stored and in next sampling stage output.The application is by designing operational amplifier, the circuit structure of charge sharing module and corresponding enable signal, reduce the overall power consumption of device and guarantee the precision of integrator.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a switched capacitor integrator based on a floating dynamic amplifier and charge sharing. Background Technology

[0002] With the increasing application of analog-to-digital converters (ADCs), the performance of ADCs urgently needs to be improved. Switched-capacitor integrators, as an important component of ADCs, especially Delta-Sigma ADCs, can provide a constant analog signal for the ADC during the analog-to-digital encoding process. On the other hand, they can integrate and sum the error voltage, and function as a low-pass filter for the input signal and a high-pass filter for quantization noise, thereby achieving separation of the input signal and quantization noise in the frequency domain. This pushes most of the quantization noise to a higher frequency band, thereby improving the signal-to-noise ratio within the signal bandwidth and significantly improving the accuracy of the ADC results.

[0003] Switched-capacitor integrators require two main characteristics: low power consumption and high accuracy. However, traditional switched-capacitor integrators suffer from two main problems. First, during the sampling phase, no input signal flows into the internal operational amplifier, yet the amplifier continues to operate, introducing additional static power consumption and making it difficult to meet the low-power design requirements of switched-capacitor integrators. Second, during the integration phase, insufficient gain of the internal operational amplifier leads to a decrease in integration accuracy. These issues with traditional switched-capacitor integrators result in low measurement accuracy for analog-to-digital converters (ADCs), limiting their application. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a switched-capacitor integrator based on a floating dynamic amplifier and charge sharing. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A switched-capacitor integrator based on a floating dynamic amplifier and charge sharing includes a sampling module, an integration module, and a charge sharing module connected in sequence, wherein...

[0006] The sampling module is based on the first enable signal Φ1 and the second enable signal Φ from the outside. 1d The third enable signal Φ2 and the fourth enable signal Φ 2d The differential signal is acquired from the outside during the sampling phase, the differential signal is stored, and the differential signal is output to the integration module during the integration phase.

[0007] The integration module is used to integrate the first enable signal Φ1 and the fourth enable signal Φ1. 2dUnder the control of [the system], charging is performed and operation is stopped during the sampling phase, and the differential signal is integrated during the integration phase, and the integrated differential signal is output.

[0008] The charge sharing module is based on a fifth enable signal Φ from the outside. EN The integral differential signal is stored and output during the integration phase, wherein the first enable signal Φ1 and the second enable signal Φ2 are... 1d The third enable signal Φ2 and the fourth enable signal Φ 2d and the fifth enable signal Φ EN The periods are all the same. The first enable signal Φ1 and the third enable signal Φ2 are two-phase non-overlapping clock signals, and the first enable signal Φ1 and the second enable signal Φ2 have the same period. 1d The duty cycles are the same, and the second enable signal Φ 1d The third enable signal Φ2 and the fourth enable signal Φ1 are delayed signals. 2d The duty cycles are the same, and the fourth enable signal Φ 2d It is the delayed signal of the third enable signal Φ2, and the fifth enable signal Φ EN The pulse signal that arrives at the rising edge of the third enable signal Φ2, and the fifth enable signal Φ EN The duty cycle is less than the third enable signal Φ2, when the first enable signal Φ1 and the second enable signal Φ 1d Simultaneously, when both are high, it is the sampling phase; when the third enable signal Φ2 and the fourth enable signal Φ... 2d At the same time, when it is high level, it is the integration phase.

[0009] In one embodiment of the present invention, the integration module includes an operational amplifier FIA, an integrating capacitor C3, and an integrating capacitor C4, wherein the operational amplifier FIA is a floating inverter type dynamic amplifier.

[0010] The integrating capacitor C3 is connected between the non-inverting input and the inverting output of the floating inverter-type dynamic amplifier. The integrating capacitor C4 is connected between the inverting input and the non-inverting output of the floating inverter-type dynamic amplifier. The non-inverting input of the floating inverter-type dynamic amplifier is also connected to the first output of the sampling module. The inverting input of the floating inverter-type dynamic amplifier is connected to the second output of the sampling module. The non-inverting output of the floating inverter-type dynamic amplifier is connected to the first input of the charge-sharing module. The inverting output of the floating inverter-type dynamic amplifier is connected to the second input of the charge-sharing module. The floating inverter-type dynamic amplifier operates according to the first enable signal Φ1 and the fourth enable signal Φ. 2dDuring the sampling phase, charging is performed and operation is stopped. During the integration phase, a differential output voltage is established through the integrating capacitors C3 and C4 to integrate the differential signal from the sampling module and output the integrated differential signal.

[0011] In one embodiment of the present invention, the floating inverter type dynamic amplifier includes a ClassAB-based floating inverter dynamic amplifier and a Cascode-based floating inverter dynamic amplifier connected in sequence, wherein,

[0012] The ClassAB-based floating inverting dynamic amplifier includes: differential input terminal V1, differential input terminal V2, thirteenth control switch K13, fourteenth control switch K14, fifteenth control switch K15, sixteenth control switch K16, seventeenth control switch K17, eighteenth control switch K18, nineteenth control switch K19, twentieth control switch K20, and first floating capacitor C. float1 Class AB output stage operational amplifier A1, Class AB output stage operational amplifier A2, and first load capacitor C L1 Second load capacitor C L2 Differential output terminals V3 and V4, wherein,

[0013] The differential input terminal V1 serves as the non-inverting input terminal, and the differential input terminal V2 serves as the inverting input terminal. Differential input terminal V1 is connected to one end of the thirteenth control switch K13, and differential input terminal V2 is connected to one end of the fourteenth control switch K14. The other ends of the thirteenth and fourteenth control switches K13 and K14 are connected to an external power supply V. CM One end of the nineteenth control switch K19, one end of the twentieth control switch K20, and the first load capacitor C L1 The lower electrode and the second load capacitor C L2 The lower plates are all connected to the power supply V. CM The other ends of the nineteenth control switch K19 and the twentieth control switch K20 are respectively connected to the differential output terminal V3 and the differential output terminal V4, and the first load capacitor C L1 With the second load capacitor C L2 The upper-level board is connected to the differential output terminal V3 and the differential output terminal V4 respectively, and the first floating capacitor C float1 The upper plate is connected to one end of the fifteenth control switch K15 and the seventeenth control switch K17 respectively, and the first floating capacitor C float1The lower plate of the circuit is connected to one end of the sixteenth control switch K16 and the eighteenth control switch K18, respectively. The other end of the fifteenth control switch K15 is connected to the external power supply potential VDD. The other end of the sixteenth control switch K16 is connected to the ground terminal GND. The other end of the seventeenth control switch K17 is connected to the highest potential of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2, respectively. The other end of the eighteenth control switch K18 is connected to the lowest potential of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2, respectively. The input terminals of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2 are connected to the differential input terminal V1 and the differential input terminal V2, respectively. The output terminals of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2 are connected to the differential output terminal V3 and the differential output terminal V4, respectively.

[0014] The floating inverting dynamic amplifier based on the Cascode structure includes a 21st control switch K21, a 22nd control switch K22, a 23rd control switch K23, a 24th control switch K24, a 25th control switch K25, a 26th control switch K26, and a second floating capacitor C. float2 Cascode operational amplifier A3, Cascode operational amplifier A4, differential output V OP and differential output V ON ,in,

[0015] The second floating capacitor C float2 The upper plates are respectively connected to the 21st control switch K21 and the 23rd control switch K23, and the second floating capacitor C float2The lower plates are respectively connected to the 22nd control switch K22 and the 24th control switch K24. The other end of the 21st control switch K21 is connected to the power supply potential VDD. The other end of the 22nd control switch K22 is connected to the ground terminal GND. The other end of the 23rd control switch K23 is connected to the highest potential of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4. The other end of the 24th control switch K24 is respectively connected to the lowest potential of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4. The input terminals of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4 are respectively connected to the differential output terminal V3 and the differential output terminal V4. The output terminals of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4 are respectively connected to the differential output terminal V4. OP and the differential output terminal V ON One end of both the 25th control switch K25 and the 26th control switch K26 is connected to the power supply V. CM The other ends of the 25th control switch K25 and the 26th control switch K26 are respectively connected to the differential output terminal V. ON and the differential output terminal V OP The differential output terminal V ON As the inverting output terminal of the floating inverter type dynamic amplifier, the differential output terminal V OP As the non-inverting output terminal of the aforementioned floating inverter-type dynamic amplifier,

[0016] The thirteenth control switch K13, the fourteenth control switch K14, the fifteenth control switch K15, the sixteenth control switch K16, the nineteenth control switch K19, the twentieth control switch K20, the twenty-first control switch K21, the twenty-second control switch K22, the twenty-fifth control switch K25, and the twenty-sixth control switch K26 receive the first enable signal Φ1 and are turned on during the sampling phase. The first floating capacitor C float1 and the second floating capacitor C float2 When the charge is brought to the same potential as the power supply potential VDD, the seventeenth control switch K17, the eighteenth control switch K18, the twenty-third control switch K23, and the twenty-fourth control switch K24 receive the fourth enable signal Φ. 2d And it is activated during the integration phase.

[0017] In one embodiment of the present invention, the power supply V CMThe voltage value is half of the power supply potential VDD.

[0018] In one embodiment of the present invention, the Class AB-based output operational amplifier A1 includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, an input terminal VIN, and an output terminal VOUT, wherein,

[0019] The source of the first NMOS transistor MN1 is connected to the drain of the third PMOS transistor MP3. The drain of the first NMOS transistor MN1 is connected to both the drain and gate of the second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is also connected to the gate of the third PMOS transistor MP3. The source of the second PMOS transistor MP2 is connected to the source of the second NMOS transistor MN2. The sources of the third PMOS transistor MP3 and the third NMOS transistor MN3 are both connected to the output terminal VOUT. The output terminal VOUT is the output terminal of the ClassAB-based output operational amplifier A1. The second NMOS transistor MN2... The gate of the first NMOS transistor MN1 is connected to the gate of the third NMOS transistor MN3. The gate and drain of the second NMOS transistor MN2 are both connected to the drain of the first PMOS transistor MP1. The source of the first PMOS transistor MP1 is connected to the drain of the third NMOS transistor MN3. The gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are both connected to the input terminal VIN. The input terminal VIN is the input terminal of the ClassAB-based output operational amplifier A1. The source of the first PMOS transistor MP1 is connected to the seventeenth control switch K17. The source of the first NMOS transistor MN1 is connected to the eighteenth control switch K18.

[0020] In one embodiment of the present invention, the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2 have the same structure.

[0021] In one embodiment of the present invention, the Cascode-based operational amplifier A3 includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and an input terminal V. IN and output terminal V OUT ,in,

[0022] The drain of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5. The source of the fourth NMOS transistor MN4 is connected to the twenty-fourth control switch K24. The source of the fifth NMOS transistor MN5 is also connected to the source of the sixth NMOS transistor MN6. The drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6 and the drain of the fifth PMOS transistor MP5. The drain of the fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor MP6. The source of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6. The source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4. The gates of the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are both connected to the input terminal V. IN The input terminal V IN The input terminal of the Cascode-based operational amplifier A3, and the drain and output terminal V of the fifth PMOS transistor MP5 are connected. OUT Connection, the output terminal V OUT The output terminal of the Cascode-based operational amplifier A3 is connected to the source of the fourth PMOS transistor MP4, which is connected to the twenty-third control switch K23. The gates of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are both connected to the differential output terminal V3. The gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 are both connected to the differential output terminal V4.

[0023] In one embodiment of the present invention, the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4 have the same structure.

[0024] In one embodiment of the present invention, the sampling module includes a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, a fifth control switch K5, a sixth control switch K6, a seventh control switch K7, an eighth control switch K8, a first sampling capacitor C1, and a second sampling capacitor C2, wherein,

[0025] One end of the first control switch K1 and one end of the second control switch K2 serve as the input terminals VIP and VIN of the entire switched capacitor integrator, respectively. The other end of the first control switch K1 is connected to one end of the third control switch K3 and one end of the first sampling capacitor C1, respectively. The other end of the second control switch K2 is connected to one end of the fourth control switch K4 and one end of the second sampling capacitor C2, respectively. The other ends of the third control switch K3 and the fourth control switch K4 are both connected to the power supply V. CM The other end of the first sampling capacitor C1 is connected to one end of the fifth control switch K5 and one end of the seventh control switch K7, respectively. The other end of the second sampling capacitor C2 is connected to one end of the sixth control switch K6 and one end of the eighth control switch K8, respectively. The other ends of the fifth control switch K5 and the sixth control switch K6 are both connected to the power supply V. CM The other end of the seventh control switch K7 serves as the first output terminal of the sampling module, connected to the non-inverting input terminal of the floating inverter-type dynamic amplifier. The other end of the eighth control switch K8 serves as the second output terminal of the sampling module, connected to the inverting input terminal of the floating inverter-type dynamic amplifier.

[0026] The first control switch K1 and the second control switch K2 receive the second enable signal Φ 1d The fifth control switch K5 and the sixth control switch K6 receive the first enable signal Φ1. During the sampling phase, the first control switch K1, the second control switch K2, the fifth control switch K5, and the sixth control switch K6 are turned on, and the input terminal VIP and the input terminal VIN acquire and store the differential signal from the outside. The third control switch K3 and the fourth control switch K4 receive the third enable signal Φ2, and the seventh control switch K7 and the eighth control switch K8 receive the fourth enable signal Φ1. 2d During the integration phase, the third control switch K3, the fourth control switch K4, the seventh control switch K7, and the eighth control switch K8 are turned on, and the stored differential signal from the outside is transferred to the integration module.

[0027] In one embodiment of the present invention, the charge sharing module includes a ninth control switch K9, a tenth control switch K10, an eleventh control switch K11, a twelfth control switch K12, a first storage capacitor C5, and a second storage capacitor C6, wherein...

[0028] One end of the ninth control switch K9 serves as the second input terminal of the charge sharing module and is connected to the inverting output terminal of the floating inverter-type dynamic amplifier. One end of the tenth control switch K10 serves as the first input terminal of the charge sharing module and is connected to the non-inverting output terminal of the floating inverter-type dynamic amplifier. The other end of the ninth control switch K9 is connected to one end of the eleventh control switch K11 and the integrating capacitor C3 in the integrating module. The other end of the eleventh control switch K11 is connected to the upper plate of the first storage capacitor C5 and serves as the output terminal VON of the entire switched capacitor integrator. The other end of the tenth control switch K10 is connected to one end of the twelfth control switch K12 and the integrating capacitor C4 in the integrating module. The other end of the twelfth control switch K12 is connected to the lower plate of the second storage capacitor C6 and serves as the output terminal VOP of the entire switched capacitor integrator. The lower plate of the first storage capacitor C5 and the upper plate of the second storage capacitor C6 are both connected to the power supply V. CM Connection, where,

[0029] The ninth control switch K9, the tenth control switch K10, the eleventh control switch K11, and the twelfth control switch K12 receive the control of the fifth enable signal ΦEN, and save the integral differential signal at the end of the integration phase and output it in the next sampling phase.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] 1. The switched-capacitor integrator provided by this invention, through the design of a floating inverter-type dynamic amplifier circuit structure and all enable signals acting on the switched-capacitor integrator, uses a floating capacitor to power the amplifier, so that the switched-capacitor integrator only works during the integration phase. This allows the floating inverter-type dynamic amplifier to stop working during the sampling phase to remove unnecessary static power consumption, consuming very little power to charge the first floating capacitor. The static power consumption during the sampling phase approaches zero, thereby reducing the overall power consumption of the switched-capacitor integrator. This solves the problem in traditional structures where, due to the sampling switch being turned off during the sampling phase, no input signal flows into the internal operational amplifier, but the internal operational amplifier continues to work, resulting in additional static power consumption and excessive power consumption of the switched-capacitor integrator.

[0032] 2. This invention designs a charge-sharing module to receive the fifth enable signal, which can receive and store the integration differential signal in a timely manner at the end of the integration stage and output it in the next sampling stage. This solves the problem of decreased integration accuracy caused by the parasitic capacitance between the non-inverting and inverting input terminals of the floating inverter-type dynamic amplifier due to charge transfer.

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a circuit structure of a switched capacitor integrator based on a floating dynamic amplifier and charge sharing, provided by an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the circuit structure of the floating dynamic amplifier provided in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the circuit structure of the Class AB output operational amplifier A1 provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the circuit structure based on the Cascode operational amplifier A3 provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the enable signal of the control switch provided in an embodiment of the present invention. Detailed Implementation

[0039] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0040] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified. Furthermore, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships commonly used when the product is in use. These are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0041] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0042] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of a switched capacitor integrator based on a floating dynamic amplifier and charge sharing provided by an embodiment of the present invention. The switched capacitor integrator includes a sampling module 10, an integration module 20 and a charge sharing module 30 connected in sequence.

[0044] Specifically, the sampling module 10 uses the first enable signal Φ1 and the second enable signal Φ1 from the outside. 1d The third enable signal Φ2 and the fourth enable signal Φ 2d The differential signal is acquired and stored from the external source during the sampling phase, and then output to the integration module 20 during the integration phase. The first enable signal Φ1 and the second enable signal Φ2 are used in this process. 1d The third enable signal Φ2 and the fourth enable signal Φ 2d The periods are all the same. The first enable signal Φ1 and the third enable signal Φ2 are two-phase non-overlapping clock signals, and the first enable signal Φ1 and the second enable signal Φ2 have the same period. 1d The duty cycles are the same, and the second enable signal Φ 1d The first enable signal Φ1 is a delayed signal, and the third enable signal Φ2 and the fourth enable signal Φ are delayed signals. 2d The duty cycles are the same, and the fourth enable signal Φ 2dIt is a delayed signal of the third enable signal Φ2, when the first enable signal Φ1 and the second enable signal Φ2 are delayed. 1d When both are high, the switched capacitor integrator is in the sampling phase; when the third enable signal Φ2 and the fourth enable signal Φ are high, the integrator is in the sampling phase. 2d At the same time, when it is high level, it is the integration phase.

[0045] Furthermore, the sampling module 10 includes a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, a fifth control switch K5, a sixth control switch K6, a seventh control switch K7, an eighth control switch K8, a first sampling capacitor C1, and a second sampling capacitor C2.

[0046] Specifically, one end of the first control switch K1 and the second control switch K2 serve as the input terminals VIP and VIN of the entire switched capacitor integrator, respectively. The other end of the first control switch K1 is connected to one end of the third control switch K3 and one end of the first sampling capacitor C1, respectively. The other end of the second control switch K2 is connected to one end of the fourth control switch K4 and one end of the second sampling capacitor C2, respectively. The other ends of the third control switch K3 and the fourth control switch K4 are both connected to the power supply V. CM The other end of the first sampling capacitor C1 is connected to one end of the fifth control switch K5 and one end of the seventh control switch K7, respectively. The other end of the second sampling capacitor C2 is connected to one end of the sixth control switch K6 and one end of the eighth control switch K8, respectively. The other ends of the fifth control switch K5 and the sixth control switch K6 are both connected to the power supply V. CM The other end of the seventh control switch K7 serves as the first output terminal of the sampling module 10 and is connected to the non-inverting input terminal of the floating inverter type dynamic amplifier. The other end of the eighth control switch K8 serves as the second output terminal of the sampling module 10 and is connected to the inverting input terminal of the floating inverter type dynamic amplifier.

[0047] In this embodiment, the sampling module 10 is a switched-capacitor integrator, capable of acquiring, storing, and outputting the externally input differential signal to the integration module 20. In this embodiment, the differential signal is a differential AC signal. Specifically, the first control switch K1 and the second control switch K2 receive the second enable signal Φ. 1d The fifth control switch K5 and the sixth control switch K6 receive the first enable signal Φ1. During the sampling phase, the first control switch K1, the second control switch K2, the fifth control switch K5, and the sixth control switch K6 are turned on, and the input terminals VIP and VIN acquire and store the differential signal from the outside. The third control switch K3 and the fourth control switch K4 receive the third enable signal Φ2, and the seventh control switch K7 and the eighth control switch K8 receive the fourth enable signal Φ2. 2dDuring the integration phase, the third control switch K3, the fourth control switch K4, the seventh control switch K7, and the eighth control switch K8 are turned on, and the stored differential signals from the outside are transferred to the integration module 20.

[0048] Integrator module 20 is used for the first enable signal Φ1 and the fourth enable signal Φ 2d Under the control of [the system], charging is performed and operation is stopped during the sampling phase, and the differential signal is integrated during the integration phase, and the integrated differential signal is output.

[0049] Furthermore, the integration module 20 includes an operational amplifier FIA, an integrating capacitor C3, and an integrating capacitor C4, wherein the operational amplifier FIA is a floating inverter type dynamic amplifier. Specifically, the integrating capacitor C3 is connected between the non-inverting input and the inverting output of the floating inverter type dynamic amplifier, and the integrating capacitor C4 is connected between the inverting input and the non-inverting output of the floating inverter type dynamic amplifier. The non-inverting input of the floating inverter type dynamic amplifier is also connected to the first output of the sampling module 10, the inverting input of the floating inverter type dynamic amplifier is connected to the second output of the sampling module 10, the non-inverting output of the floating inverter type dynamic amplifier is connected to the first input of the charge sharing module 30, and the inverting output of the floating inverter type dynamic amplifier is connected to the second input of the charge sharing module 30. The floating inverter type dynamic amplifier is activated according to the first enable signal Φ1 and the fourth enable signal Φ2. 2d During the sampling phase, charging is performed and operation is stopped. During the integration phase, a differential output voltage is established through integrating capacitors C3 and C4 to integrate the differential signal from the sampling module 10 and output the integrated differential signal.

[0050] Further, please see Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of the floating dynamic amplifier provided in an embodiment of the present invention. The floating inverter type dynamic amplifier includes a ClassAB-based floating inverter type dynamic amplifier 201 and a Cascode-based floating inverter type dynamic amplifier 202 connected in sequence.

[0051] Specifically, the ClassAB-based floating inverting dynamic amplifier 201 includes differential input terminal V1, differential input terminal V2, thirteenth control switch K13, fourteenth control switch K14, fifteenth control switch K15, sixteenth control switch K16, seventeenth control switch K17, eighteenth control switch K18, nineteenth control switch K19, twentieth control switch K20, and a first floating capacitor C. float1 Class AB output stage operational amplifier A1, Class AB output stage operational amplifier A2, and first load capacitor C L1Second load capacitor C L2 Differential output terminal V3 and differential output terminal V4.

[0052] Furthermore, differential input V1 serves as the non-inverting input, and differential input V2 serves as the inverting input. Differential input V1 is connected to one end of the thirteenth control switch K13, and differential input V2 is connected to one end of the fourteenth control switch K14. The other ends of the thirteenth and fourteenth control switches K13 and K14 are connected to an external power supply V. CM One end of the nineteenth control switch K19, one end of the twentieth control switch K20, and the first load capacitor C L1 The lower electrode and the second load capacitor C L2 The lower plates are all connected to the power supply V. CM The other ends of the nineteenth control switch K19 and the twentieth control switch K20 are respectively connected to the differential output terminals V3 and V4, and the first load capacitor C L1 With the second load capacitor C L2 The upper-level board is connected to the differential output terminals V3 and V4 respectively, and the first floating capacitor C float1 The upper plates are respectively connected to one end of the fifteenth control switch K15 and the seventeenth control switch K17, and the first floating capacitor C float1 The lower plates are connected to one end of the sixteenth control switch K16 and the eighteenth control switch K18, respectively. The other end of the fifteenth control switch K15 is connected to the external power supply potential VDD. The other end of the sixteenth control switch K16 is connected to the ground terminal GND. The other end of the seventeenth control switch K17 is connected to the highest potential of ClassAB-based operational amplifier A1 and ClassAB-based operational amplifier A2, respectively. The other end of the eighteenth control switch K18 is connected to the lowest potential of ClassAB-based operational amplifier A1 and ClassAB-based operational amplifier A2, respectively. The input terminals of ClassAB-based operational amplifier A1 and ClassAB-based operational amplifier A2 are connected to the differential input terminals V1 and V2, respectively. The output terminals of ClassAB-based operational amplifier A1 and ClassAB-based operational amplifier A2 are connected to the differential output terminals V3 and V4, respectively.

[0053] Preferably, the power supply V CM The voltage value is half the voltage value of the power supply potential VDD, and the power supply V CM It can provide DC bias, enabling the floating inverter type dynamic amplifier to achieve the maximum input voltage swing and output voltage swing, thereby reducing the limitation of the switched capacitor integrator on the input signal amplitude and output signal amplitude.

[0054] It can be seen that after the seventeenth control switch K17 is turned on, the connection node FVDD1 between the seventeenth control switch K17, the highest potential of ClassAB-based output operational amplifier A1, and the highest potential of ClassAB-based output operational amplifier A2 collects data from the first floating capacitor C. float1 The voltage of the upper plate, after the eighteenth control switch K18 is turned on, the connection node FGND1 between the eighteenth control switch K18, the lowest potential of ClassAB output operational amplifier A1, and the lowest potential of ClassAB output operational amplifier A2 collects data from the first floating capacitor C. float1 The voltage of the lower plate.

[0055] Furthermore, the floating inverting dynamic amplifier 202 based on the Cascode structure includes a twenty-first control switch K21, a twenty-second control switch K22, a twenty-third control switch K23, a twenty-fourth control switch K24, a twenty-fifth control switch K25, a twenty-sixth control switch K26, and a second floating capacitor C. float2 Cascode operational amplifier A3, Cascode operational amplifier A4, differential output V OP and differential output V ON .

[0056] Furthermore, the second floating capacitor C float2 The upper plates are respectively connected to the twenty-first control switch K21 and the twenty-third control switch K23, and the second floating capacitor C float2 The lower plates are connected to the twenty-second control switch K22 and the twenty-fourth control switch K24, respectively. The other end of the twenty-first control switch K21 is connected to the power supply potential VDD. The other end of the twenty-second control switch K22 is connected to the ground terminal GND. The other end of the twenty-third control switch K23 is connected to the highest potential of Cascode operational amplifiers A3 and A4, respectively. The other end of the twenty-fourth control switch K24 is connected to the lowest potential of Cascode operational amplifiers A3 and A4, respectively. The input terminals of Cascode operational amplifiers A3 and A4 are connected to the differential output terminals V3 and V4, respectively. The output terminals of Cascode operational amplifiers A3 and A4 are connected to the differential output terminals V3 and V4, respectively. OP and differential output V ON One end of both the twenty-fifth control switch K25 and the twenty-sixth control switch K26 is connected to the power supply V. CM The other ends of the twenty-fifth control switch K25 and the twenty-sixth control switch K26 are respectively connected to the differential output terminal V. ONand differential output V OP Differential output terminal V ON As the inverting output terminal of a floating inverter-type dynamic amplifier, the differential output terminal V OP As the non-inverting output of a floating inverter-type dynamic amplifier.

[0057] It can be seen that after the 23rd control switch K23 is turned on, the connection node FVDD2 between the 23rd control switch K23, the highest potential of the Cascode operational amplifier A3 and the Cascode operational amplifier A4 collects data from the second floating capacitor C. float2 The voltage of the upper plate, after the twenty-fourth control switch K24 is turned on, the connection node FGND2 between the twenty-fourth control switch K24, the lowest potential of the Cascode operational amplifier A3, and the lowest potential of the Cascode operational amplifier A4 collects data from the second floating capacitor C. float2 The voltage of the lower plate.

[0058] In this embodiment, the thirteenth control switch K13, the fourteenth control switch K14, the fifteenth control switch K15, the sixteenth control switch K16, the nineteenth control switch K19, the twentieth control switch K20, the twenty-first control switch K21, the twenty-second control switch K22, the twenty-fifth control switch K25, and the twenty-sixth control switch K26 receive the first enable signal Φ1 and are turned on during the sampling phase. The first floating capacitor C float1 Second floating capacitor C float2 When the charge reaches the same potential as the power supply potential VDD, the seventeenth control switch K17, the eighteenth control switch K18, the twenty-third control switch K23, and the twenty-fourth control switch K24 receive the fourth enable signal Φ. 2d And it is activated during the integration phase.

[0059] Further, please see Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of the ClassAB-based output operational amplifier A1 provided in an embodiment of the present invention. The ClassAB-based output operational amplifier A1 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, an input terminal VIN, and an output terminal VOUT.

[0060] Specifically, the source of the first NMOS transistor MN1 is connected to the drain of the third PMOS transistor MP3. The drain of the first NMOS transistor MN1 is connected to both the drain and gate of the second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is also connected to the gate of the third PMOS transistor MP3. The source of the second PMOS transistor MP2 is connected to the source of the second NMOS transistor MN2. The sources of both the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected to the output terminal VOUT. The output terminal VOUT is the output terminal of the Class AB-based output operational amplifier A1. The gate of transistor MN2 is connected to the gate of the third NMOS transistor MN3. The gate and drain of the second NMOS transistor MN2 are both connected to the drain of the first PMOS transistor MP1. The source of the first PMOS transistor MP1 is connected to the drain of the third NMOS transistor MN3. The gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are both connected to the input terminal VIN. The input terminal VIN is the input terminal of the Class AB output operational amplifier A1. The source of the first PMOS transistor MP1 is connected to the seventeenth control switch K17. The source of the first NMOS transistor MN1 is connected to the eighteenth control switch K18.

[0061] Furthermore, the ClassAB-based output operational amplifier A1 has the same structure as the ClassAB-based output operational amplifier A2.

[0062] Further, please see Figure 4 , Figure 4 This is a schematic diagram of the circuit structure of the Cascode operational amplifier A3 provided in an embodiment of the present invention. The Cascode operational amplifier A3 includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and an input terminal V. IN and output terminal V OUT .

[0063] Specifically, the drain of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5. The source of the fourth NMOS transistor MN4 is connected to the twenty-fourth control switch K24. The source of the fifth NMOS transistor MN5 is also connected to the source of the sixth NMOS transistor MN6. The drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6 and the drain of the fifth PMOS transistor MP5. The drain of the fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor MP6. The source of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6. The source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4. The gates of the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are both connected to the input terminal V. IN Input terminal V IN As the input of Cascode operational amplifier A3, the drain of the fifth PMOS transistor MP5 is connected to the output V. OUT Connection, output terminal V OUT As the output of Cascode operational amplifier A3, the source of the fourth PMOS transistor MP4 is connected to the twenty-third control switch K23, the gates of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are both connected to the differential output terminal V3, and the gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 are both connected to the differential output terminal V4.

[0064] Furthermore, the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4 have the same structure.

[0065] The switched-capacitor integrator provided in this embodiment, through the design of a floating inverter-type dynamic amplifier circuit structure and all enable signals acting on the switched-capacitor integrator, uses a floating capacitor to power the amplifier, enabling the switched-capacitor integrator to operate only during the integration phase. This allows the floating inverter-type dynamic amplifier to stop working during the sampling phase to remove unnecessary static power consumption, consuming very little power to charge the first floating capacitor. The static power consumption during the sampling phase approaches zero, thereby reducing the overall power consumption of the switched-capacitor integrator. This solves the problem in traditional structures where, due to the sampling switch being turned off during the sampling phase, no input signal flows into the internal operational amplifier, yet the internal operational amplifier continues to operate, resulting in additional static power consumption and excessive power consumption of the switched-capacitor integrator.

[0066] Please continue reading Figure 1 The charge sharing module 30 responds to the fifth enable signal Φ from the outside. EN The integral differential signal is stored in the integration phase and output in the next sampling phase, wherein the fifth enable signal ΦEN The frequency of the first enable signal Φ1 and the second enable signal Φ2 is the same as that of the third enable signal Φ2. 1d The third enable signal Φ2 and the fourth enable signal Φ 2d and the fifth enable signal Φ EN The periods are all the same. The fifth enable signal Φ EN The pulse signal is the pulse signal that arrives at the rising edge of the third enable signal Φ2, and the fifth enable signal Φ EN The duty cycle is less than that of the third enable signal Φ2.

[0067] Furthermore, the charge sharing module 30 includes a ninth control switch K9, a tenth control switch K10, an eleventh control switch K11, a twelfth control switch K12, a first storage capacitor C5, and a second storage capacitor C6.

[0068] Furthermore, one end of the ninth control switch K9 serves as the second input terminal of the charge sharing module 30, connected to the inverting output terminal of the floating inverter-type dynamic amplifier. One end of the tenth control switch K10 serves as the first input terminal of the charge sharing module 30, connected to the non-inverting output terminal of the floating inverter-type dynamic amplifier. The other end of the ninth control switch K9 is connected to one end of the eleventh control switch K11 and the integrating capacitor C3 in the integrating module 20. The other end of the eleventh control switch K11 is connected to the upper plate of the first storage capacitor C5 and serves as the output terminal VON of the entire switched capacitor integrator. The other end of the tenth control switch K10 is connected to one end of the twelfth control switch K12 and the integrating capacitor C4 in the integrating module 20. The other end of the twelfth control switch K12 is connected to the lower plate of the second storage capacitor C6 and serves as the output terminal VOP of the entire switched capacitor integrator. The lower plate of the first storage capacitor C5 and the upper plate of the second storage capacitor C6 are both connected to the power supply V. CM connect.

[0069] The ninth control switch K9, the tenth control switch K10, the eleventh control switch K11, and the twelfth control switch K12 receive the fifth enable signal Φ. EN The system controls the process and saves the integral difference signal at the end of the integration phase and outputs it in the next sampling phase.

[0070] The switched capacitor integrator provided in this embodiment stores the correct integrated voltage value in the first storage capacitor C5 and the second storage capacitor C6 after the floating inverter-type dynamic amplifier has completed integration via the charge sharing module 30. The thirteenth control switch K13, fourteenth control switch K14, fifteenth control switch K15, sixteenth control switch K16, nineteenth control switch K19, twentieth control switch K20, twenty-first control switch K21, twenty-second control switch K22, twenty-fifth control switch K25, and twenty-sixth control switch K26 receive the first enable signal Φ1 and are disconnected during the integration phase. The seventeenth control switch K17, eighteenth control switch K18, twenty-third control switch K23, and twenty-fourth control switch K24 receive the fourth enable signal Φ2d and are turned on during the integration phase. The first floating capacitor C... float1 Second floating capacitor C float2 Discharge begins, and ClassAB-based output operational amplifiers A1, A2, A3, and A4 start operating. This is due to the first floating capacitor C... float1 Second floating capacitor C float2 As the voltage across the terminals gradually decreases, if the integration phase takes too long, the internal MOS transistors of ClassAB-based output operational amplifiers A1, A2, A3, and A4 will enter the linear region or even be cut off. This makes it difficult for the floating amplifier to maintain sufficient gain, and consequently, some charge on integrating capacitors C3 and C4 will transfer to the parasitic capacitance between the non-inverting and inverting inputs of the floating inverter-type dynamic amplifier, leading to a decrease in integration accuracy. This embodiment addresses this by designing a charge-sharing module 30 to receive the fifth enable signal Φ. EN It can receive and output the integral differential signal in time at the end of the integration stage, thus solving the problem of decreased integration accuracy caused by the parasitic capacitance between the non-inverting and inverting input terminals of the floating inverter-type dynamic amplifier due to charge transfer.

[0071] Please see Figure 5 , Figure 5 This is a schematic diagram of the enable signal of the control switch provided in an embodiment of the present invention. The enable signal includes the aforementioned first enable signal Φ1 and second enable signal Φ2. 1d Third enable signal Φ2, fourth enable signal Φ 2d and the fifth enable signal Φ EN .

[0072] Specifically, during the sampling phase, the sampling module 10 uses the first enable signal Φ1 and the second enable signal Φ2. 1dThe third enable signal Φ2 and the fourth enable signal Φ 2d Under the control of [unclear], differential signals are acquired. These differential signals are stored in the form of charges in the first sampling capacitor C1 and the second sampling capacitor C2. By designing the circuit structure of the integration module 20, and combining the first enable signal Φ1 and the fourth enable signal Φ [unclear], [unclear] can be used to acquire differential signals. 2d The effect is applied to the integrator module 20, causing the floating inverter-type dynamic amplifier to be inactive at this time, thereby realizing a low-power switched capacitor integrator and reducing the overall power consumption of the switched capacitor integrator.

[0073] To prevent integrator leakage, switched-capacitor integrators typically require high operational amplifier gain. During the integration phase, the first floating capacitor C... float1 Second floating capacitor C float2 Discharge begins, the floating amplifier starts working, and the charge stored in the first sampling capacitor C1 and the second sampling capacitor C2 is transferred to the integrating capacitors C3 and C4. After the floating inverter-type dynamic amplifier starts working, the first floating capacitor C... float1 Second floating capacitor C float2 The voltage across the terminals will gradually decrease as the discharge process progresses. After a period of time, the floating inverter-type dynamic amplifier will no longer meet the operational amplifier gain requirements of the switched capacitor integrator, thus exacerbating the integrator leakage problem. This is especially true when the input signal is a human bioelectric signal with a frequency distribution of 0.5-200Hz. For low-power design considerations, excessively low-frequency input signals limit the integrator from using higher sampling frequencies, thus increasing the operating time of the floating inverter-type dynamic amplifier and further worsening the switched capacitor integrator leakage. To address this problem while achieving a low-power switched capacitor integrator, the switched capacitor integrator provided in this embodiment incorporates a charge-sharing module 30 and a fifth enable signal Φ acting on the charge-sharing module 30. EN This ensures that the integrated voltage value that has not yet leaked is stored in the first storage capacitor C5 and the second storage capacitor C6 after integration is completed. The ninth control switch K9, the tenth control switch K10, the eleventh control switch K11 and the twelfth control switch K12 are disconnected to eliminate the impact of the dynamic amplifier gain drop on the integrating capacitors C3 and C4 and the first and second storage capacitors C5 and C6, thereby ensuring the accuracy of the integrator. In the next sampling stage, the charge stored in the first storage capacitor C5 and the second storage capacitor C6 is transferred to the sampling capacitor of the next stage integrator through charge sharing.

[0074] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A switched-capacitor integrator based on a floating dynamic amplifier and charge sharing, characterized in that, It includes a sampling module (10), an integration module (20), and a charge sharing module (30) connected in sequence, wherein, The sampling module (10) uses the first enable signal Φ1 and the second enable signal Φ1 from the outside. 1d The third enable signal Φ2 and the fourth enable signal Φ 2d During the sampling phase, differential signals from the outside are acquired and stored, and during the integration phase, the differential signals are output to the integration module (20). The integration module (20) is used to integrate the first enable signal Φ1 and the fourth enable signal Φ1. 2d Under the control of [the system], charging is performed and operation is stopped during the sampling phase, and the differential signal is integrated during the integration phase, and the integrated differential signal is output. The charge sharing module (30) responds to a fifth enable signal Φ from the outside. EN The integral differential signal is stored and output during the integration phase, wherein the first enable signal Φ1 and the second enable signal Φ2 are... 1d The third enable signal Φ2 and the fourth enable signal Φ 2d and the fifth enable signal Φ EN The periods are all the same. The first enable signal Φ1 and the third enable signal Φ2 are two-phase non-overlapping clock signals, and the first enable signal Φ1 and the second enable signal Φ2 have the same period. 1d The duty cycles are the same, and the second enable signal Φ 1d The third enable signal Φ2 and the fourth enable signal Φ1 are delayed signals. 2d The duty cycles are the same, and the fourth enable signal Φ 2d It is the delayed signal of the third enable signal Φ2, and the fifth enable signal Φ EN The pulse signal that arrives at the rising edge of the third enable signal Φ2, and the fifth enable signal Φ EN The duty cycle is less than the third enable signal Φ2, when the first enable signal Φ1 and the second enable signal Φ 1d Simultaneously, when both are high, it is the sampling phase; when the third enable signal Φ2 and the fourth enable signal Φ... 2d At the same time, when it is high level, it is the integration phase.

2. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 1, characterized in that, The integration module (20) includes an operational amplifier FIA, an integrating capacitor C3, and an integrating capacitor C4, wherein the operational amplifier FIA is a floating inverter type dynamic amplifier. The integrating capacitor C3 is connected between the non-inverting input and the inverting output of the floating inverter-type dynamic amplifier, and the integrating capacitor C4 is connected between the inverting input and the non-inverting output of the floating inverter-type dynamic amplifier. The non-inverting input of the floating inverter-type dynamic amplifier is also connected to the first output of the sampling module (10), the inverting input of the floating inverter-type dynamic amplifier is connected to the second output of the sampling module (10), the non-inverting output of the floating inverter-type dynamic amplifier is connected to the first input of the charge sharing module (30), and the inverting output of the floating inverter-type dynamic amplifier is connected to the second input of the charge sharing module (30). The floating inverter-type dynamic amplifier is activated according to the first enable signal Φ1 and the fourth enable signal Φ1. 2d During the sampling phase, charging is performed and operation is stopped. During the integration phase, a differential output voltage is established through the integrating capacitor C3 and the integrating capacitor C4 to integrate the differential signal from the sampling module (10) and output the integrated differential signal.

3. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 2, characterized in that, The floating inverter type dynamic amplifier includes a Class AB-based floating inverter type dynamic amplifier (201) and a Cascode-based floating inverter type dynamic amplifier (202) connected in sequence, wherein, The ClassAB-based floating inverting dynamic amplifier (201) includes: differential input terminal V1, differential input terminal V2, thirteenth control switch K13, fourteenth control switch K14, fifteenth control switch K15, sixteenth control switch K16, seventeenth control switch K17, eighteenth control switch K18, nineteenth control switch K19, twentieth control switch K20, and first floating capacitor C. float1 Class AB output stage operational amplifier A1, Class AB output stage operational amplifier A2, and first load capacitor C L1 Second load capacitor C L2 Differential output terminals V3 and V4, wherein, The differential input terminal V1 serves as the non-inverting input terminal, and the differential input terminal V2 serves as the inverting input terminal. Differential input terminal V1 is connected to one end of the thirteenth control switch K13, and differential input terminal V2 is connected to one end of the fourteenth control switch K14. The other ends of the thirteenth and fourteenth control switches K13 and K14 are connected to an external power supply V. CM One end of the nineteenth control switch K19, one end of the twentieth control switch K20, and the first load capacitor C L1 The lower electrode and the second load capacitor C L2 The lower plates are all connected to the power supply V. CM The other ends of the nineteenth control switch K19 and the twentieth control switch K20 are respectively connected to the differential output terminal V3 and the differential output terminal V4, and the first load capacitor C L1 With the second load capacitor C L2 The upper-level board is connected to the differential output terminal V3 and the differential output terminal V4 respectively, and the first floating capacitor C float1 The upper plate is connected to one end of the fifteenth control switch K15 and the seventeenth control switch K17 respectively, and the first floating capacitor C float1 The lower plate of the circuit is connected to one end of the sixteenth control switch K16 and the eighteenth control switch K18, respectively. The other end of the fifteenth control switch K15 is connected to the external power supply potential VDD. The other end of the sixteenth control switch K16 is connected to the ground terminal GND. The other end of the seventeenth control switch K17 is connected to the highest potential of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2, respectively. The other end of the eighteenth control switch K18 is connected to the lowest potential of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2, respectively. The input terminals of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2 are connected to the differential input terminal V1 and the differential input terminal V2, respectively. The output terminals of the ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2 are connected to the differential output terminal V3 and the differential output terminal V4, respectively. The floating inverting dynamic amplifier (202) based on the Cascode structure includes a twenty-first control switch K21, a twenty-second control switch K22, a twenty-third control switch K23, a twenty-fourth control switch K24, a twenty-fifth control switch K25, a twenty-sixth control switch K26, and a second floating capacitor C. float2 Cascode operational amplifier A3, Cascode operational amplifier A4, differential output V OP and differential output V ON ,in, The second floating capacitor C float2 The upper plates are respectively connected to the 21st control switch K21 and the 23rd control switch K23, and the second floating capacitor C float2 The lower plates are respectively connected to the 22nd control switch K22 and the 24th control switch K24. The other end of the 21st control switch K21 is connected to the power supply potential VDD. The other end of the 22nd control switch K22 is connected to the ground terminal GND. The other end of the 23rd control switch K23 is connected to the highest potential of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4. The other end of the 24th control switch K24 is respectively connected to the lowest potential of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4. The input terminals of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4 are respectively connected to the differential output terminal V3 and the differential output terminal V4. The output terminals of the Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4 are respectively connected to the differential output terminal V4. OP and the differential output terminal V ON One end of both the 25th control switch K25 and the 26th control switch K26 is connected to the power supply V. CM The other ends of the 25th control switch K25 and the 26th control switch K26 are respectively connected to the differential output terminal V. ON and the differential output terminal V OP The differential output terminal V ON As the inverting output terminal of the floating inverter type dynamic amplifier, the differential output terminal V OP As the non-inverting output terminal of the aforementioned floating inverter-type dynamic amplifier, The thirteenth control switch K13, the fourteenth control switch K14, the fifteenth control switch K15, the sixteenth control switch K16, the nineteenth control switch K19, the twentieth control switch K20, the twenty-first control switch K21, the twenty-second control switch K22, the twenty-fifth control switch K25, and the twenty-sixth control switch K26 receive the first enable signal Φ1 and are turned on during the sampling phase. The first floating capacitor C float1 and the second floating capacitor C float2 When the charge is brought to the same potential as the power supply potential VDD, the seventeenth control switch K17, the eighteenth control switch K18, the twenty-third control switch K23, and the twenty-fourth control switch K24 receive the fourth enable signal Φ. 2d And it is activated during the integration phase.

4. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 3, characterized in that, The power supply V CM The voltage value is half of the power supply potential VDD.

5. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 3, characterized in that, The Class AB-based operational amplifier A1 includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, an input terminal VIN, and an output terminal VOUT. The source of the first NMOS transistor MN1 is connected to the drain of the third PMOS transistor MP3. The drain of the first NMOS transistor MN1 is connected to both the drain and gate of the second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is also connected to the gate of the third PMOS transistor MP3. The source of the second PMOS transistor MP2 is connected to the source of the second NMOS transistor MN2. The sources of the third PMOS transistor MP3 and the third NMOS transistor MN3 are both connected to the output terminal VOUT. The output terminal VOUT is the output terminal of the ClassAB-based output operational amplifier A1. The second NMOS transistor MN2... The gate of the first NMOS transistor MN1 is connected to the gate of the third NMOS transistor MN3. The gate and drain of the second NMOS transistor MN2 are both connected to the drain of the first PMOS transistor MP1. The source of the first PMOS transistor MP1 is connected to the drain of the third NMOS transistor MN3. The gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are both connected to the input terminal VIN. The input terminal VIN is the input terminal of the ClassAB-based output operational amplifier A1. The source of the first PMOS transistor MP1 is connected to the seventeenth control switch K17. The source of the first NMOS transistor MN1 is connected to the eighteenth control switch K18.

6. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 5, characterized in that, The ClassAB-based output operational amplifier A1 and the ClassAB-based output operational amplifier A2 have the same structure.

7. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 3, characterized in that, The Cascode-based operational amplifier A3 includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and an input terminal V. IN and output terminal V OUT ,in, The drain of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5. The source of the fourth NMOS transistor MN4 is connected to the twenty-fourth control switch K24. The source of the fifth NMOS transistor MN5 is also connected to the source of the sixth NMOS transistor MN6. The drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6 and the drain of the fifth PMOS transistor MP5. The drain of the fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor MP6. The source of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6. The source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4. The gates of the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are both connected to the input terminal V. IN The input terminal V IN The input terminal of the Cascode-based operational amplifier A3, and the drain and output terminal V of the fifth PMOS transistor MP5 are connected. OUT Connection, the output terminal V OUT The output terminal of the Cascode-based operational amplifier A3 is connected to the source of the fourth PMOS transistor MP4, which is connected to the twenty-third control switch K23. The gates of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are both connected to the differential output terminal V3. The gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 are both connected to the differential output terminal V4.

8. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 7, characterized in that, The Cascode-based operational amplifier A3 and the Cascode-based operational amplifier A4 have the same structure.

9. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 8, characterized in that, The sampling module (10) includes a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, a fifth control switch K5, a sixth control switch K6, a seventh control switch K7, an eighth control switch K8, a first sampling capacitor C1, and a second sampling capacitor C2, wherein, One end of the first control switch K1 and one end of the second control switch K2 serve as the input terminals VIP and VIN of the entire switched capacitor integrator, respectively. The other end of the first control switch K1 is connected to one end of the third control switch K3 and one end of the first sampling capacitor C1, respectively. The other end of the second control switch K2 is connected to one end of the fourth control switch K4 and one end of the second sampling capacitor C2, respectively. The other ends of the third control switch K3 and the fourth control switch K4 are both connected to the power supply V. CM The other end of the first sampling capacitor C1 is connected to one end of the fifth control switch K5 and one end of the seventh control switch K7, respectively. The other end of the second sampling capacitor C2 is connected to one end of the sixth control switch K6 and one end of the eighth control switch K8, respectively. The other ends of the fifth control switch K5 and the sixth control switch K6 are both connected to the power supply V. CM The other end of the seventh control switch K7 serves as the first output terminal of the sampling module (10) and is connected to the non-inverting input terminal of the floating inverter-type dynamic amplifier. The other end of the eighth control switch K8 serves as the second output terminal of the sampling module (10) and is connected to the inverting input terminal of the floating inverter-type dynamic amplifier. The first control switch K1 and the second control switch K2 receive the second enable signal Φ 1d The fifth control switch K5 and the sixth control switch K6 receive the first enable signal Φ1. During the sampling phase, the first control switch K1, the second control switch K2, the fifth control switch K5, and the sixth control switch K6 are turned on, and the input terminal VIP and the input terminal VIN acquire and store the differential signal from the outside. The third control switch K3 and the fourth control switch K4 receive the third enable signal Φ2, and the seventh control switch K7 and the eighth control switch K8 receive the fourth enable signal Φ1. 2d During the integration phase, the third control switch K3, the fourth control switch K4, the seventh control switch K7, and the eighth control switch K8 are turned on, and the stored differential signal from the outside is transferred to the integration module (20).

10. The switched capacitor integrator based on a floating dynamic amplifier and charge sharing according to claim 9, characterized in that, The charge sharing module (30) includes a ninth control switch K9, a tenth control switch K10, an eleventh control switch K11, a twelfth control switch K12, a first storage capacitor C5, and a second storage capacitor C6, wherein, One end of the ninth control switch K9 serves as the second input terminal of the charge sharing module (30) and is connected to the inverting output terminal of the floating inverter-type dynamic amplifier. One end of the tenth control switch K10 serves as the first input terminal of the charge sharing module (30) and is connected to the non-inverting output terminal of the floating inverter-type dynamic amplifier. The other end of the ninth control switch K9 is connected to one end of the eleventh control switch K11 and the integrating capacitor C3 in the integrating module (20). The other end of the eleventh control switch K11 is connected to the upper plate of the first storage capacitor C5 and serves as the output terminal VON of the entire switched capacitor integrator. The other end of the tenth control switch K10 is connected to one end of the twelfth control switch K12 and the integrating capacitor C4 in the integrating module (20). The other end of the twelfth control switch K12 is connected to the lower plate of the second storage capacitor C6 and serves as the output terminal VOP of the entire switched capacitor integrator. The lower plate of the first storage capacitor C5 and the upper plate of the second storage capacitor C6 are both connected to the power supply V. CM Connection, where, The ninth control switch K9, the tenth control switch K10, the eleventh control switch K11, and the twelfth control switch K12 receive the fifth enable signal Φ. EN The system controls the process and saves the integral differential signal at the end of the integration phase and outputs it in the next sampling phase.

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