Low-density parity-check code error correction decoding method and device

Abstract

The application provides a low-density parity-check code error correction decoding method and device, wherein the method comprises the following steps: reading data bits and check bits in a flash memory system, and forming a decision vector by combining the data bits and the check bits; checking the decision vector by using a check matrix of a low-density parity-check code, and judging whether to perform iterative error correction on the decision vector according to a check result; and when the check result fails, iteratively correcting the decision vector until the decision vector passes the check or a preset maximum number of iterations is reached. The problem that the bit repeatedly flips in the iteration process in the traditional bit flip decoding algorithm, thereby leading to the decline of decoding performance, is solved.

Description

Low-density parity check code error correction decoding method and device Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically, to a low-density parity check code error correction decoding method and apparatus. Background Technology

[0002] Error-correcting coding techniques are applied in flash memory to correct errors when data is read, thereby improving the reliability of the flash memory and extending its lifespan. Low-density parity-check (LDPC) codes are a class of linear codes defined by sparse parity-check matrices. Under long code lengths, LPC codes employ decoding algorithms based on the belief propagation criterion, which exhibit excellent error-correcting performance. However, these decoding algorithms are relatively complex, making them unsuitable for data storage applications with limited decoding complexity. To address this, the academic community has proposed several low-complexity decoding algorithms, with bit-flipping decoding being an important example. However, these algorithms suffer from repeated bit flipping during iteration, leading to decreased decoding performance and limiting the application of LPC codes in non-volatile storage media. Summary of the Invention

[0003] The main objective of this invention is to provide a low-density parity-check code error correction decoding method and apparatus, so as to at least solve the problem of degradation in decoding performance caused by repeated bit flipping during the iteration process in traditional bit flip decoding algorithms.

[0004] According to one aspect of the present invention, a low-density parity check (LDPC) code error correction decoding method is provided, comprising: reading data bits and parity bits from a flash memory system, and constructing a decision vector from the data bits and parity bits; verifying the decision vector using a parity check matrix of the low-density parity check code, and determining whether to perform iterative error correction on the decision vector based on the verification result; if the verification result fails, iteratively correcting the decision vector until the decision vector passes the verification or reaches a preset maximum number of iterations.

[0005] Furthermore, before reading the data bits and parity bits from the flash memory system, the error correction decoding method also includes: pre-setting array R, array I, parameter α, and parameter K. max Arrays R, I, and parameter α are called during the verification decision vector. Their specific values ​​are related to the parameters of the low-density parity-check code, including parameter K. max The maximum number of iterations is limited; the last component of array R is 0, and the length is L. R Each component of array I is a non-negative integer, corresponding to a bit in the decision vector; parameter α is a positive number; parameter K max It is a positive integer.

[0006] Furthermore, during each iteration of the error correction decision vector, the components of array I are updated. Initially, each component of array I is set to L. R -1.

[0007] Furthermore, the verification decision vector includes: determining whether the syndrome vector obtained by performing modulo-2 multiplication of the parity check matrix and the decision vector of the low-density parity check code is a zero vector; if the syndrome vector is a zero vector, the verification passes, otherwise the verification fails.

[0008] Furthermore, the iterative error correction decision vector includes: calculating the flip indicator function value of each bit in the decision vector, and determining the flip threshold based on the flip indicator function values ​​of all bits; flipping and updating the bits whose flip indicator function values ​​reach the flip threshold, and updating the components of array I corresponding to the bits whose flip indicator function values ​​reach the flip threshold.

[0009] Furthermore, the bit flip indicator function value is the sum of the following three terms: the first term of the bit flip indicator function value is the column inner product of the adjoint vector and the parity check matrix corresponding to the bit; the second term of the bit flip indicator function value is obtained by judging the initial value and the current value of the bit; if the two values ​​are different, then the second term of the bit flip indicator function value is the parameter α, otherwise it is 0; the third term of the bit flip indicator function value is the value of the corresponding array I component of the bit in array R.

[0010] Furthermore, the flip threshold is the maximum value of the flip indicator function for all bits.

[0011] Furthermore, updating the bit whose flip indicator function value reaches the flip threshold includes: performing an XOR operation between the bit and 1; if the bit is 0, then flip and update it to 1; if the bit is 1, then flip and update it to 0.

[0012] Furthermore, updating the components of array I includes setting the components of array I corresponding to the bits whose flip indicator function values ​​reach the flip threshold to 0.

[0013] According to another aspect of the present invention, a low-density parity check (LDPC) code error correction decoding apparatus is provided, comprising: a reading unit for reading data bits and parity bits in a flash memory system and constructing a decision vector from the data bits and parity bits; a verification unit for verifying the decision vector using a parity check matrix of the low-density parity check code; a judgment unit for determining whether to iteratively correct the decision vector based on the verification result; and an error correction unit for iteratively correcting decision vectors that fail the verification until the decision vector passes the verification or reaches a preset maximum number of iterations.

[0014] In this embodiment of the invention, data bits and parity bits from the flash memory system are read and used to form a decision vector. The decision vector is then verified using a low-density parity-check matrix, and the verification result determines whether iterative error correction should be performed. If the verification result fails, the decision vector is iteratively corrected until it passes the verification or reaches a pre-set maximum number of iterations. This solves the problem of reduced decoding performance caused by repeated bit flipping during iteration in traditional bit-flipping decoding algorithms. Attached Figure Description

[0015] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0016] Figure 1 is a flowchart of an optional low-density parity check code error correction and decoding method according to an embodiment of the present invention;

[0017] Figure 2 is a flowchart of another optional low-density parity check code error correction decoding method according to an embodiment of the present invention;

[0018] Figure 3 is a flowchart of an optional verification decision vector according to an embodiment of the present invention;

[0019] Figure 4 is a flowchart of an optional iterative error correction decision vector according to an embodiment of the present invention;

[0020] Figure 5 is a flowchart of an optional low-density parity check code error correction decoding method according to an embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of bit reading in an optional flash memory system according to an embodiment of the present invention;

[0022] Figure 7 is a structural block diagram of a low-density parity check code error correction decoding device according to an embodiment of the present invention.

[0023] Figure 8 is a bit error rate performance diagram after a low-density parity check code error correction decoding, which is an optional embodiment of the present invention. Detailed Implementation Methods

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] This invention provides a low-density parity check code error correction decoding method.

[0026] Furthermore, Figure 1 is a flowchart of a low-density parity check code error correction decoding method that may be selected according to an embodiment of the present invention.

[0027] As shown in Figure 1, the error correction decoding method includes the following steps:

[0028] Step S102: Read the data bits and parity bits in the flash memory system, and combine the data bits and parity bits to form a decision vector;

[0029] Step S104: Use the parity check matrix of the low-density parity check code to check the decision vector, and determine whether to perform iterative error correction on the decision vector based on the check result;

[0030] Step S106: If the verification result fails, iterate the error correction decision vector until the decision vector passes the verification or the preset maximum number of iterations is reached.

[0031] In this embodiment of the invention, data bits and parity bits from the flash memory system are read and used to form a decision vector. The decision vector is then verified using a low-density parity-check matrix, and the verification result determines whether iterative error correction should be performed. If the verification result fails, the decision vector is iteratively corrected until it passes the verification or reaches a pre-set maximum number of iterations. This solves the problem of reduced decoding performance caused by repeated bit flipping during iteration in traditional bit-flipping decoding algorithms.

[0032] Furthermore, Figure 2 is a flowchart of another low-density parity check code error correction decoding method optional according to an embodiment of the present invention.

[0033] As shown in Figure 2, the error correction decoding method includes the following steps:

[0034] Step S202: Pre-define array R, array I, parameter α, and parameter K. max ;

[0035] Step S204: Read the data bits and parity bits in the flash memory system, and combine the data bits and parity bits to form a decision vector;

[0036] Step S206: Use the parity check matrix of the low-density parity check code to check the decision vector, and determine whether to perform iterative error correction on the decision vector based on the check result;

[0037] Step S208: If the verification result fails, iterate the error correction decision vector until the decision vector passes the verification or the preset maximum number of iterations K is reached. max .

[0038] Specifically, the last component of array R is 0, and its length is L. REach component of array I is a non-negative integer, corresponding to a bit in the decision vector. During each iteration of the error correction decision vector, the components of array I are updated. Initially, each component of array I is set to L. R -1; parameter α is a positive number; parameter K max It is a positive integer; arrays R, I, and parameter α are called when verifying the decision vector, and their specific values ​​are related to the parameters of the low-density parity-check code. By setting parameter α, array R, and array I, the phenomenon of repeated bit flipping during the iteration process is suppressed. Simultaneously, by setting parameter K... max Limit the maximum number of iterations.

[0039] Furthermore, Figure 3 is a flowchart of an optional verification decision vector according to an embodiment of the present invention.

[0040] As shown in Figure 3, the verification decision vector includes the following steps:

[0041] Step S302: Determine whether the syndrome vector obtained by performing modulo-2 multiplication of the parity check matrix and the decision vector of the low-density parity check code is a zero vector.

[0042] Step S304: If the adjoint vector is zero, the verification passes; otherwise, the verification fails.

[0043] Specifically, the parity check matrix of a low-density parity check code is usually a sparse matrix, which can be constructed in a certain way, but will not be described in detail here; the modulo-2 multiplication operation is the result of performing a modulo-2 operation on the multiplication result; the parity check matrix is ​​applied to the decision vector, and the parity check result can determine whether there is an error and locate it.

[0044] Furthermore, Figure 4 is a flowchart of an optional iterative error correction decision vector according to an embodiment of the present invention.

[0045] As shown in Figure 4, the iterative error correction decision vector includes the following steps:

[0046] Step S402: Calculate the flip indicator function value for each bit in the decision vector;

[0047] Step S404: Determine the flip threshold based on the flip indicator function values ​​of all bits;

[0048] Step S406: Update the bits whose flip indicator function values ​​have reached the flip threshold by flipping;

[0049] Step S408: Update the components of array I corresponding to the bits whose flip indicator function values ​​reach the flip threshold.

[0050] Specifically, the bit flip indicator function value is the sum of the following three terms: the first term of the bit flip indicator function value is the column inner product of the adjoint vector and the parity check matrix corresponding to the bit; the second term of the bit flip indicator function value is obtained by judging the initial value and the current value of the bit. If the two values ​​are different, the second term of the bit flip indicator function value is the parameter α, otherwise it is 0; the third term of the bit flip indicator function value is the value of the corresponding array I component of the bit in array R.

[0051] The flip threshold is the maximum value of the flip indicator function for all bits. Bits whose flip indicator function values ​​reach the flip threshold are XORed with 1. If the bit is 0, it is flipped and updated to 1; if the bit is 1, it is flipped and updated to 0. The component of array I corresponding to the bit whose flip indicator function value reaches the flip threshold is set to 0. By setting the flip threshold, erroneous bits (those that have reached the flip threshold) can be located and flipped more accurately and efficiently in each iteration, eliminating the need to flip every single bit. This reduces the overall complexity of the iterative error correction decision vector process and improves error correction performance.

[0052] This invention provides a low-density parity-check code error correction and decoding method. In specific implementation, as shown in Figure 5, it is assumed that the code length of the low-density parity-check code used is n, x (k) Given the k-th iteration result of the decision vector, the low-density parity-check code error correction and decoding method proposed in this invention includes the following steps:

[0053] Step S500: Set k = 0, set and read array R, array I, parameter α, and parameter K. max ;

[0054] Step S501: Read the flash memory data bits and parity bits, and combine the data bits and parity bits to form a decision vector x. (0) .

[0055] Step S502: Calculate the adjoint vector s = x (k) ∙H T ; where H is the parity check matrix of the low-density parity check code. Assuming the length of the data bits is m and the length of the parity bits is nm, the parity check matrix of the low-density parity check code is usually a sparse matrix of (nm)×n, which can be constructed according to a certain method. T ∙ denotes matrix transpose; ∙ denotes modulo-2 multiplication, which is the result of performing a modulo-2 operation on the multiplication result.

[0056] Step S503: Determine whether s = 0 is true. If it is true, proceed to step S520; otherwise, proceed to step S504.

[0057] Step S504: Set i = 0.

[0058] Step S505: Update the value of I[i]. Specifically, I[i] = min(I[i], L R -1); where I[i] represents the i-th element of the array I, corresponding to the i-th bit of x (k) , and min represents the minimum value.

[0059] Step S506: Calculate the partial flip indication function value E1[i] of the i-th bit. Specifically, E1[i] = <s, h i >; where h i is the i-th column of the parity-check matrix H, and <,> represents the inner product of two vectors.

[0060] Step S507: Calculate the partial flip indication function value E2[i] of the i-th bit. Specifically, determine whether x i (k) is different from x i (0) . If they are different, then E2[i] = α; otherwise, E2[i] = 0.

[0061] Step S508: Calculate the partial flip indication function value E3[i] of the i-th bit. Specifically, E3[i] = R[I[i]]; where R[I[i]] represents the I[i]-th element of the array R.

[0062] Step S509: Calculate the flip indication function value E[i] of the i-th bit. Specifically, E[i]= E1[i]+ E2[i]+ E3[i].

[0063] Step S510: Determine whether i = n - 1 holds. If not, go to Step S511; otherwise, go to Step S512.

[0064] Step S511: Set i ← i + 1 and go to Step S505.

[0065] Step S512: Calculate the flip threshold T. Specifically, T = max{E[i]: 0 ≤ i < n}; where max represents the maximum value.

[0066] Step S513: Set i = 0.

[0067] Step S514: Update the i-th bit x (k+1) of x (k+1) [i]. Specifically, x (k+1) [i] is obtained from x (k) [i]. If E[i] is equal to T, then x (k+1) [i] = x (k) [i] ⊕ 1; otherwise, x(k+1) [i] = x (k) [i]; where x (k+1) Let be the vector for the (k+1)th iteration. ⊕ represents the XOR operation. If the i-th bit is 0, then flip and update it to 1; if the i-th bit is 1, then flip and update it to 0.

[0068] Step S515: Update I[i]. Specifically, if E[i] equals T, then set the value of I[i] to 0.

[0069] Step S516: Determine whether i = n-1 is true. If not, proceed to step S517; otherwise, proceed to step S518.

[0070] Step S517: Set i ← i + 1, go to step S514.

[0071] Step S518: Determine if K = K max Check if the condition is met. If not, proceed to step S519; otherwise, proceed to step S520.

[0072] Step S519: Set k ← k + 1, then proceed to step S502.

[0073] Step S520: End the decoding process.

[0074] The execution process of the low-density parity check code error correction decoding method of this invention is described in detail below with examples. For convenience, the element indices of vectors and arrays are counted starting from 0.

[0075] Step S500: Set k = 0, set and read array R, array I, parameter α, and parameter K. max Arrays R, I, and parameter α are called during the verification decision vector. Their specific values ​​are related to the parameters of the low-density parity-check code, including parameter K. max The maximum number of iterations is limited; the last component of array R is 0, and the length is L. R For example, if R = [-2,-1,-1,0], then L R =4; Each component of array I is a non-negative integer, corresponding to a bit of the decision vector. Initially, each component of array I is set to L. R -1, for example, L R = 4, then L R -1 = 3; the parameter α is a positive number, for example, α = 1; the parameter K max K is a positive integer, typically... max = 50.

[0076] Step S501: Read the flash memory data bits and parity bits. As shown in Figure 6, the read bit is determined to be 0 or 1 by comparing the read voltage with a threshold voltage. If the read voltage exceeds the set threshold voltage, the read bit is determined to be 1; otherwise, the read bit is determined to be 0. At the same time, the data bits and parity bits are used to form a decision vector x. (0) .

[0077] Step S502: Calculate the adjoint vector s = x (k) ∙H T Where H is the parity check matrix of a low-density parity check code, which is usually a sparse matrix that can be constructed according to a certain method; T represents matrix transpose; ∙ represents modulo-2 multiplication, which is the result of performing a modulo-2 operation on the multiplication result. Equivalently, s[i] is derived from x (k) The value obtained by XORing the product of the elements in the i-th row of matrix H is obtained.

[0078] To more clearly illustrate the above encoding calculation and data storage process, the following matrix will be used as an example for specific description. Assume the matrix...

[0079]

[0080] Given vector x = [1,1,1,0,0,1], then s[0] = (1×1)⊕(1×1)⊕(1×1)⊕(0×0)⊕(0×0)⊕(1×0) = 1⊕1⊕1⊕0⊕0⊕0 = 1, where ⊕ represents the XOR operation. Similarly, s[1], s[2], and s[3] can be obtained, resulting in s = [1,1,0,0].

[0081] Step S503: Determine whether s = 0 is true. If true, exit iterative error correction decoding; otherwise, start iterative error correction decoding.

[0082] Steps S504 to S511 update the value of array I corresponding to each bit in sequence and calculate its flip indicator function value.

[0083] For the i-th bit, the corresponding value of array I is I[i] = min(I[i],L). R -1), that is, take the current value of I[i] and L R -1 is the minimum of the two.

[0084] For the i-th bit, its toggle indicator function value E[i] is E[i] = E

[0085] Specifically, E1[i] = <s, h i >, where h i$h_i$ is the $i$-th column of the parity-check matrix $H$, and $\langle,\rangle$ represents the inner product of two vectors. Still taking the previous matrix $H$ as an example, assume $s = [1,1,0,0]$, then the inner product $\langle s, h_0\rangle=1\times1 + 1\times1+0\times0 + 0\times0 = 2$. Similarly, the inner products of $s$ with the 1st, 2nd, 3rd, 4th columns are all 1, and the inner product of $s$ with the 5th column is 0.

[0086] The value of $E2[i]$ is obtained by judging whether the current value of the $i$-th bit is different from the initial value. If it is different, then $E2[i]=\alpha$; otherwise, $E2[i]=0$. For example, for the $i$-th bit $x$ i (0) $= 0$, $x$ i (k) $= 1$, or $x$ i (0) $= 1$, $x$ i (k) $= 0$, then $E2[i]=\alpha$; $x$ i (0) $= x$ i (k) $= 0$, or $x$ i (0) $= x$ i (k) $= 1$, then $E2[i]=0$.

[0087] $E3[i]=R[I[i]]$, where $R[I[i]]$ represents the $I[i]$-th element of the array $R$. For example, if $R = [-2,-1,-1,0]$ and $I[i]=0$, then $E3[i]= - 2$.

[0088] Step S512: Calculate the flipping threshold $T$, $T=\max\{E[i]:0\leq i\lt n\}$, that is, take the maximum value of each bit flipping indicator function value.

[0089] Steps S513 - S517 perform bit flipping and update the value of the array $I$ corresponding to the flipped bits.

[0090] Assume $x$ (k+1) is the vector in the $(k + 1)$-th iteration, and its $i$-th bit $x$ (k+1) [i] is obtained from $x$ (k) [i]. If $E[i]$ is equal to $T$, $x$ (k+1) [i]=x (k) [i]\(\oplus1\); otherwise $x$ (k+1) [i]=x (k) [i], where $\oplus$ represents the exclusive-or operation. It can be seen that $x$ (k+1) [i] flips the bits in $x$ (k) [i] that satisfy $E[i]$ equal to $T$, that is, if $x$(k) If [i] = 0, then x (k+1) [i]=1; if x (k) If [i] = 1, then x (k+1) [i]=0.

[0091] If the i-th bit is flipped, then update the corresponding I[i]. Specifically, if E[i] equals T, then set the value of I[i] to 0.

[0092] Step S518: Determine if K = K max If the condition is not met, proceed to step S519 for the next iteration of error correction; otherwise, proceed to step S520 to end the iteration of error correction.

[0093] Step S519: Set k ← k + 1, then proceed to step S502.

[0094] Step S520: End the decoding process.

[0095] Figure 7 is a structural block diagram of a low-density parity check code error correction decoding device according to an embodiment of the present invention.

[0096] As shown in Figure 7, the error correction decoding device includes a reading unit, a verification unit, a judgment unit, and an error correction unit. The reading unit reads the data bits and parity bits in the flash memory system and constructs a decision vector from the data bits and parity bits. The verification unit uses the parity check matrix of the low-density parity check code to verify the decision vector. The judgment unit determines whether to perform iterative error correction on the decision vector based on the verification result. The error correction unit iteratively corrects the decision vectors that fail the verification until the decision vector passes the verification or reaches the preset maximum number of iterations.

[0097] In this embodiment of the invention, a reading unit reads data bits and parity bits from the flash memory system and uses them to form a decision vector. A verification unit verifies the decision vector using a low-density parity check matrix. A judgment unit determines whether to iteratively correct the decision vector based on the verification result. An error correction unit iteratively corrects decision vectors that fail the verification until the decision vector passes the verification or reaches a preset maximum number of iterations. This solves the problem of degraded decoding performance caused by repeated bit flipping during iteration in traditional bit-flipping decoding algorithms.

[0098] Furthermore, Figure 8 shows the bit error rate (BER) performance of the low-density parity check (LDPC) code in the flash memory system under different original error rates p, obtained by using the LDPC error correction and decoding method of this embodiment. The BER of this LDPC code is 1024 bits long and has a code rate of 0.91.

[0099] It can be seen that the bit error rate after decoding using the low-density parity-check code error correction decoding method of this invention is reduced. For example, when p = 10 -4 Under these conditions, the bit error rate after decoding decreased by at least two orders of magnitude.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-density parity-check code error correction decoding method, characterized in that, include: Read the data bits and parity bits from the flash memory system, and combine the data bits and the parity bits to form a decision vector; The decision vector is verified using the parity-check matrix of a low-density parity-check code, and iterative error correction is performed on the decision vector based on the verification result. If the verification result fails, the decision vector is iteratively corrected until it passes the verification or reaches a preset maximum number of iterations. Arrays R, I, α, and Kmax are preset. Arrays R, I, and α are called during the verification of the decision vector, and their specific values ​​are related to the parameters of the low-density parity-check code. Parameter Kmax limits the maximum number of iterations. Array R has a last component of 0 and a length of LR. Each component of array I is a non-negative integer, corresponding to one bit of the decision vector. Parameter α is a positive number. Parameter Kmax is a positive integer. The result is obtained by performing a modulo-2 multiplication of the parity-check matrix of the low-density parity-check code and the decision vector. The check is performed to determine if the adjoint vector is zero. If the adjoint vector is zero, the check passes; otherwise, the check fails. The flip indicator function value for each bit in the decision vector is calculated, and a flip threshold is determined based on the flip indicator function values ​​of all bits. Bits whose flip indicator function values ​​reach the flip threshold are flipped and updated, and the components of array I corresponding to the bits whose flip indicator function values ​​reach the flip threshold are updated. The first term of the bit flip indicator function value is the column inner product of the adjoint vector and the check matrix corresponding to the bit. The second term of the bit flip indicator function value is obtained by judging the initial value and the current value of the bit. If the two values ​​are different, the second term of the bit flip indicator function value is the parameter α; otherwise, it is 0. The third term of the bit flip indicator function value is the value at the corresponding position extracted from array R by using the component of array I as the index value.

2. The low-density parity-check code error correction decoding method according to claim 1, characterized in that, During each iteration of the error correction of the decision vector, the components of array I are updated. Initially, each component of array I is set to LR-1.

3. The low-density parity-check code error correction decoding method according to claim 1, characterized in that, The flip threshold is the maximum value of the flip indicator function for all bits.

4. The low-density parity-check code error correction decoding method according to claim 1, characterized in that, Updating a bit whose flip indicator function value reaches the flip threshold includes: performing an XOR operation on the bit and 1; if the bit is 0, then flip and update it to 1; if the bit is 1, then flip and update it to 0.

5. The low-density parity-check code error correction decoding method according to claim 1, characterized in that, Updating the components of array I includes setting the components of array I corresponding to the bits whose flip indicator function values ​​reach the flip threshold to 0.

6. A low-density parity-check code error correction decoding device, characterized in that, The error correction decoding device uses the low-density parity check code error correction decoding method according to any one of claims 1 to 5. The error correction decoding device includes: a reading unit, which reads data bits and parity bits from the flash memory system and constructs a decision vector from the data bits and the parity bits; a verification unit, which verifies the decision vector using the parity check matrix of the low-density parity check code; a judgment unit, which determines whether to iteratively correct the decision vector based on the verification result; and an error correction unit, which iteratively corrects the decision vectors whose verification results fail, until the decision vectors pass the verification or reach a preset maximum number of iterations.

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