A SerDes high-speed communication system based on domestically produced FPGA

Abstract

This invention relates to a high-speed SerDes communication system based on a domestically produced FPGA, belonging to the field of SerDes communication technology. The system of this invention includes the following components: an FPGA logic design module, a transmitting module, a receiving module, a clock management module, a differential serial data interface, and a differential clock interface. The FPGA logic design module, transmitting module, receiving module, and clock processing module are all implemented using an FPGA. The technical solution proposed in this invention enables high-speed SerDes data communication on a domestically produced FPGA platform, meeting application requirements. Unlike the commonly used 8B / 10B encoding scheme in existing technologies, the 64B / 66B encoding method adopted in this invention effectively improves data transmission efficiency and has greater advantages in high-speed data transmission application environments. This invention simplifies the 64B / 66B encoding design, with related functions implemented by IP cores and custom logic, effectively saving costs and development time.

Description

Technical Field

[0001] This invention belongs to the field of SerDes communication technology, specifically relating to a high-speed SerDes communication system based on a domestically produced FPGA. Background Technology

[0002] With the continuous development of fields such as spaceborne communication and radar testing, the demand for high-speed data acquisition technology is constantly increasing. Traditional parallel interface designs, due to problems such as clock synchronization, line loss, and signal crosstalk, are no longer able to meet the ever-increasing data transmission rates. High-speed serial transmission technology has advantages such as high bandwidth, low latency, good signal integrity, and strong scalability, and has been widely used in applications requiring high-speed, intensive computing, such as digital signal processing and high-speed data processing. A typical implementation scheme is the SerDes communication scheme. SerDes' advantages lie in its high bandwidth, fewer pins, and support for multiple mainstream interfaces, such as RapidIO, FC, PCIe, SATA, and XAUI.

[0003] Line encoding is essential in SerDes data transmission applications. Currently, 8B / 10B and 64B / 66B encodings are commonly used. 8B / 10B encoding can achieve functions such as DC balancing, clock embedding, and control character embedding, but it suffers from significant bandwidth loss. 64B / 66B encoding overcomes this bandwidth loss drawback and is suitable for higher-speed communication. Generally, 64B / 66B encoding uses a lookup table-based encoding method, which consumes considerable FPGA logic resources.

[0004] FPGA chips have a short development cycle and high flexibility. FPGA-based system design and verification have advantages such as high stability, low cost, and fast processing speed. FPGA has become an ideal connection platform for realizing serial interface applications. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] The technical problem to be solved by this invention is how to provide a high-speed SerDes communication system based on domestically produced FPGA, so as to solve the problem that traditional parallel interface design is unable to meet the ever-increasing data transmission rate due to problems such as clock synchronization, line loss and signal crosstalk.

[0007] (II) Technical Solution

[0008] To address the aforementioned technical issues, this invention proposes a SerDes high-speed communication system based on a domestically produced FPGA. This system includes an FPGA logic design module, a transmitting module, a receiving module, a clock management module, a differential serial data interface, and a differential clock interface; wherein the FPGA logic design module, transmitting module, receiving module, and clock processing module are all implemented using FPGA.

[0009] The differential serial data interface is a SerDes-based fiber optic interface that runs serialized high-speed fiber optic data.

[0010] The clock management module is responsible for generating the clock signals required by each module and managing the phase relationship between these clocks;

[0011] Both the transmitting module and the receiving module consist of a PCS layer and a PMA layer.

[0012] In the transmission module, the TX PCS layer includes: an encoding module (TX Gearbox Block), a phase compensation FIFO, and a polarity control module for the transmitter (TX Polarity); the TX PMA layer includes: a parallel-to-serial conversion module (PISO), a transmission equalizer, and a transmitter.

[0013] The encoding module provides an effective combination of synchronization header and data for 64B / 66B encoding, and simultaneously performs scrambling on the transmitted data;

[0014] The phase compensation FIFO is used for rate and phase matching between the parallel clock domains of the TX PMA and the transmit TX PCS.

[0015] The polarity control module of the transmitting end is an optional module, used to drive the structured user interface to a high level to flip the data polarity;

[0016] The parallel / serial conversion module is responsible for converting the parallel data inside the FPGA into serial data through the SerDes interface.

[0017] The function of the transmit equalizer is to compensate for the non-ideal characteristics of the channel;

[0018] In the receiving module, the RX PCS layer includes: a decoding module (RX Gearbox Block), an elastic buffer FIFO, and a polarity control module for the receiver (RX Polarity); the RX PMA layer includes: a serial-to-parallel conversion module (SIPO), a clock data recovery module (CDR), a receiver equalizer, and a receiver.

[0019] The receiver equalizer of the receiving module is responsible for equalizing channel loss.

[0020] The clock data recovery module (CDR) extracts the clock and data from the data stream. When the data passes through, it captures the frequency of the data edge transitions to obtain the clock frequency and finds the optimal sampling point.

[0021] The serial-to-parallel conversion module is responsible for converting the serial data from the SerDes interface into parallel data within the FPGA.

[0022] The polarity control module of the receiving end is an optional module, used to drive the structured user interface to a high level to flip the data polarity;

[0023] The receiver has two different clock domains: a local clock domain and a clock domain recovered from the CDR. The elastic buffer FIFO is used to resolve the differences between the data in the two different clock domains, match the frequency and phase between the two clock domains, and complete clock correction and channel bonding.

[0024] The decoding module effectively separates the synchronization header and data for 64B / 66B decoding, and simultaneously completes the descrambling of the transmitted data.

[0025] (III) Beneficial Effects

[0026] This invention proposes a high-speed SerDes communication system based on a domestically produced FPGA. The technical solution proposed in this invention realizes high-speed SerDes data communication on a domestically produced FPGA platform, meeting the application requirements.

[0027] Unlike the 8B / 10B encoding scheme commonly used in existing technologies, the 64B / 66B encoding method used in this invention can effectively improve data transmission efficiency and has more advantages in high-speed data transmission application environments.

[0028] This invention simplifies the 64B / 66B encoding design, with related functions implemented by IP cores and custom logic, effectively saving costs and development time. Attached Figure Description

[0029] Figure 1 The SerDes communication system architecture and data transmission / reception flowchart designed for this invention are shown below.

[0030] Figure 2 The data encoding process designed for transmission in this invention;

[0031] Figure 3 The data decoding process designed for this invention. Detailed Implementation

[0032] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0033] The technical problem to be solved by this invention is: how to design a high-speed SerDes communication system and method on a domestic platform.

[0034] This invention provides a SerDes high-speed communication system based on a domestically produced FPGA, which is responsible for realizing data interaction between the interface and the data processing module inside the FPGA.

[0035] The line coding mechanism selected in this invention is the 64B / 66B encoding / decoding protocol. This mechanism transforms the input raw data into a format receivable by the receiver, providing a method for aligning data to words and ensuring sufficient high / low level switching for the clock recovery circuit while maintaining good DC balance. The 64B / 66B encoding / decoding technology is a scrambling-based encoding / decoding method, a standard encoding method recommended by IEEE for 10G communication. This protocol encodes 64 bits of data or control information plus a 2-bit synchronization header into a 66-bit block for transmission, ensuring DC balance, guaranteeing correct clock recovery from the data stream, and effectively reducing the overhead of 8B / 10B encoding, making it suitable for higher-speed transmission environments. In addition to the synchronization header, data scrambling must be performed before transmission, i.e., rearranging or encoding the data to optimize its distribution, maximizing the randomness of "0"s and "1"s, and eliminating other sequences that negatively impact the receiver's reception capability, further mitigating jitter and intersymbol interference, and improving data reliability.

[0036] refer to Figure 1 The measurement system of this invention mainly includes the following parts: an FPGA logic design module, a transmitting module, a receiving module, a clock management module, a differential serial data interface, and a differential clock interface. The FPGA logic design module, transmitting module, receiving module, and clock processing module are all implemented using FPGA. The domestic FPGA platform selected in this embodiment is the Fudan Micro 7V690T series FPGA, which has 80 GTH high-speed serial transceivers.

[0037] In this invention, the differential serial data interface is a SerDes-based fiber optic interface that runs serialized high-speed fiber optic data.

[0038] In this invention, the clock management module is responsible for generating the clock signals required by each module and managing the phase relationship between these clocks. The clock source is a differential clock provided externally.

[0039] In this invention, both the transmitting module and the receiving module consist of a PCS layer and a PMA layer. The PCS layer performs parallel digital signal processing and belongs to the logic layer, primarily implemented by FPGA logic. The PMA layer performs serial-to-parallel conversion and analog circuitry and belongs to the physical layer, primarily implemented by the FPGA's built-in circuitry.

[0040] like Figure 1 As shown, the TX PCS layer in the transmission module includes: an encoding module (TX GearboxBlock), a phase compensation FIFO, and a polarity control module for the transmitter (TX Polarity). The TX PMA layer includes: a parallel-to-serial conversion module (PISO), a transmission equalizer, and a transmitter.

[0041] The encoding module provides an effective combination of synchronization header and data for 64B / 66B encoding, and simultaneously performs scrambling on the transmitted data. The encoding module includes a transmit gearbox (TX Gearbox) and a scrambler. The gearbox is a transmission mechanism that enables conversion between arbitrary data bit widths, supporting 2-byte, 4-byte, and 8-byte interface definitions. In this embodiment, the transmit gearbox (TX Gearbox) implements the data bit width conversion from 8 bytes to 4 bytes, and the scrambler is implemented using FPGA logic. The operation of the encoding module in this embodiment is as follows: Figure 2 As shown.

[0042] The phase compensation FIFO is used for rate and phase matching between the parallel clock domains of the TX PMA and the transmit TX PCS.

[0043] The polarity control module at the transmitting end is an optional module. This function is driven high by the structured user interface to toggle the data polarity. This module is not used in one embodiment.

[0044] The parallel / serial conversion module is responsible for converting the parallel data inside the FPGA into serial data through the SerDes interface.

[0045] The function of a transmit equalizer is to compensate for the non-ideal characteristics of the channel, ensuring signal integrity and thus supporting higher speed and longer distance serial data transmission. Equalizers include feed-forward equalizers (FFE), linear equalizers, and decision feedback equalizers (DFE). The transmit equalizer typically uses an FFE structure to compensate for channel-induced signal degradation.

[0046] like Figure 1 As shown, the receiving module includes the following components: the RX PCS layer comprises a decoding module (RX Gearbox Block), a flexible buffer FIFO, and a receiver polarity control module (RX Polarity). The RX PMA layer comprises a serial-to-parallel conversion module (SIPO), a clock data recovery module (CDR), a receiver equalizer, and a receiver.

[0047] The receiver module's receiver equalizer adopts a DFE structure, which is more suitable for high-speed SerDes application scenarios and is responsible for equalizing channel loss.

[0048] The clock data recovery module (CDR) extracts the clock and data from the data stream. As the data passes through, it captures the frequency of the data edge transitions to obtain the clock frequency and finds the optimal sampling point.

[0049] The serial-to-parallel conversion module is responsible for converting the serial data from the SerDes interface into parallel data within the FPGA.

[0050] The polarity control module at the receiving end is an optional module, and its function is the same as that at the transmitting end. This module is not used in this embodiment.

[0051] The receiver operates in two distinct clock domains: a local clock domain and a clock domain recovered from the CDR. The elastic buffer FIFO is used to resolve the differences between the two clock domains, match the frequency and phase between the two clock domains, and perform clock correction and channel bonding.

[0052] The decoding module performs effective separation of the synchronization header and data for 64B / 66B decoding, and simultaneously completes the descrambling of the transmitted data. The decoding module includes a descrambler and a receiving gearbox (RX Gearbox). The descrambler is implemented using FPGA logic, and the receiving gearbox (RX Gearbox) performs data width conversion from 8 bytes to 4 bytes. The operation of the decoding module in this embodiment is as follows: Figure 3 As shown.

[0053] In this embodiment, the user data bit width is set to 32 bits, the internal bit width is 32 bits, the transmission method is little endian transmission, and no polarity conversion is required.

[0054] The characteristic polynomial of the scrambler used in this embodiment for 64B / 66B encoding and decoding is G(x) = x. 58 +x 39 +1, the descrambling coder uses the same polynomial. In this embodiment, to simplify the transmission and encoding process, the data packet does not contain control information; a synchronization header is generated based on whether the data is valid.

[0055] This embodiment uses a custom data format for transmission. A data status flag, TXDATAVALID, is set in the user data. During data transmission, if the data status is invalid (TXDATAVALID = 0), this portion of data can be discarded without encoding, and the data can be directly set to 32'hBCBCBCBC, effectively saving FPGA logic resources. The synchronization header definition is shown in Table 1:

[0056] Table 1

[0057] TXDATAVALID Sync header Data types 1 01 Data valid 0 10 idle

[0058] The encoding and transmission process of the data sent in this embodiment is as follows:

[0059] Reference Figure 1 The user interface data TXD is 32-bit custom fiber optic data, a data packet generated by the FPGA's internal logic. (Refer to...) Figure 2 Two valid 32-bit interface data are encoded to obtain data D0-D7. D0-D7 is then scrambled by a scrambler to obtain scrambled data S0-S7. This scrambled data is then merged with the sync header to generate a 66-bit transport block. After processing by the Gearbox, 32-bit encoded data TX_DATA is obtained and sent to the internal interface of the PCS layer of the transmitting module. Then, it is referenced... Figure 1 After passing through a phase-compensated FIFO, a parallel-to-serial conversion is performed to obtain a high-speed serial bit stream containing clock information. After passing through a transmit equalizer, the high-speed serial bit stream is sent by the transmitter to the external SerDes interface.

[0060] The decoding and transmission process of received data in this embodiment is as follows:

[0061] Reference Figure 1 The receiver receives the high-speed serial data stream from the SerDes interface. After passing through the receive equalizer, the clock data recovery module recovers the valid data and clock signals. Driven by this clock signal, the serial-to-parallel conversion module converts it into 32-bit parallel data, which is then sent to the internal interface of the PCS layer of the receiving module via a flexible buffer FIFO. (Refer to...) Figure 3 The internal interface data and synchronization header are synchronized by the Gearbox, and then descrambled by the descrambler and decoded in 64B / 66B to obtain separate 32-bit user interface data and synchronization header, which are then sent to the FPGA internal logic for data processing and interaction.

[0062] The above-described embodiments are merely one implementation of the present invention, and the present invention is also applicable to other communication application scenarios based on the SerDes interface and other data formats.

[0063] The technical solution proposed in this invention enables high-speed SerDes data communication on a domestic FPGA platform, meeting application requirements.

[0064] Unlike the 8B / 10B encoding scheme commonly used in existing technologies, the 64B / 66B encoding method used in this invention can effectively improve data transmission efficiency and has more advantages in high-speed data transmission application environments.

[0065] This invention simplifies the 64B / 66B encoding design, with related functions implemented by IP cores and custom logic, effectively saving costs and development time.

[0066] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A SerDes high-speed communication system based on a domestically produced FPGA, characterized in that, The system includes an FPGA logic design module, a transmitting module, a receiving module, a clock management module, a differential serial data interface, and a differential clock interface; among them, the FPGA logic design module, the transmitting module, the receiving module, and the clock processing module are all implemented by FPGA. The differential serial data interface is a SerDes-based fiber optic interface that runs serialized high-speed fiber optic data. The clock management module is responsible for generating the clock signals required by each module and managing the phase relationship between these clocks; Both the transmitting module and the receiving module consist of a PCS layer and a PMA layer. In the transmission module, the TX PCS layer includes: an encoding module (TX Gearbox Block), a phase compensation FIFO, and a polarity control module for the transmitter (TX Polarity); the TX PMA layer includes: a parallel-to-serial conversion module (PISO), a transmission equalizer, and a transmitter. The encoding module provides an effective combination of synchronization header and data for 64B / 66B encoding, and simultaneously performs scrambling on the transmitted data; The phase compensation FIFO is used for rate and phase matching between the parallel clock domains of the TX PMA and the transmit TX PCS. The polarity control module of the transmitting end is an optional module, used to drive the structured user interface to a high level to flip the data polarity; The parallel / serial conversion module is responsible for converting the parallel data inside the FPGA into serial data through the SerDes interface. The function of the transmit equalizer is to compensate for the non-ideal characteristics of the channel; In the receiving module, the RX PCS layer includes: a decoding module (RX Gearbox Block), an elastic buffer FIFO, and a polarity control module for the receiver (RX Polarity); the RX PMA layer includes: a serial-to-parallel conversion module (SIPO), a clock data recovery module (CDR), a receiver equalizer, and a receiver. The receiver equalizer of the receiving module is responsible for equalizing channel loss. The clock data recovery module (CDR) extracts the clock and data from the data stream. When the data passes through, it captures the frequency of the data edge transitions to obtain the clock frequency and finds the optimal sampling point. The serial-to-parallel conversion module is responsible for converting the serial data from the SerDes interface into parallel data within the FPGA. The polarity control module of the receiving end is an optional module, used to drive the structured user interface to a high level to flip the data polarity; The receiver has two different clock domains: a local clock domain and a clock domain recovered from the CDR. The elastic buffer FIFO is used to resolve the differences between the data in the two different clock domains, match the frequency and phase between the two clock domains, and complete clock correction and channel bonding. The decoding module effectively separates the synchronization header and data for 64B / 66B decoding, and simultaneously completes the descrambling of the transmitted data.

2. The SerDes high-speed communication system based on domestically produced FPGA as described in claim 1, characterized in that, The PCS layer function is parallel digital signal processing, which belongs to the logic layer and is implemented by FPGA logic.

3. The SerDes high-speed communication system based on domestically produced FPGA as described in claim 1, characterized in that, The PMA's functions are: serial-to-parallel conversion and analog section, belonging to the physical layer, and implemented by the FPGA's built-in circuitry.

4. The SerDes high-speed communication system based on domestically produced FPGA as described in claim 1, characterized in that, The encoding module includes a transmission gearbox (TX Gearbox) and a scrambler. The transmission gearbox (TX Gearbox) performs data bit width conversion from 8 bytes to 4 bytes, and the scrambler is implemented by FPGA logic.

5. The SerDes high-speed communication system based on domestically produced FPGA as described in claim 1, characterized in that, The transmit equalizer adopts a feed-forward equalization (FFE) structure, which is responsible for compensating for the damage to the signal caused by the channel.

6. The SerDes high-speed communication system based on domestically produced FPGA as described in claim 1, characterized in that, The receiver module's receiver equalizer adopts a decision feedback equalizer (DFE) structure.

7. The SerDes high-speed communication system based on domestically produced FPGA as described in claim 1, characterized in that, The decoding module includes a descrambler and an RX gearbox. The descrambler is implemented by FPGA logic, and the RX gearbox performs data bit width conversion from 8 bytes to 4 bytes.

8. The SerDes high-speed communication system based on a domestically produced FPGA as described in any one of claims 1-7, characterized in that, The encoding and transmission process of the transmitted data is as follows: The user interface data TXD is 32-bit custom fiber optic data, which is a data packet generated by the internal logic of the FPGA; two valid 32-bit interface data are encoded to obtain data D0-D7. D0-D7 is scrambled by a scrambler to obtain scrambled data S0-S7. The sync header is then merged with it to generate a 66-bit transport block. After being processed by the Gearbox, 32-bit encoded data TX_DATA is obtained and sent to the internal interface of the PCS layer of the transmitting module. After passing through the phase compensation FIFO, the parallel-to-serial conversion is performed to obtain a high-speed serial bit stream containing clock information. After passing through the transmitting equalizer, the transmitter sends the high-speed serial bit stream to the external SerDes interface. The decoding and transmission process of received data is as follows: The receiver receives the high-speed serial data stream from the SerDes interface. After passing through the receive equalizer, the clock data recovery module recovers the valid data and clock signals. Driven by the clock signal, the serial-to-parallel conversion module converts the data into 32-bit parallel data, which is then sent to the internal interface of the PCS layer of the receiving module through the elastic buffer FIFO. The internal interface data and synchronization header are synchronized by the Gearbox. The data is then descrambled by the descrambler and decoded in 64B / 66B to obtain the separated 32-bit user interface data and synchronization header, which are then sent to the internal logic of the FPGA for data processing and interaction.

9. The SerDes high-speed communication system based on domestically produced FPGA as described in claim 8, characterized in that, The characteristic polynomial of the scrambler for 64B / 66B codecs is G(x) = x 58 +x 39 +1, the descrambler uses the same polynomial; the data packet does not contain control information, and a synchronization header is generated based on whether the data is valid.

10. The SerDes high-speed communication system based on a domestically produced FPGA as described in claim 8, characterized in that, The user data has a bit width of 32 bits, and the internal bit width is also 32 bits. The transmission mode is little-endian and no polarity conversion is required. The data status flag TXDATAVALID is set in the user data. During the data transmission process, if the data status is invalid, i.e., TXDATAVALID = 0, the data can be discarded without encoding and the data can be directly set to 32'hBCBCBCBC.

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